With Transition Detector Patents (Class 375/360)
  • Publication number: 20040151260
    Abstract: The invention provides a method for recovering a digital datastream (301), in which a reference clock phase (308) is recovered from the digital datastream (301), the digital datastream (301) being received in a datastream receiver (302), low-pass filtered in a low-pass filter device (303), an edge position signal (309) being determined by comparing an amplitude of the low-pass filtered datastream (305) with a predeterminable threshold value (108) in an edge position detection device (304) and a phase deviation (111a) being determined from a time difference between a 0/1 threshold intersection point (109) of the threshold value (108) with a 0/1 data transition (101) or a −1/1 threshold intersection point (110) of the threshold value (108) with a −1/1 data transmission (102) and the target time of the control system (310) in a phase correction device (307), so that the phase deviation (111a) can be corrected with the phase correction offset (111b) in the phase correction device (307).
    Type: Application
    Filed: November 7, 2003
    Publication date: August 5, 2004
    Inventors: Thomas Duda, Torsten Hinz, Martin Renner
  • Patent number: 6757341
    Abstract: In a digital audio interface signal demodulating apparatus (DDAp) that adds a preamble (PA) and additional information (V, U, C, P) to a digital audio signal (Sda) and demodulates into a digital audio interface signal (Sdai) after subjected to bi-phase modulation for transmission, based on both of positive and negative edges of a reference clock (Src) having a frequency higher than twice a minimum inverse frequency (1/T) of said digital audio interface signal (Sdai) and not necessarily synchronizing with said digital audio interface signal (Sdai), a modulation period (nT) of the digital audio interface signal (Sdai) is decided, and a decision signal (Sj) is generated. Furthermore, based on the decision signal (Sj), the: preamble (PA) is detected, and based on the detected preamble (PA), an audio signal (Sda) is obtained from said decision signal (Sj) through demodulation.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: June 29, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Noriyuki Ema, Yasushi Nakajima
  • Publication number: 20040105517
    Abstract: In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predetermined set value, a signal for resetting the operation of a serial-parallel converter circuit included in a data processing unit is output, so as to control the output of received data. Thus, disconnection of the cable can be detected with low power consumption without providing a pull-up resistor and pull-down resistor and noise resistance can be improved.
    Type: Application
    Filed: November 20, 2003
    Publication date: June 3, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Tsuyoshi Ebuchi, Toru Iwata, Takefumi Yoshikawa
  • Patent number: 6738442
    Abstract: A synchronization method and apparatus for detecting and synchronizing asynchronous signal data pulses. The synchronization system passes individual data pulses through two parallel synchronization sub-circuits, alternating synchronization sub-circuits for each succeeding pulse, and combines the output of the parallel synchronization sub-circuits to create a single synchronous signal.
    Type: Grant
    Filed: January 19, 2000
    Date of Patent: May 18, 2004
    Assignee: Agere Systems Inc.
    Inventor: Eric Wilcox
  • Patent number: 6735255
    Abstract: A correlator for use in a timing recovery apparatus of a receiver in a multicarrier transmission system. The correlator locates the beginning of a data frame and initializes a pointer register with an address to a location within the receive signal buffer. Data is transferred to a signal converter from the receive signal buffer where the samples that are fed into the converter are determined by the address stored in the pointer register.
    Type: Grant
    Filed: February 29, 2000
    Date of Patent: May 11, 2004
    Assignee: 3Com Corporation
    Inventors: Kevin J. Smart, Scott A. Bevan, William Kurt Dobson, Trent Stoddard, Mark W. Christiansen
  • Publication number: 20040062331
    Abstract: The invention describes a baud rate generator for use in a sampled data system. This generator makes possible the sampling of asynchronous digital input data when its baud rate is not known, and does so without the use of phase-locked loop circuitry. The invention uses a digital counter to count the clock intervals between successive transitions in the digital input data. This process is repeated over a period of time sufficient to assure that recognizable recurring data patterns will occur in the data stream. The smallest interval recorded by the counter is captured and is directly related to the required sampling rate.
    Type: Application
    Filed: September 27, 2002
    Publication date: April 1, 2004
    Inventor: Roshan J. Samuel
  • Patent number: 6700903
    Abstract: A system and method for enabling an optical network unit (ONU) in a passive optical network to scramble data and send the scrambled data upstream to an optical line termination unit (OLT). In passive optical networks the clocks in the OLT and ONU are synchronized by recovering the clock from the data signal. However, the clocks may drift when no data transitions occur on a long string of data. In addition, the OLT may require data transitions to ensure proper adjusting of its receive threshold. In either circumstance, collectively called Loss of Synchronization, the data may not be received correctly by the receiver and the transmitter will need to resend the data. In the present invention, the transmitter will vary the seed used in the scrambling operation. The use of a different seed per each transmission significantly reduces the chances that a loss of synchronization will occur.
    Type: Grant
    Filed: May 22, 2000
    Date of Patent: March 2, 2004
    Assignee: Terawave Communications, Inc.
    Inventors: Edward W Boyd, Douglas R Puchalski, Barry A Perkins
  • Publication number: 20040028163
    Abstract: A data recovery system and method is disclosed, which comprises an oversampler, a phase detection circuit, a data pick circuit, a data overlap/skip detection circuit and a data correction circuit. The oversampler oversamples an input signal and thus generates oversampled signals. The phase detection circuit receives for detecting transitions of the oversampled signals and outputting a phase signal. The data pick circuit receives the phase signal, accordingly groups the oversampled signals into n groups and picks one group as an output data. The data overlap/skip detection circuit determines if data is overlapped or skipped according to the phase signal and the last phase signal. The data correction circuit corrects data when data is overlapped or skipped and outputs an accurate output data.
    Type: Application
    Filed: August 4, 2003
    Publication date: February 12, 2004
    Applicant: Realtek Semiconductor Corp.
    Inventors: Chao-Hsin Lu, Yi-Shu Chang, Shiu-Rong Tong, Kuang-Hsi Hsieh
  • Publication number: 20040017870
    Abstract: Techniques to determine and indicate the extent to which transitions of an input signal deviate from a desired transition region.
    Type: Application
    Filed: July 25, 2002
    Publication date: January 29, 2004
    Inventor: Casper Dietrich
  • Patent number: 6680970
    Abstract: Methods and systems for data rate detection for multi-speed embedded clock serial receivers are described. In one embodiment, a method of determining a data rate of a high speed serially transmitted data stream comprises statistically examining edge characteristics of the incoming data stream. Based on the edge characteristics, a signature is identified that is associated with the edge characteristics. Based on the identified signature, a data rate at which the data stream is being transmitted is determined. In one embodiment, a clock extraction/data recovery circuit is provided for recovering an embedded clock and data from a high speed serially transmitted data stream. The circuit comprises a phase comparator that is configured to receive a high speed serially transmitted data stream and output indicia whenever the data stream experiences a data transition. A voltage controlled oscillator (VCO) is connected with the phase comparator and provides a clock signal having clock edges.
    Type: Grant
    Filed: May 23, 2000
    Date of Patent: January 20, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Robert G. Mejia
  • Patent number: 6680988
    Abstract: For enabling a stable clock signal to be extracted from even an input signal of which the duty factor is made worse, there is presented a clock extraction circuit applicable to an optical signal receiver equipped in an apparatus for use in the optical data communication. The clock extraction circuit includes a rising edge differential circuit (12) for differentiating the input signal at the rising edge thereof, a first monostable multivibrator (13) for processing the output from the differential circuit (12), a second monostable multivibrator (14) for processing the output from the first monostable multivibrator (13), an OR gate (15) for carrying out the logical OR between the output signals from the first and second monostable multivibrators (13) and (14) and circuitry for variably varying output pulse width, which processes the result of the logical OR.
    Type: Grant
    Filed: March 17, 2000
    Date of Patent: January 20, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Masaaki Maeda, Yoshikazu Fujita
  • Patent number: 6677727
    Abstract: Method and apparatus for synchronizing communication between a battery and an electronic device are disclosed. Bytes consisting of a number of bits are transmitted between the electronic device and the battery. A predetermined bit sequence is appended to at least some of the bytes prior to transmission. The time interval between given shifts in the predetermined bit sequence is used to synchronize the communication.
    Type: Grant
    Filed: January 25, 2000
    Date of Patent: January 13, 2004
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Heino Wendelrup, Michael Kellerman, Johan Mercke, Kristoffer Ptasinski, Charles Forsberg, Jonas Bengtsson, Jan Rubbmark
  • Publication number: 20030227987
    Abstract: A method and a corresponding decoder for decoding a Manchester encoded binary data signal includes receiving the Manchester encoded binary data signal having a first sequence of central bit transitions and a second sequence of initial bit transitions. A local clock signal is generated, and the central bit transitions of the Manchester encoded binary data signal are determined. Determination of the central bit transitions includes measuring the time interval elapsing between a pair adjacent central bit transitions, expressed as a number N of cycles of the local clock signal, and selecting each successive central bit transition based upon the time interval N measured between the pair of central bit transitions which immediately precede the successive central bit transition.
    Type: Application
    Filed: March 21, 2003
    Publication date: December 11, 2003
    Applicant: STMicroelectronics S.r.I.
    Inventors: Vanni Poletto, Paolo Ghigini
  • Patent number: 6636574
    Abstract: A method for estimating Doppler spread in mobile wireless communication devices, for example in CDMA or W-CDMA cellular communication systems, with improved noise immunity. The Doppler spread estimation is based on an estimated value of an autocorrelation or autocovariance at a first lag (210) and at a second lag (220), the magnitude of which is greater than the first lag. A first ratio is determined (250) between a first difference (230) and a second difference (240). The estimated Doppler spread is generally proportional to a square root (260) of the first ratio, and is scaled (270) by a multiplicative factor that depends on whether the estimated function is an autocorrelation or autocovariance function.
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: October 21, 2003
    Assignee: Motorola, Inc.
    Inventors: Alexandre Mallette, John Paul Oliver
  • Patent number: 6633620
    Abstract: In a data receiver, pulse edges are sequentially detected from the pulse string. If a pulse which has a width equal to two cycles of the reference clock signals is detected, bit data ‘1’ is restored. If two consecutive pulses each of which has a width equal to one cycle are detected, bit data ‘0’ is restored. If a pulse width between two consecutive pulse edges is not equal to one cycle or two cycles, it is presumed that a pulse edge of an erroneous pulse is detected. If the pulse width between the pulse edge, which is presumed to correspond to the erroneous pulse, and the next pulse edge is equal to or shorter than a predetermined threshold Th, the pulse edge and the next pulse edge is invalidated.
    Type: Grant
    Filed: December 5, 2001
    Date of Patent: October 14, 2003
    Assignee: Denso Corporation
    Inventors: Akihiro Taguchi, Hiroyuki Tsuji
  • Patent number: 6628212
    Abstract: A method and apparatus for a state-driven decoder for decoding a Manchester encoded signal. The decoder comprises an input sampling stage, an over-sampling clock, and a digital logic state machine. The over-sampling clock operates at a frequency which is less than five times the data rate of the encoded signal. The input sampling stage asynchronously samples the encoded signal at the frequency of the over-sampling clock and a produces a stream of pulse samples. The digital logic state machine analyzes the stream of pulse samples in groups and based on the logic levels of each group of pulse samples generates an output bit corresponding to the decoded Manchester signal.
    Type: Grant
    Filed: November 21, 2000
    Date of Patent: September 30, 2003
    Assignee: Nortel Networks Limited
    Inventor: Roger Toutant
  • Patent number: 6603829
    Abstract: In a phase matching circuit for generating a system clock signal for an incoming data signal from a locally existing clock signal, a delay signal is calculated from the detected phase position of the data signal in that a memory addressed with the detected phase position outputs an allocated delay signal. In a specific embodiment, the memory is supplied with an address that is compensated by the most recently identified delay. In a further development, a control comprising the memory shares circuits for a number of data signals. The phase matching, which automatically recognizes a jitter compatibility more suitable for the clocking than the jitter compatibility employed at the moment, can be completely integrated and avoids circuit areas that are operated with a higher bit repetition rate than that of the clock signal.
    Type: Grant
    Filed: October 22, 1999
    Date of Patent: August 5, 2003
    Assignee: Siemens Aktiengesellschaft
    Inventors: Winfried Gläser, Rudi Müller
  • Patent number: 6597752
    Abstract: A method for a cellular telephone receiver to detect the presence of a dotting sequence for a Manchester encoded cellular signal in a deep fading environment, wherein the presence of a single edge transition during the mask pulse for a predetermined number of consecutive clock cycles and the absence of any transition edges outside of the mask pulse for the predetermined number of consecutive clock cycles, indicate the presence of a dotting sequence and that the cellular receiver locked to a masked edge, thereby preventing the receiver from receiving the signal. In response, the receiver will shift the phase of its clock by 180 degrees so that it can lock to an unmasked edge of the cellular signal and thereby receive the signal.
    Type: Grant
    Filed: February 24, 1999
    Date of Patent: July 22, 2003
    Assignee: Agere Systems Inc.
    Inventors: Feng Chen, David L. Price
  • Patent number: 6584163
    Abstract: A shared data and clock recovery circuit including a clock synthesizer for generating sampling signals having different phases, a multiple transition detector for receiving a data stream and sampling signals, and for detecting edges in a data stream in response to the sampling signals, a counter and accumulator for detecting the time occurrences and total number of edges, and for performing weighted average calculation to select one of the phases, a decision circuit for detecting the phase difference between a source clock and a local clock such that if the PPM difference between the source clock and the local clock is at least 200 PPM, then selection of a phase is based upon stored historical information, and if the PPM difference between the source clock and the local clock is less than 200 PPM, then selection of a phase is based on a weighted averaging calculation.
    Type: Grant
    Filed: May 27, 1999
    Date of Patent: June 24, 2003
    Assignee: Agere Systems Inc.
    Inventors: Roy Thomas Myers, Jr., Shankar Ranjan Mukherjee, Jules Joseph Jelinek
  • Patent number: 6570944
    Abstract: An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing reference signal. The data-sampling signal may be provided by adjustably delaying a clock signal according to the phase information acquired from the strobe signal. The data-sampling signal may also have an improved waveform compared to the timing reference signal, including a fifty percent duty cycle and sharp transitions. The phase information acquired from the timing reference signal may also be used for other purposes, such as aligning received data with a local clock domain, or transmitting data so that it arrives at a remote device in synchronism with a reference clock signal at the remote device.
    Type: Grant
    Filed: June 25, 2001
    Date of Patent: May 27, 2003
    Assignee: Rambus Inc.
    Inventors: Scott C. Best, Richard E. Warmke, David B. Roberts, Frank Lambrecht
  • Patent number: 6567486
    Abstract: A phase-modulated signal such as a quadrature phase-shift-keyed (QPSK) signal in a wireless communication system is demodulated by frequency demodulating the phase-modulated signal. The phase-modulated signal is separated into first and second copies, the first copy is phase demodulated to generate demodulated symbols, and the second copy is frequency demodulated to generate, e.g., a measure of the instantaneous frequency of the phase-modulated signal. The instantaneous frequency measure is processed to identify one or more symbol transitions, and the identified transitions are used to generate event signals having signature properties (signature events). These signature events are used in traditional Time Difference of Arrival tdoa algorithms to accurately determine position of a mobile unit in the wireless communication system.
    Type: Grant
    Filed: July 26, 1999
    Date of Patent: May 20, 2003
    Assignee: Lucent Technologies Inc.
    Inventors: Alexander Gordon, Alex Matusevich, Jonathan Tobias, Sheng-Jen Tsai, Robert C. Wang
  • Patent number: 6567487
    Abstract: The invention relates to a method for the sampling of biphase coded digital signals by reception means which have at least one signal input having switchable signal edge sensitivity or at least two signal inputs having different signal edge sensitivity for the reception of such signals. The signals to be received are sampled precisely once per data bit, namely during the transmission of the first half-bit. The signal edges (F1-F5) of each bit are utilized for synchronizing the signal input with the control signal and for detecting transmission errors. Each signal sampling (S1-S5) is followed by a time window (&Dgr;t) within which the reception of the signal edge of the present bit is expected and evaluated as permissible. The signal edge sensitivity of the at least one signal input is set as a function of the sampled logic level of the first half-bit of the respectively transmitted bit of the signal.
    Type: Grant
    Filed: July 11, 2000
    Date of Patent: May 20, 2003
    Assignee: Patent-Treuhand-Gesellschaft fuer Elektrische Gluehlampen mbH
    Inventor: Axel Pilz
  • Publication number: 20030091137
    Abstract: There is disclosed a transition detection, validation and memorization (TDVM) circuit that detects the position of a transition in a stream of serially transmitted binary data (bits) that are over sampled and generates a control signal indicating which sampled signal represents the best the data. The incoming data stream is over sampled by the n phases of a multiple phase clock signal. The frequency of the multiphase clock signal is the same or half of the frequency of the incoming data for stability reasons. The n over sampled signals (S) are fed in the TDVM circuit which is comprised of three sections. The first section detects the transition at the positions of two consecutive sampled signals according to a specific signal processing which requires to perform twice, three comparisons on six consecutive over sampled signals (the central one being excluded at each time). The second section validates the second detection as the transition position.
    Type: Application
    Filed: October 24, 2002
    Publication date: May 15, 2003
    Applicant: International Business Machines Corporation
    Inventors: Vincent Vallet, Philippe Hauviller
  • Publication number: 20030086517
    Abstract: There is disclosed a data recovery (DR) circuit including an over sampling (OS) circuit, a transition detection (TD) circuit and a sample selection/data alignment (SSDA) circuit. A multiphase clock generating circuit delivering n phases is coupled to each of these circuits. The OS circuit over samples the received digital data stream and produces n sampled signals at each clock period. The TD circuit is configured to detect a data transition (if any) and to generate n select signals, only one of which is active and represents a determined delay with respect to the transition position, indicating thereby which over sampled signal is the best to be retained. The SSDA circuit is configured to generate the recovered (retimed) data signal that is aligned with a predefined phase of said multiphase clock signal. The data recovery circuit is well adapted to high speed serial data communications between integrated circuits/systems on digital networks.
    Type: Application
    Filed: October 24, 2002
    Publication date: May 8, 2003
    Applicant: International Business Machines Corporation
    Inventors: Vincent Vallet, Philippe Hanviller
  • Patent number: 6560305
    Abstract: A frequency detection system for producing clock pulses having a frequency equal to the frequency of a stream of binary data. The system includes a voltage controlled oscillator for producing the clock pulses. The frequency of such clock pulses changes in accordance with a control signal. Each one of the clock pulses has four sequential, one-quarter period phases. Adjacent phases are separated by boundaries to divide each clock pulse period into four quadrants. A frequency detector is fed by detected edges of the stream of binary data and the clock pulses for producing the control signal in accordance with the difference in frequency between the frequency of the clock pulses and the frequency of the stream of binary data. A lock-out circuit prevents subsequent production of the control signal until a subsequently detected data edge crosses a different one of the boundaries.
    Type: Grant
    Filed: October 7, 1998
    Date of Patent: May 6, 2003
    Assignee: Analog Devices, Inc.
    Inventor: Rosamaria Croughwell
  • Patent number: 6549595
    Abstract: A serial communication system transfers respective first and second signals via respective parallel signal carriers from a transmitter circuit to a receiver circuit. In synchronization with a clock signal (150), the transmitter circuit (110) serially represents a combination of the clock signal and data bit(s) (160) of a data message as the first and second signals (130, 140). At a data bit boundary, the transmitter circuit effects a transition of the first signal (130) if the data bit to be transmitted has a first value and effects a transition of the second signal (140) if the data bit has a different second value. The receiver circuit (120) recovers the clock signal by detecting and combining signal transitions of the first and second signal, for instance using an XOR function, and recovers the data message from the first and/or the second signal.
    Type: Grant
    Filed: December 29, 1998
    Date of Patent: April 15, 2003
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Gerrit W. Den Besten, Marcellinus J. M. Pelgrom
  • Patent number: 6542552
    Abstract: A data transmitter according to the present invention includes driver, transmission line and receiver. The receiver includes a transition pulse generator for generating a transition pulse simultaneously with the transition of a data signal output from the driver. If an edge of an internal clock signal overlaps with the transition pulse being applied, then the receiver does not latch the data signal in synchronism with the edge of the internal clock signal. Instead, the receiver obtains and retains a data value opposite to the previous cycle one. On the other hand, while no transition pulses are being applied, the receiver latches the data signal normally responsive to the internal clock signal. Accordingly, the receiver can always accurately retain the very data transmitted through the transmission line, thus improving the reliability of the data received and realizing high-speed data transmission even if the internal clock signal has lagged with respect to the data signal.
    Type: Grant
    Filed: December 22, 1999
    Date of Patent: April 1, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takefumi Yoshikawa, Yutaka Terada
  • Patent number: 6542494
    Abstract: A frame period is specified by means of a predetermined signal; a management data transmission region is set in this frame period; and when common information to be transmitted from the control station in the management data transmission region is received at a plurality of communication stations, any of these communication stations performs processing for repeatedly transmitting the received common information, whereby when communications in a network system are controlled by a control station, a station incapable of directly making communication with a control station can be controlled satisfactorily.
    Type: Grant
    Filed: September 9, 1999
    Date of Patent: April 1, 2003
    Assignee: Sony Corporation
    Inventors: Shigeru Sugaya, Hidemasa Yoshida, Takanobu Kamo, Takehiro Sugita
  • Patent number: 6542559
    Abstract: A decoding method and apparatus include providing capability for decoding data symbols that were encoded in a transmitter by either a serial-concatenated code or turbo code in a parallel processing fashion. The receiver upon knowing the encoding method may reconfigure the selection of data symbols from a table (600) to accommodate the appropriate decoding process. Initially a data symbol estimate for a number of data symbols of a plurality of data symbols Xi, Yi, and Wi are determined. The estimates of data symbols Xi, Yi, and Wi passing to a first and second decision nodes (610, 620) include estimates for the variables in one or more encoding equations. A new estimate for the data symbol Xi is determined based on the estimate determined at the initial step and the new estimate for each occurrence of the data symbol Xi at the first and second decision nodes (610, 620).
    Type: Grant
    Filed: May 15, 2000
    Date of Patent: April 1, 2003
    Assignee: Qualcomm, Incorporated
    Inventor: Jack K. Wolf
  • Patent number: 6539063
    Abstract: The system for recovering symbol timing offset and carrier frequency error from an orthogonal frequency division multiplexed (OFDM) signal includes a receiver circuit for receiving an OFDM modulated signal representing a series of OFDM symbols, and providing a received signal to an output thereof. A peak development circuit is included for developing a signal having a plurality of signal peaks representing symbol boundary positions for each received OFDM symbol, where each of the signal peaks is developed responsive to an amplitude and phase correspondence produced between the leading and trailing portions of each of the received OFDM symbols. The system includes a circuit for enhancing the signal peak detectability, which includes a circuit for additively superimposing and then filtering the signal peaks, to produce an enhanced signal peak having an improved signal-to-noise ratio.
    Type: Grant
    Filed: February 18, 1999
    Date of Patent: March 25, 2003
    Assignee: Ibiquity Digital Corporation
    Inventors: Paul James Peyla, Joseph Bertram Bronder
  • Publication number: 20030053570
    Abstract: Logic apparatus filters noise signals on a signal line to a digital circuit. An edge detector determines one or more edges of the noise signals relative to a fast clock. Signals indicative of the edges asynchronously reset a timer; the timer clocks the latch of the signal line when the signal line is stable, and without noise signals detected by the edge detector, for a period defined by a slow clock. The slow clock is slower than the fast clock by several orders of magnitude. The edge detector may be constructed by one flip-flop and an XOR gate. A second flip flop couples to the signal line and the output of the timer to pass through the latched value of the signal line to the digital circuit when clocked by the timer.
    Type: Application
    Filed: July 24, 2001
    Publication date: March 20, 2003
    Inventors: Michael John Erickson, Bradley D. Winick, David R. Maciorowski
  • Patent number: 6529459
    Abstract: A method for extracting binary data conveyed by an incident signal is provided in which the binary data is coded in the form of a pulsatile signal whose pulses have variable lengths which are multiples of a base pulse length 1T. The incident signal may include a succession of transitions whose spacings are representative of the lengths of the pulses. The method may include an initialization phase in which the value of a base distance corresponding to the base pulse length is determined from the contents of the incident signal, and an extraction phase in which a set of reference values corresponding respectively to various multiples of the determined base distance is formulated. For a calculated current distance, the values of the data corresponding to this current distance may be determined from a comparison between the reference values and a current corrected distance.
    Type: Grant
    Filed: September 27, 2000
    Date of Patent: March 4, 2003
    Assignee: STMicroelectronics S.A.
    Inventor: Fritz Lebowsky
  • Patent number: 6498537
    Abstract: A phase comparison circuit capable of realizing high-speed response by the PLL circuit in order to realize high-speed reproduction of the signals. An input signal is delayed by a delay buffer in order to produce a delayed signal. Changes in the level of the input signal are detected by a leading edge detection circuit and a falling edge detection circuit, a first and a second edge detection signals are output a control circuit changes the level of an output signal according to these detection signals, a phase comparison circuit compares the phases of the output from the control circuit and the clock signal, and a first and a second control signals are output according to the comparison result.
    Type: Grant
    Filed: March 12, 1999
    Date of Patent: December 24, 2002
    Assignee: Texas Instruments Incorporated
    Inventor: Seiji Watanabe
  • Patent number: 6490704
    Abstract: The invention relates to a digital radio system and to a method for correcting a synchronization error in a digital radio system comprising at least one base station (100) communicating with terminals (102, 104) in its coverage area, and a mobile telephone exchange (108) communicating with the base station and controlling the operation of the base stations. The information to be transmitted is coded and decoded in a transcoder unit (200) into a form suitable for the transmission. The base station sends information frames to the transcoder at a certain pace, and, correspondingly, the transcoder sends information frames to the base station at a certain pace. To ensure easy transmission of information and to increase flexibility, the base station (100) indicates in an information frame sent to the transcoder (200) the synchronization error present in the information frames coming from the transcoder, and the transcoder corrects its synchronization after receiving said message.
    Type: Grant
    Filed: November 5, 1999
    Date of Patent: December 3, 2002
    Assignee: Nokia Networks Oy
    Inventor: Antti Ropponen
  • Patent number: 6487263
    Abstract: A digital circuit generates a phase synchronization signal for a digital input signal coded according to a biphase modulation. The phase synchronization signal is derived from a clock signal having a higher frequency than the maximum switching frequency of the digital input signal. The frequency of the clock signal is divided with a fully digital divider circuit having a non-integer ratio. The divider is self-synchronizing with the input digital signal. Control signals are used to enable or disable switching of the frequency divider. These control signals are generated by two circuits which sample the input signal with the master clock signal and analyze triplets of consecutive sampling values.
    Type: Grant
    Filed: December 2, 1998
    Date of Patent: November 26, 2002
    Assignee: STMicroelectronics S.r.l.
    Inventors: Marco Bianchessi, Sandro Dalle Feste, Nadia Serina, Marco Angelici
  • Publication number: 20020146084
    Abstract: The architecture and the method of operation of a receiver core are described. The core performs clock and data recovery on an incoming serial data stream transmitted across a wired media, such as a chip-to-chip or card-to-card interconnect. The bit error rate and accuracy of the recovery are optimized without centering of oversampling. Further, random errors due to edge mis-tracking are minimized. The receiver utilizes a phase rotator to detect the edge position of the bits of the data stream, select the optimum data sample and generate early and late signals if the detected edge is not in the expected position. A phase locked loop provides a frequency source for the phase rotator. At least three evenly spaced samples are detected for each bit. A sample processing algorithm, preferably an adaptive behavior algorithm, is used for centering the bit edge between two of the samples.
    Type: Application
    Filed: November 28, 2001
    Publication date: October 10, 2002
    Applicant: International Business Machines Corporation
    Inventors: Hayden Clavie Cranford, Vernon Roberts Norman, Martin Leo Schmatz
  • Patent number: 6463092
    Abstract: The system preferably includes a unique transmitter that sends both clock and data signals over the same transmission line. The receiver uses the same transmission line to send data signals back to the transmitter. The transmitter comprises a clock generator, a decoder and a line interface. The clock generator produces a clock signal that includes a variable position falling edge. The falling edge position is decoded by the receiver to extract data from the clock signal. The receiver comprises a clock re-generator, a data decoder and a return channel encoder. The clock re-generator monitors the transmission line, receives signals, filters them and generates a clock signal at the receiver from the signal on the transmission line. The return channel encoder generates signals and asserts them on the transmission line. The signal is asserted or superimposed over the clock & data signal provided by the transmitter.
    Type: Grant
    Filed: September 9, 1999
    Date of Patent: October 8, 2002
    Assignee: Silicon Image, Inc.
    Inventors: Gyudong Kim, Min-Kyu Kim, Seung Ho Hwang
  • Patent number: 6460001
    Abstract: An input clock signal is transformed into a complex analytic signal zc(t) by an analytic signal transforming means 13 and an instantaneous phase of its real part xc(t) is estimated using the analytic signal zc(t). A linear phase is removed from the instantaneous phase to obtain a phase noise waveform &Dgr;&phgr;(t). A peak value &Dgr;&phgr;max of absolute values of the &Dgr;&phgr;(t) is obtained, and 4&Dgr;&phgr;max is defined as the worst value of period jitter of the input signal. The &Dgr;&phgr;(t) is sampled at a timing close to a zero-crossing point of the xc(t) to extract the sample value. A differential between adjacent samples is obtained in the sequential order to calculate a root-mean-square value of the differentials (period jitters). An exp(−(2&Dgr;&phgr;max)2/(2&sgr;j2)) is calculated from the mean-square value &sgr;j and 2&Dgr;&phgr;max, and the calculated value is defined as a probability that a period jitter exceeds 2&Dgr;&phgr;max.
    Type: Grant
    Filed: March 29, 2000
    Date of Patent: October 1, 2002
    Assignee: Advantest Corporation
    Inventors: Takahiro Yamaguchi, Masahiro Ishida, Mani Soma
  • Patent number: 6452990
    Abstract: A magnetic disk drive data storage disk defines recording tracks divided into data sectors by narrow servo spokes. A data sector lying between servo spokes is recorded with user data encoded in accordance with a code having a predetermined distance and user data code rate. Each servo spoke of the recording area has at least one servo information field encoded in a wide bi-phase code pattern. The disk drive further includes a synchronous sampling data detection channel having a data transducer head positioned by a servo-controlled actuator over the recording track, a preamplifier for receiving electrical analog signals magnetically induced by the data transducer head from flux transitions present in at least the servo information field, a digital sampler for synchronously sampling the electrical analog signals to produce digital samples, and wide bi-phase decoding circuitry coupled to receive digital samples from the synchronous sampling data detection channel for decoding the wide bi-phase code pattern.
    Type: Grant
    Filed: January 27, 1999
    Date of Patent: September 17, 2002
    Assignee: Maxtor Corporation
    Inventors: Michael D. Leis, Ara Patapoutian, Mathew P. Vea, Richard M. Ehrlich, Kevin D. Fisher, James A. Henson, William R. Akin, Jr.
  • Patent number: 6449078
    Abstract: An optical receiver of the present invention comprises a photodiode receiving an optical signal and converting it into an electric signal, a signal edge detector generating an edge signal from the electric signal, a quantizing circuit generating a signal quantized on the basis of the edge signal, and a variable gain amplifier amplifying an output signal from the photodiode so that the amplitude of the edge signal may become constant, and has the structure of an output signal of the variable gain amplifier being inputted to the quantizing circuit. In addition, a spatial optical transmitter has the structure of making a transmission band twice by using polarized light mutually orthogonal.
    Type: Grant
    Filed: August 5, 1998
    Date of Patent: September 10, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Satoshi Hirotsune
  • Patent number: 6445753
    Abstract: A method and a circuit configuration deactivate an input of a receiving circuit when a first edge occurs, during processing of a digital input signal. When a falling edge occurs, the input is only reactivated after a delay. An influence of signal interference and incorrect interpretations of the signal can thereby be reduced. The method and circuit configuration are employed in particular with clock signals in which only one edge is used for signal evaluation.
    Type: Grant
    Filed: August 4, 1998
    Date of Patent: September 3, 2002
    Assignee: Infineon Technologies AG
    Inventor: Martin Buck
  • Patent number: 6415008
    Abstract: An electronic circuit that multiplies an input signal using primarily digital components so that the resulting circuit can be fabricated consistently by different foundries. The circuit determines a period for the input signal and converts the period to a digital number (e.g., a binary number). An adder is used to determine an average period over a predetermined number of cycles. By determining the average period, voltage fluctuations are cancelled. A multiplier allows for a variable multiplication of the averaged period. A clock generating circuit uses the results obtained by the multiplier to generate a multiplied output signal. Additionally, the input signal is routinely multiplexed with the generated output signal to ensure phase matching.
    Type: Grant
    Filed: December 15, 1998
    Date of Patent: July 2, 2002
    Inventors: Roland Albert Béchade, Ronald Joseph Cheponis
  • Patent number: 6411665
    Abstract: A clock recovery circuit includes a phase locked loop in which the control voltage of a voltage controlled oscillator is controlled by a loop filter driven by the output of a phase comparator. During acquisition of the phase locked condition, a frequency error detector is used to detect frequency error and input a frequency error signal to a charge pump circuit associated with the loop filter. Frequency error is detected by a method of determining the phase quadrant of clock signal in which each transition of the data occurs, an algorithm implemented by logic circuit being utilized to selectively generate the frequency error signal only for certain defined transitions between phase quadrant values. Sampling of the phase quadrant values is effected by sampling sub-circuits using latched values of the clock and quadrature clock signals to obtain samples of the clock and quadrature clock signals for each transition, and subsequently determining the phase quadrant value by a logical combination of the samples.
    Type: Grant
    Filed: March 11, 1999
    Date of Patent: June 25, 2002
    Assignee: Nortel Networks Limited
    Inventors: Joseph Chan, Richard Francis Bastable
  • Publication number: 20020048334
    Abstract: When the number of transmit bits and gain allocated to each carrier of a multicarrier transmission system are decided, the S/N ratio of each carrier is found and a number of transmit bits is allocated to each of the carriers based upon the respective S/N ratios thereof. Next, the gains of carriers for which the number of allocated bits is equal to a maximum limit number are decreased and the gains of prescribed carriers other than these carriers are increased. Control is performed in such a manner that the sum total of gain increases and sum total of gain decreases will be equal, as a result of which the total of number of transmit bits allocated to the carriers is increased.
    Type: Application
    Filed: March 12, 2001
    Publication date: April 25, 2002
    Inventor: Kazutomo Hasegawa
  • Patent number: 6359943
    Abstract: In accordance with this invention, a data capture circuit of a data receiver captures data from a data stream of a data transmitter operating at a different phase or frequency from the system clock of the data receiver. In one embodiment, the data receiver determines the number of clock periods of a clock signal in a data period of the data stream. Specifically, a signal detection circuit receives a signal having a periodic and distinctive feature. The period of the periodic and distinctive feature is related to the data period by a fixed scaling factor. A counter counts the number of clock periods of the clock signal between a first occurrence of the periodic and distinctive feature and a second occurrence of the periodic and distinctive feature. A multiplier/divider circuit divides or multiples the content of the first counter by the scaling factor to determine the integer clock period count. The results of the multiply or divide is stored in a count register.
    Type: Grant
    Filed: December 13, 1999
    Date of Patent: March 19, 2002
    Assignee: Integrated Memory Logic, Inc.
    Inventor: Wei-Chi Lo
  • Publication number: 20020025013
    Abstract: A device and a method for detecting a period of an input signal includes a count value setting portion to set a reference clock to be counted by n times; an A/D converter to sample an analog input signal at each period of the reference clock, and convert the signal into digital values having (+) and (−) symbols; a zero cross point detecting portion to detect a change of (+) and (−) symbols of the digital values received from the A/D converter, and output the detected signal; a arithmetic processing unit to divide two sampling sectors having a zero cross point in their center by a preset value which is set in the count value setting portion, predict a zero cross point sector based on the digital values of two sampling points, and calculate a count value of the reference clock in accordance with the predicted zero cross point sector and the preset value which is set in the count value setting portion; a counter to accumulate the count values of each reference clock, which are calculated fr
    Type: Application
    Filed: July 30, 2001
    Publication date: February 28, 2002
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-wook Lee, Dae-yun Shim
  • Patent number: 6339412
    Abstract: A stabilizing circuit for stabilizing a horizontal transistor of a video display device. The stabilizing circuit includes a transient state detector for detecting a transient state of a phase locked loop circuit in a horizontal drive circuit due to a change in an operation mode of a video card in a computer system. A micro-computer outputs vertical and horizontal synchronous signals with frequencies before the change in the operation mode of the video card when the transient state detector detects the transient state of the phase locked loop circuit. The transient state detector detects the transient state of the phase locked loop circuit according to a direct current level variation based on a phase difference between a horizontal synchronous signal from the micro-computer and a horizontal drive signal from the phase locked loop circuit.
    Type: Grant
    Filed: June 16, 1997
    Date of Patent: January 15, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ji-Young Lee
  • Patent number: 6307904
    Abstract: An edge detector (10) detects edges of clock pulses in a digital signal and provides edge detect pulses to a state corrector (20). A state sequencer (15) receives a clock signal and steps through a sequence of states in accordance with the clock signal to generate a recovered clock signal which is substantially synchronized with the clock pulses in the digital signal. The state corrector (20) selectively providing reset states to reset the state sequencer in accordance with various parameters to maintain synchronization between the clock pulses in the digital signal and the recovered clock signal. The state corrector (20) also inhibits resetting the state sequencer (15) when edge detect pulse produced from instability in the edge detector (10) are received.
    Type: Grant
    Filed: January 14, 1999
    Date of Patent: October 23, 2001
    Assignee: Motorola. Inc.
    Inventors: Shih Sheng Hu, Chien Yu Lai
  • Publication number: 20010028686
    Abstract: Apparatus, and an accompanying method, for transmitting a frame synchronization signal and a data signal simultaneously through a serial transmission medium (170). Specifically within a data transmitter (105), a frame synchronization signal, a clock signal and a data signal, are encoded to form a single bi-phase mark signal having the frame synchronization signal incorporated into the bi-phase mark signal as a phase-shift. The bi-phase mark signal is then transmitted through a suitable serial transmission medium. A receiver (175), connected to the transmission medium, receives and amplifies an incoming bi-phase mark signal appearing on the medium, and, in turn, synthesizes the clock, frame synchronization, and data signals from this bi-phase mark signal.
    Type: Application
    Filed: May 1, 2001
    Publication date: October 11, 2001
    Applicant: Siemens Information and Communications Networks, Inc.
    Inventor: Glenn L. Richards
  • Publication number: 20010022824
    Abstract: An object of the present invention is to provide a delay apparatus which can delay not only a rising edge but also falling edge of the digital signal for a predetermined delay period of time.
    Type: Application
    Filed: March 16, 2001
    Publication date: September 20, 2001
    Inventor: Satoru Araki