Abstract: Methods and corresponding apparatus to recover data from a signal comprising groups of pulses generated in response to analog waveforms are described. Data recovery in accordance with the invention is based on parameters characterizing the groups of pulses. These parameters are the basis for mapping the groups of pulses to information symbols which collectively constitute the data to be recovered.

Abstract: The invention concerns a radio-frequency transponder (12) for contact-free identification with a reader (10), comprising: an antenna (24), an analog circuit (25) including a capacitor (32) an AC-DC converter (34), a modulator (40) and a demodulator (38), a logic control circuit (26), a storage unit (27). Said transponder (12) is designed such that: the antenna (24) and the capacitor (32) form together a resonant circuit, the clock extractor (36) processes the first signal (Tx) to extract therefrom a clock signal addressed to said modulator (38) as long as the voltage of said signal (Tx) exceeds a first threshold value, the converter (34) transforms the first signal (Tx) into a rectified signal, to power the transponder (12). The performances of the transponder, and more particularly energy recuperation and data transmission rate, are improved by the fact that the analog circuit comprises two clock extractors, one of low level type (35), the other of the high level type (36).

Abstract: The system for recovering symbol timing offset and carrier frequency error from an orthogonal frequency division multiplexed (OFDM) signal includes a receiver circuit for receiving an OFDM modulated signal representing a series of OFDM symbols, and providing a received signal to an output thereof. A peak development circuit is included for developing a signal having a plurality of signal peaks representing symbol boundary positions for each received OFDM symbol, where each of the signal peaks is developed responsive to an amplitude and phase correspondence produced between the leading and trailing portions of each of the received OFDM symbols. The system includes a circuit for enhancing the signal peak detectability, which includes a circuit for additively superimposing and then filtering the signal peaks, to produce an enhanced signal peak having an improved signal-to-noise ratio.

Abstract: A wireless receiver e.g., a Bluetooth-compatible receiver or a receive chain in a Bluetooth-compatible transceiver, includes a discriminator unit and a timing recovery unit. The output of the discriminator unit is provided as an input to the timing recovery unit, which timing recovery unit is configured to align a free-running clock of the receiver with a received signal to extract received data therefrom.

Abstract: A bit synchronizing circuit used in a reception circuit for serial communication comprises a data sampling circuit for over-sampling inputted data, a change point detecting circuit for detecting a change point of the inputted data based on an output from the data sampling circuit, a change point holding circuit for changing a held value stepwise in the case where the output from the change point detecting circuit is different from the held data, a selected value setting circuit for determining which value of the data sampling circuit is to be selected based on the output of the change point holding circuit and a data selecting circuit for selecting the data from the data sampling circuit based on the output of the selected value setting circuit. It alternatively may comprise a data sampling circuit for over-sampling the bit data, a synchronizing circuit, a change point detecting circuit, and a data selecting circuit.

Abstract: Method and apparatus for recovering a clock and data from a data signal. One method of the invention includes receiving the data signal having a first data rate, receiving the clock signal having a first clock frequency, alternating between a first level and a second level, wherein the first data rate is twice the first clock frequency. A first signal is generated by passing the data signal when the clock signal is at the first level, and storing the data signal when the clock signal is at the second level. A second signal is generated by passing the data signal when the clock signal is at the second level, and storing the data signal when the clock signal is at the first level. A third signal is generated by passing the first signal when the clock signal is at the second level, and storing the first signal when the clock signal is at the first level.

Abstract: A method of channel estimation in a Code Division Multiple Access (CDMA) transmission system that incorporates Pilot Symbol Assisted Modulation (PSAM) using an iterative coherent detection method to estimate the phase and frequency of the received pilot symbols. Arctangent calculations are used to estimate phase and frequency. An iterative least squares linearization identifies and corrects values of the arctangent associated with an incorrect 2? alias, which arise due to the multiple-valued nature of the arctangent function. An alternative non-iterative least squares linearization also corrects the arctangent values, based on a calculation involving stored values of the pilot symbols.

Abstract: A host interface includes transition detection circuitry, transition phase averaging circuitry, and bit stream sampling circuitry. The transition detection circuitry receives an incoming bit stream and a reference clock signal and detects transitions of the incoming bit stream with respect to the reference clock signal. The transition detection circuitry also determines relative phases of the transitions with respect to the reference clock signal. The transition phase averaging circuitry determines an average relative phase of the detected transitions with respect to the reference clock signal and also determines, based upon the average relative phase of the detected transitions with respect to the reference clock signal, a sampling phase with respect to the reference clock signal. The bit stream sampling circuitry samples the incoming bit stream at the sampling phase with respect to the reference clock signal to extract the bit values. The incoming bit stream may comply with the Universal Serial Bus 2.

Abstract: An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing reference signal. The data-sampling signal may be provided by adjustably delaying a clock signal according to the phase information acquired from the strobe signal. The data-sampling signal may also have an improved waveform compared to the timing reference signal, including a fifty percent duty cycle and sharp transitions. The phase information acquired from the timing reference signal may also be used for other purposes, such as aligning received data with a local clock domain, or transmitting data so that it arrives at a remote device in synchronism with a reference clock signal at the remote device.

Abstract: The invention is related to analog to digital conversion of a multi-level analog signal at a very low sampling rate. The analog signal is sampled by a recovered clock to produce a succession of samples of the analog signal. The low sampling rate may be within an order of magnitude of the symbol rate of the analog signal. Each sample is converted to a digital word. A phase detector reference circuit determines from peak values of the analog signal at least two allowable levels of the analog signal including a reference-crossing level. The phase detector defines a zero band of amplitude ranges of the analog signal including the reference-crossing level. It further defines an error band of amplitude ranges of the analog signal extending from said zero band to a fraction of the amplitude of the next allowable level. The phase detector then infers either a positive or negative phase error for each pair of successive samples of the analog signal.

Abstract: In a method for detecting a varying data rate in a data signal, with which data signal a bit is transmitted in the form of a signal edge generated at a particular nominal time, after triggering by an interrupt signal (IS) generated in an analog/digital converter (13), the times of occurrence (TA, TB, TC, TD) of the signal edges are detected and subsequently the edge intervals (T1, T2) determined from the times of occurrence (TA, TB, TC, TD) of the signal edges and subsequently the mean edge interval (Tm) determined from the determined edge intervals (T1, T2). From the mean edge interval (Tm) and a tolerance range of the mean edge interval (Tm) are determined an upper time of occurrence limit (OAZ) and a lower time of occurrence limit (UAZ), within which upper and lower time of occurrence limit a subsequent signal edge must occur in order to be valid for the detection of a current data rate from the mean edge interval (Tm).

Abstract: In a clock extracting circuit according to the present invention, after serial data is subjected to oversampling using a reference clock of 2N times a frequency of the serial data, clock timing in a period of time in which signal level remains unchanged for a long duration is extracted by first timing detecting means. Clock timing based on a point of change in the signal level is extracted by second timing detecting means, and a final clock timing signal is outputted according to these timings detected. Thus, clock timing can be extracted accurately without omission even when the input signal includes jitter. Further, the clock extraction is performed without converting the input signal into parallel data and by simple processing. A clock extracting circuit for extracting a clock signal from the received serial data with high accuracy is thus realized without increasing the circuit scale.

Abstract: A clock recovery circuit which has a transition detector connected to the incoming data stream. An output of the transition detector is connected to a gate, such as a D flip-flop, which has an input receiving the recovered clock. A zero or one output will be generated depending upon whether the transition is before or after the rising edge of the recovered clock. An accumulator circuit accumulates a count for each transition, providing the results to a comparison circuit. The comparison circuit compares the accumulated count to maximum and minimum thresholds, and provides advance or retard outputs when those thresholds are exceeded. A phase circuit adjusts the phase of the recovered clock by advancing or retarding it after a sufficient number of transitions have been detected either in advance or behind the recovered clock to justify such an adjustment.

Abstract: The invention provides a method for recovering a digital datastream (301), in which a reference clock phase (308) is recovered from the digital datastream (301), the digital datastream (301) being received in a datastream receiver (302), low-pass filtered in a low-pass filter device (303), an edge position signal (309) being determined by comparing an amplitude of the low-pass filtered datastream (305) with a predeterminable threshold value (108) in an edge position detection device (304) and a phase deviation (111a) being determined from a time difference between a 0/1 threshold intersection point (109) of the threshold value (108) with a 0/1 data transition (101) or a −1/1 threshold intersection point (110) of the threshold value (108) with a −1/1 data transmission (102) and the target time of the control system (310) in a phase correction device (307), so that the phase deviation (111a) can be corrected with the phase correction offset (111b) in the phase correction device (307).

Abstract: In a digital audio interface signal demodulating apparatus (DDAp) that adds a preamble (PA) and additional information (V, U, C, P) to a digital audio signal (Sda) and demodulates into a digital audio interface signal (Sdai) after subjected to bi-phase modulation for transmission, based on both of positive and negative edges of a reference clock (Src) having a frequency higher than twice a minimum inverse frequency (1/T) of said digital audio interface signal (Sdai) and not necessarily synchronizing with said digital audio interface signal (Sdai), a modulation period (nT) of the digital audio interface signal (Sdai) is decided, and a decision signal (Sj) is generated. Furthermore, based on the decision signal (Sj), the: preamble (PA) is detected, and based on the detected preamble (PA), an audio signal (Sda) is obtained from said decision signal (Sj) through demodulation.

Abstract: In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predetermined set value, a signal for resetting the operation of a serial-parallel converter circuit included in a data processing unit is output, so as to control the output of received data. Thus, disconnection of the cable can be detected with low power consumption without providing a pull-up resistor and pull-down resistor and noise resistance can be improved.

Abstract: A synchronization method and apparatus for detecting and synchronizing asynchronous signal data pulses. The synchronization system passes individual data pulses through two parallel synchronization sub-circuits, alternating synchronization sub-circuits for each succeeding pulse, and combines the output of the parallel synchronization sub-circuits to create a single synchronous signal.

Abstract: A correlator for use in a timing recovery apparatus of a receiver in a multicarrier transmission system. The correlator locates the beginning of a data frame and initializes a pointer register with an address to a location within the receive signal buffer. Data is transferred to a signal converter from the receive signal buffer where the samples that are fed into the converter are determined by the address stored in the pointer register.

Abstract: The invention describes a baud rate generator for use in a sampled data system. This generator makes possible the sampling of asynchronous digital input data when its baud rate is not known, and does so without the use of phase-locked loop circuitry. The invention uses a digital counter to count the clock intervals between successive transitions in the digital input data. This process is repeated over a period of time sufficient to assure that recognizable recurring data patterns will occur in the data stream. The smallest interval recorded by the counter is captured and is directly related to the required sampling rate.

Abstract: A system and method for enabling an optical network unit (ONU) in a passive optical network to scramble data and send the scrambled data upstream to an optical line termination unit (OLT). In passive optical networks the clocks in the OLT and ONU are synchronized by recovering the clock from the data signal. However, the clocks may drift when no data transitions occur on a long string of data. In addition, the OLT may require data transitions to ensure proper adjusting of its receive threshold. In either circumstance, collectively called Loss of Synchronization, the data may not be received correctly by the receiver and the transmitter will need to resend the data. In the present invention, the transmitter will vary the seed used in the scrambling operation. The use of a different seed per each transmission significantly reduces the chances that a loss of synchronization will occur.

Abstract: A data recovery system and method is disclosed, which comprises an oversampler, a phase detection circuit, a data pick circuit, a data overlap/skip detection circuit and a data correction circuit. The oversampler oversamples an input signal and thus generates oversampled signals. The phase detection circuit receives for detecting transitions of the oversampled signals and outputting a phase signal. The data pick circuit receives the phase signal, accordingly groups the oversampled signals into n groups and picks one group as an output data. The data overlap/skip detection circuit determines if data is overlapped or skipped according to the phase signal and the last phase signal. The data correction circuit corrects data when data is overlapped or skipped and outputs an accurate output data.

Abstract: Techniques to determine and indicate the extent to which transitions of an input signal deviate from a desired transition region.

Abstract: For enabling a stable clock signal to be extracted from even an input signal of which the duty factor is made worse, there is presented a clock extraction circuit applicable to an optical signal receiver equipped in an apparatus for use in the optical data communication. The clock extraction circuit includes a rising edge differential circuit (12) for differentiating the input signal at the rising edge thereof, a first monostable multivibrator (13) for processing the output from the differential circuit (12), a second monostable multivibrator (14) for processing the output from the first monostable multivibrator (13), an OR gate (15) for carrying out the logical OR between the output signals from the first and second monostable multivibrators (13) and (14) and circuitry for variably varying output pulse width, which processes the result of the logical OR.

Abstract: Methods and systems for data rate detection for multi-speed embedded clock serial receivers are described. In one embodiment, a method of determining a data rate of a high speed serially transmitted data stream comprises statistically examining edge characteristics of the incoming data stream. Based on the edge characteristics, a signature is identified that is associated with the edge characteristics. Based on the identified signature, a data rate at which the data stream is being transmitted is determined. In one embodiment, a clock extraction/data recovery circuit is provided for recovering an embedded clock and data from a high speed serially transmitted data stream. The circuit comprises a phase comparator that is configured to receive a high speed serially transmitted data stream and output indicia whenever the data stream experiences a data transition. A voltage controlled oscillator (VCO) is connected with the phase comparator and provides a clock signal having clock edges.

Abstract: Method and apparatus for synchronizing communication between a battery and an electronic device are disclosed. Bytes consisting of a number of bits are transmitted between the electronic device and the battery. A predetermined bit sequence is appended to at least some of the bytes prior to transmission. The time interval between given shifts in the predetermined bit sequence is used to synchronize the communication.

Abstract: A method and a corresponding decoder for decoding a Manchester encoded binary data signal includes receiving the Manchester encoded binary data signal having a first sequence of central bit transitions and a second sequence of initial bit transitions. A local clock signal is generated, and the central bit transitions of the Manchester encoded binary data signal are determined. Determination of the central bit transitions includes measuring the time interval elapsing between a pair adjacent central bit transitions, expressed as a number N of cycles of the local clock signal, and selecting each successive central bit transition based upon the time interval N measured between the pair of central bit transitions which immediately precede the successive central bit transition.

Abstract: A method for estimating Doppler spread in mobile wireless communication devices, for example in CDMA or W-CDMA cellular communication systems, with improved noise immunity. The Doppler spread estimation is based on an estimated value of an autocorrelation or autocovariance at a first lag (210) and at a second lag (220), the magnitude of which is greater than the first lag. A first ratio is determined (250) between a first difference (230) and a second difference (240). The estimated Doppler spread is generally proportional to a square root (260) of the first ratio, and is scaled (270) by a multiplicative factor that depends on whether the estimated function is an autocorrelation or autocovariance function.

Abstract: In a data receiver, pulse edges are sequentially detected from the pulse string. If a pulse which has a width equal to two cycles of the reference clock signals is detected, bit data ‘1’ is restored. If two consecutive pulses each of which has a width equal to one cycle are detected, bit data ‘0’ is restored. If a pulse width between two consecutive pulse edges is not equal to one cycle or two cycles, it is presumed that a pulse edge of an erroneous pulse is detected. If the pulse width between the pulse edge, which is presumed to correspond to the erroneous pulse, and the next pulse edge is equal to or shorter than a predetermined threshold Th, the pulse edge and the next pulse edge is invalidated.

Abstract: A method and apparatus for a state-driven decoder for decoding a Manchester encoded signal. The decoder comprises an input sampling stage, an over-sampling clock, and a digital logic state machine. The over-sampling clock operates at a frequency which is less than five times the data rate of the encoded signal. The input sampling stage asynchronously samples the encoded signal at the frequency of the over-sampling clock and a produces a stream of pulse samples. The digital logic state machine analyzes the stream of pulse samples in groups and based on the logic levels of each group of pulse samples generates an output bit corresponding to the decoded Manchester signal.

Abstract: In a phase matching circuit for generating a system clock signal for an incoming data signal from a locally existing clock signal, a delay signal is calculated from the detected phase position of the data signal in that a memory addressed with the detected phase position outputs an allocated delay signal. In a specific embodiment, the memory is supplied with an address that is compensated by the most recently identified delay. In a further development, a control comprising the memory shares circuits for a number of data signals. The phase matching, which automatically recognizes a jitter compatibility more suitable for the clocking than the jitter compatibility employed at the moment, can be completely integrated and avoids circuit areas that are operated with a higher bit repetition rate than that of the clock signal.

Abstract: A method for a cellular telephone receiver to detect the presence of a dotting sequence for a Manchester encoded cellular signal in a deep fading environment, wherein the presence of a single edge transition during the mask pulse for a predetermined number of consecutive clock cycles and the absence of any transition edges outside of the mask pulse for the predetermined number of consecutive clock cycles, indicate the presence of a dotting sequence and that the cellular receiver locked to a masked edge, thereby preventing the receiver from receiving the signal. In response, the receiver will shift the phase of its clock by 180 degrees so that it can lock to an unmasked edge of the cellular signal and thereby receive the signal.

Abstract: A shared data and clock recovery circuit including a clock synthesizer for generating sampling signals having different phases, a multiple transition detector for receiving a data stream and sampling signals, and for detecting edges in a data stream in response to the sampling signals, a counter and accumulator for detecting the time occurrences and total number of edges, and for performing weighted average calculation to select one of the phases, a decision circuit for detecting the phase difference between a source clock and a local clock such that if the PPM difference between the source clock and the local clock is at least 200 PPM, then selection of a phase is based upon stored historical information, and if the PPM difference between the source clock and the local clock is less than 200 PPM, then selection of a phase is based on a weighted averaging calculation.

Abstract: An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing reference signal. The data-sampling signal may be provided by adjustably delaying a clock signal according to the phase information acquired from the strobe signal. The data-sampling signal may also have an improved waveform compared to the timing reference signal, including a fifty percent duty cycle and sharp transitions. The phase information acquired from the timing reference signal may also be used for other purposes, such as aligning received data with a local clock domain, or transmitting data so that it arrives at a remote device in synchronism with a reference clock signal at the remote device.

Abstract: The invention relates to a method for the sampling of biphase coded digital signals by reception means which have at least one signal input having switchable signal edge sensitivity or at least two signal inputs having different signal edge sensitivity for the reception of such signals. The signals to be received are sampled precisely once per data bit, namely during the transmission of the first half-bit. The signal edges (F1-F5) of each bit are utilized for synchronizing the signal input with the control signal and for detecting transmission errors. Each signal sampling (S1-S5) is followed by a time window (&Dgr;t) within which the reception of the signal edge of the present bit is expected and evaluated as permissible. The signal edge sensitivity of the at least one signal input is set as a function of the sampled logic level of the first half-bit of the respectively transmitted bit of the signal.

Abstract: A phase-modulated signal such as a quadrature phase-shift-keyed (QPSK) signal in a wireless communication system is demodulated by frequency demodulating the phase-modulated signal. The phase-modulated signal is separated into first and second copies, the first copy is phase demodulated to generate demodulated symbols, and the second copy is frequency demodulated to generate, e.g., a measure of the instantaneous frequency of the phase-modulated signal. The instantaneous frequency measure is processed to identify one or more symbol transitions, and the identified transitions are used to generate event signals having signature properties (signature events). These signature events are used in traditional Time Difference of Arrival tdoa algorithms to accurately determine position of a mobile unit in the wireless communication system.

Abstract: There is disclosed a transition detection, validation and memorization (TDVM) circuit that detects the position of a transition in a stream of serially transmitted binary data (bits) that are over sampled and generates a control signal indicating which sampled signal represents the best the data. The incoming data stream is over sampled by the n phases of a multiple phase clock signal. The frequency of the multiphase clock signal is the same or half of the frequency of the incoming data for stability reasons. The n over sampled signals (S) are fed in the TDVM circuit which is comprised of three sections. The first section detects the transition at the positions of two consecutive sampled signals according to a specific signal processing which requires to perform twice, three comparisons on six consecutive over sampled signals (the central one being excluded at each time). The second section validates the second detection as the transition position.

Abstract: There is disclosed a data recovery (DR) circuit including an over sampling (OS) circuit, a transition detection (TD) circuit and a sample selection/data alignment (SSDA) circuit. A multiphase clock generating circuit delivering n phases is coupled to each of these circuits. The OS circuit over samples the received digital data stream and produces n sampled signals at each clock period. The TD circuit is configured to detect a data transition (if any) and to generate n select signals, only one of which is active and represents a determined delay with respect to the transition position, indicating thereby which over sampled signal is the best to be retained. The SSDA circuit is configured to generate the recovered (retimed) data signal that is aligned with a predefined phase of said multiphase clock signal. The data recovery circuit is well adapted to high speed serial data communications between integrated circuits/systems on digital networks.

Abstract: A frequency detection system for producing clock pulses having a frequency equal to the frequency of a stream of binary data. The system includes a voltage controlled oscillator for producing the clock pulses. The frequency of such clock pulses changes in accordance with a control signal. Each one of the clock pulses has four sequential, one-quarter period phases. Adjacent phases are separated by boundaries to divide each clock pulse period into four quadrants. A frequency detector is fed by detected edges of the stream of binary data and the clock pulses for producing the control signal in accordance with the difference in frequency between the frequency of the clock pulses and the frequency of the stream of binary data. A lock-out circuit prevents subsequent production of the control signal until a subsequently detected data edge crosses a different one of the boundaries.

Abstract: A serial communication system transfers respective first and second signals via respective parallel signal carriers from a transmitter circuit to a receiver circuit. In synchronization with a clock signal (150), the transmitter circuit (110) serially represents a combination of the clock signal and data bit(s) (160) of a data message as the first and second signals (130, 140). At a data bit boundary, the transmitter circuit effects a transition of the first signal (130) if the data bit to be transmitted has a first value and effects a transition of the second signal (140) if the data bit has a different second value. The receiver circuit (120) recovers the clock signal by detecting and combining signal transitions of the first and second signal, for instance using an XOR function, and recovers the data message from the first and/or the second signal.

Abstract: A frame period is specified by means of a predetermined signal; a management data transmission region is set in this frame period; and when common information to be transmitted from the control station in the management data transmission region is received at a plurality of communication stations, any of these communication stations performs processing for repeatedly transmitting the received common information, whereby when communications in a network system are controlled by a control station, a station incapable of directly making communication with a control station can be controlled satisfactorily.

Abstract: A data transmitter according to the present invention includes driver, transmission line and receiver. The receiver includes a transition pulse generator for generating a transition pulse simultaneously with the transition of a data signal output from the driver. If an edge of an internal clock signal overlaps with the transition pulse being applied, then the receiver does not latch the data signal in synchronism with the edge of the internal clock signal. Instead, the receiver obtains and retains a data value opposite to the previous cycle one. On the other hand, while no transition pulses are being applied, the receiver latches the data signal normally responsive to the internal clock signal. Accordingly, the receiver can always accurately retain the very data transmitted through the transmission line, thus improving the reliability of the data received and realizing high-speed data transmission even if the internal clock signal has lagged with respect to the data signal.

Abstract: A decoding method and apparatus include providing capability for decoding data symbols that were encoded in a transmitter by either a serial-concatenated code or turbo code in a parallel processing fashion. The receiver upon knowing the encoding method may reconfigure the selection of data symbols from a table (600) to accommodate the appropriate decoding process. Initially a data symbol estimate for a number of data symbols of a plurality of data symbols Xi, Yi, and Wi are determined. The estimates of data symbols Xi, Yi, and Wi passing to a first and second decision nodes (610, 620) include estimates for the variables in one or more encoding equations. A new estimate for the data symbol Xi is determined based on the estimate determined at the initial step and the new estimate for each occurrence of the data symbol Xi at the first and second decision nodes (610, 620).

Abstract: The system for recovering symbol timing offset and carrier frequency error from an orthogonal frequency division multiplexed (OFDM) signal includes a receiver circuit for receiving an OFDM modulated signal representing a series of OFDM symbols, and providing a received signal to an output thereof. A peak development circuit is included for developing a signal having a plurality of signal peaks representing symbol boundary positions for each received OFDM symbol, where each of the signal peaks is developed responsive to an amplitude and phase correspondence produced between the leading and trailing portions of each of the received OFDM symbols. The system includes a circuit for enhancing the signal peak detectability, which includes a circuit for additively superimposing and then filtering the signal peaks, to produce an enhanced signal peak having an improved signal-to-noise ratio.

Abstract: Logic apparatus filters noise signals on a signal line to a digital circuit. An edge detector determines one or more edges of the noise signals relative to a fast clock. Signals indicative of the edges asynchronously reset a timer; the timer clocks the latch of the signal line when the signal line is stable, and without noise signals detected by the edge detector, for a period defined by a slow clock. The slow clock is slower than the fast clock by several orders of magnitude. The edge detector may be constructed by one flip-flop and an XOR gate. A second flip flop couples to the signal line and the output of the timer to pass through the latched value of the signal line to the digital circuit when clocked by the timer.

Abstract: A method for extracting binary data conveyed by an incident signal is provided in which the binary data is coded in the form of a pulsatile signal whose pulses have variable lengths which are multiples of a base pulse length 1T. The incident signal may include a succession of transitions whose spacings are representative of the lengths of the pulses. The method may include an initialization phase in which the value of a base distance corresponding to the base pulse length is determined from the contents of the incident signal, and an extraction phase in which a set of reference values corresponding respectively to various multiples of the determined base distance is formulated. For a calculated current distance, the values of the data corresponding to this current distance may be determined from a comparison between the reference values and a current corrected distance.

Abstract: A phase comparison circuit capable of realizing high-speed response by the PLL circuit in order to realize high-speed reproduction of the signals. An input signal is delayed by a delay buffer in order to produce a delayed signal. Changes in the level of the input signal are detected by a leading edge detection circuit and a falling edge detection circuit, a first and a second edge detection signals are output a control circuit changes the level of an output signal according to these detection signals, a phase comparison circuit compares the phases of the output from the control circuit and the clock signal, and a first and a second control signals are output according to the comparison result.

Abstract: The invention relates to a digital radio system and to a method for correcting a synchronization error in a digital radio system comprising at least one base station (100) communicating with terminals (102, 104) in its coverage area, and a mobile telephone exchange (108) communicating with the base station and controlling the operation of the base stations. The information to be transmitted is coded and decoded in a transcoder unit (200) into a form suitable for the transmission. The base station sends information frames to the transcoder at a certain pace, and, correspondingly, the transcoder sends information frames to the base station at a certain pace. To ensure easy transmission of information and to increase flexibility, the base station (100) indicates in an information frame sent to the transcoder (200) the synchronization error present in the information frames coming from the transcoder, and the transcoder corrects its synchronization after receiving said message.

Abstract: A digital circuit generates a phase synchronization signal for a digital input signal coded according to a biphase modulation. The phase synchronization signal is derived from a clock signal having a higher frequency than the maximum switching frequency of the digital input signal. The frequency of the clock signal is divided with a fully digital divider circuit having a non-integer ratio. The divider is self-synchronizing with the input digital signal. Control signals are used to enable or disable switching of the frequency divider. These control signals are generated by two circuits which sample the input signal with the master clock signal and analyze triplets of consecutive sampling values.

Abstract: The architecture and the method of operation of a receiver core are described. The core performs clock and data recovery on an incoming serial data stream transmitted across a wired media, such as a chip-to-chip or card-to-card interconnect. The bit error rate and accuracy of the recovery are optimized without centering of oversampling. Further, random errors due to edge mis-tracking are minimized. The receiver utilizes a phase rotator to detect the edge position of the bits of the data stream, select the optimum data sample and generate early and late signals if the detected edge is not in the expected position. A phase locked loop provides a frequency source for the phase rotator. At least three evenly spaced samples are detected for each bit. A sample processing algorithm, preferably an adaptive behavior algorithm, is used for centering the bit edge between two of the samples.

Abstract: The system preferably includes a unique transmitter that sends both clock and data signals over the same transmission line. The receiver uses the same transmission line to send data signals back to the transmitter. The transmitter comprises a clock generator, a decoder and a line interface. The clock generator produces a clock signal that includes a variable position falling edge. The falling edge position is decoded by the receiver to extract data from the clock signal. The receiver comprises a clock re-generator, a data decoder and a return channel encoder. The clock re-generator monitors the transmission line, receives signals, filters them and generates a clock signal at the receiver from the signal on the transmission line. The return channel encoder generates signals and asserts them on the transmission line. The signal is asserted or superimposed over the clock & data signal provided by the transmitter.