Abstract: An apparatus for data processing includes first and second functional units driven by corresponding first and second clock-signal sources, and a clock-retardation unit. The clock-retardation unit is configured to cause the second clock-signal to sustain a temporal offset that causes an offset between the first and second clock-signals to step toward a target time-domain offset between the first and second clock-signals.

Abstract: A method, an apparatus, and a computer program product for data communication over a multi-wire, multi-phase interface are provided. The method may include providing a sequence of symbols to be transmitted on a 3-wire interface, each symbol in the sequence of symbols defining one of three voltage states for each wire of the 3-wire interface, driving all wires of the 3-wire interface to a common voltage state during a transition from a first transmitted symbol to a second transmitted symbol, driving each wire of the 3-wire interface in accordance with the second transmitted symbol after a predetermined delay. Each wire may be in a different voltage state from the other wires of the 3-wire interface during transmission of the each symbol. The common voltage state may lie between two of the three voltage states.

Abstract: Methods of performing time-of-day synchronization in a packet processing network include accumulating timestamps transmitted in packets between master and slave devices, which are synchronized to respective master and slave clocks and separated from each other by the packet processing network. Operations are also performed to determine whether first timestamps accumulated in a first direction across the packet network demonstrate that a first packet delay variation (PDV) sequence observed from the first timestamps is stationary. A phase offset between the master and slave clocks is then adjusted using a time-of-day (ToD) estimation algorithm. This adjusting can include evaluating a location-dependent statistic of the first PDV sequence.

Abstract: A locking device comprising: a code generation means for generating a plurality of access codes in a first series and a second series, each access code being valid for a predetermined period of time, a code input means for receiving an input code, and a code comparison means, wherein the code comparison means is configured to unlock the lock in response to input of a code that corresponds to a currently valid access code, wherein the period of validity of each access code in first series partially overlaps the period of validity two adjacent access codes in the second series.

Abstract: A carrier frequency offset calibration method and a carrier frequency offset calibration system are provided. The carrier frequency offset calibration method is adapted to calibrate the carrier frequency offsets of a transmission signal which includes a primary carrier and a secondary carrier. In the carrier frequency offset calibration method, the transmission signal is analyzed according to known carrier frequencies, a primary feedback value and a secondary feedback value, so as to obtain a primary carrier offset value and a secondary carrier offset value. The relationship between the primary carrier offset value and the secondary offset value is considered to determine whether to adjust the primary feedback signal and the secondary feedback signal.

Abstract: A method for synchronising a receiving device with a transmitting device in a wireless communication network comprising forming a synchronisation sequence that has a frequency spectrum comprising peaks at multiple discrete fundamental frequencies, a signal power of the synchronisation sequence being concentrated at those frequencies, and transmitting said synchronisation sequence from the transmitting device to the receiving device.

Abstract: A device is disclosed including a memory configured to store a user data frame. The user data frame includes a first portion that includes traffic data. The user data frame also includes a second portion that includes a set of stuff bits arranged in a detectible pattern wherein a count of the set of stuff bits is associated with a measure of transport utilization of a data communication channel over which the user data frame is transported.

Abstract: The receiver includes a first buffer configured to buffer a data to generate a first internal data, a first delay unit configured to retard the first internal clock signal by a first delay period to generate a first delayed internal clock signal, and a second buffer configured to buffer the first internal data to generate a first input data.

Abstract: A communication system includes: a plurality of lanes; a plurality of transmission circuits respectively outputting data to the lanes in accordance with a transmission clock; and a plurality of reception circuits respectively receiving data from the lanes, each reception circuit includes: a clock data recovery circuit extracting own clock information from received data: a clock information switch circuit selecting either one of the own clock information of the reception circuit or another own clock information of an another reception circuit; a phase shifter generating a phase adjusted clock from a common reception clock source in accordance with clock information selected by the clock information switch circuit; and an input circuit taking in transmitted data in accordance with the adjusted clock, and the clock information switch circuit selects the own clock information in a normal operation and selects the another own clock information in an eye-opening measurement operation.

Abstract: A system including a midamble detection module and a processing module. The midamble detection module is configured to detect a midamble of a packet transmitted via a channel, where the packet includes (i) a preamble, (ii) the midamble, and (iii) a plurality of data fields, where the preamble includes (i) a first short training field, (ii) a first long training field, and (iii) a signal field, where the midamble includes (i) a second short training field and (ii) a second long training field, and where the midamble follows the preamble and is between two or more of the data fields. The processing module is configured to determine that the channel is busy in response to detecting the midamble in the packet.

Abstract: Methods are presented herein for estimating at least a frequency (offset) for a block of received symbols using two or more estimation stages. These methods may allow reducing the computational complexity of a frequency estimator while maintaining large frequency offset coverage and high frequency estimation accuracy. Also presented herein are satellite communication systems employing a burst transmission or continuous transmission, and configured to estimate at least a frequency (offset) for a received burst or a block of received symbols using two or more estimation stages. In some embodiments, a received burst or a received block of symbols may include a Unique Word located at or about the center of the received burst or the block of symbols.

Abstract: Systems and methods are provided for detecting a received synchronization signal. The method includes receiving, at a receiver, a signal from a transmitter, where one or more portions of the received signal include the received synchronization signal. The method includes processing the one or more portions of the received signal to obtain a differential signal, and processing the differential signal and a plurality of candidate differential synchronization signals to obtain a plurality of cross-correlation signals. Each candidate differential synchronization signal is associated with one cross-correlation signal.

Abstract: A method of determining at a receiver whether a received signal comprises a pure tone signal component. The method comprises: measuring a received signal over a measurement period; calculating, using maximum likelihood hypothesis testing, a likelihood ratio value for the measured signal and, determining, based on said likelihood ratio value, whether the measured signal comprises a pure tone signal component. The likelihood ratio value is a value indicative of the ratio of a likelihood LFSC that the measured signal comprises a pure tone signal component, and a likelihood LnoFSC that the measured signal does not comprise the pure tone signal component.

Abstract: A method performed by a device for performing synchronization between devices for a Device-to-Device (D2D) communication is provided. The method includes setting, according to a process of the device, the device to a group of devices for performing a dynamic switching; outputting a synchronization signal corresponding to the set group as a signal for setting synchronization in a physical layer; controlling, upon receiving another synchronization signal from another device, the outputting of the synchronization signal by applying a time offset according to a relation between the set group that includes the device and the group that includes the another device; and setting, if the synchronization signal and the another synchronization signal are converged, synchronization of the device based on a time point where the synchronization signal is output.

Abstract: A multi-port information communication system includes a reference clock signal generator configured to generate a reference clock signal. The system also includes a phase controller configured to generate a plurality of information communication clock signals based on the reference clock signal by staggering a phase of each of the information communication clock signals. The phase controller includes a delay-locked loop configured to generate a plurality of delay-locked loop signals based on the reference clock signal, and a plurality of time delay elements. Each time delay element is configured to produce a respective one of the information communication clock signals by adding a respective delay to a respective one of the delay-locked loop signals. The system includes information communication devices each including a respective transmitter. Each of the transmitters is configured to operate in response to a respective one of the information communication clock signals.

Abstract: A clock synchronization circuit is configured to capture an input data bit according to an input clock signal, and to synchronize and output the input data bit. The clock synchronization circuit includes a clock buffer for generating an internal clock signal according to the input clock signal and transmitting the internal clock signal to a clock line. The clock synchronization circuit further includes a D flip-flop for capturing and outputting the input data bit at an edge timing of the internal clock signal. The clock buffer includes an inverter core portion and an electric current suppressing portion. The inverter core portion is configured to generate the internal clock signal through alternately supplying an electric current to the clock line and drawing the electric current from the clock line according to the input clock signal. The electric current suppressing portion is configured to suppress an amount of the electric current.

Abstract: Methods and apparatus for improving system timing margin of high speed I/O (input/output) interconnect links by using fine training of a phase interpolator are described. In some embodiments, I/O links use forward clock architecture to send data from transmit driver to receiver logic. Moreover, at the receiver side, Phase Interpolator (PI) logic may be used to place the sampling clock at the center of the valid data window or eye. In an embodiment, a Digital Eye Width Monitor (DEWM) logic may be used to measure data eye width in real time. Other embodiments are also disclosed.

Abstract: Systems and methods are disclosed herein to provide improved clock synchronization between wireless data communication transmitters and receivers, including Orthogonal Frequency Division Multiplexing (OFDM) communication systems. In accordance with one or more embodiments, a clock synchronization system is disclosed that includes an adaptive threshold function operative in conjunction with a synchronizer that adjusts the frequency and phase of a receive clock oscillator. Such a synchronization system may offer improved capabilities such as resistance to radio frequency (RF) channel impairments and noise, rejection of mis-decoded clock synchronization signals, and handling of multiple transmitters.

Abstract: An object of the present invention is to provide a receiving apparatus and a receiving method capable of preventing phase rotation of a signal after FFT from occurring on a frequency domain. Further, the receiving apparatus according to the present invention is provided with: a window control unit configured to control a position of an FFT window in which FFT is performed to the time domain signal, and output FFT data corresponding to the FFT window; a signal delaying unit configured to generate, from the time domain signal, a plurality of delay signals with different delay amounts; and a signal switching unit having a switch for outputting by switching between two of the time domain signal and the plurality of delay signals based on a predetermined switch timing, the signal switching unit being configured to output the FFT data including the output signal of the switch.

Abstract: Embodiments of a system and method for synchronizing chains in a transceiver using central synchronization signals are generally described herein. In some embodiments, an RF signal having a reference frequency in a differential mode and a synchronization signal having a second frequency being the reference frequency divided by an integer in a common mode are produced at a oscillator generation circuit. The RF signal having a reference frequency in a differential mode and the synchronization signal having a second frequency being the reference frequency divided by an integer in a common mode are provided over each of a plurality of LO lines to a plurality of local LO generation circuit chains. Each synchronization signal having a second frequency being the reference frequency divided by an integer in a common mode is extracted at the plurality of local LO generation circuit chains.

Abstract: A method in a QAM receiver (100) for performing timing recovery. The QAM receiver (100) is configured to receive a sequence of symbols. Each symbol is represented by a respective IQ pair comprising a respective inphase component I and a respective quadrature component Q. The QAM receiver (100) samples the respective I component and the respective Q component with a relative timing offset between the sampling of the respective I component and the respective Q component. The QAM receiver (100) establishes a first value associated to a quality of the I component samples, and a second value associated to a quality of the Q component samples, and compares the first value and second value to determine if the sampling timing should be advanced or delayed to improve the sample quality. The QAM receiver (100) adjusts subsequent sampling by advancing or delaying a sampling timing based on the comparison.

Abstract: HDMI is a digital audio and video communications protocol commonly used in consumer electronics. HDMI is particularly synonymous with high fidelity audio and video. Even though HDMI is a digital communications protocol, the audio quality can be impaired by analog signal impairments and distortions even if there are no digital decoding errors. In particular, the very process by which the audio is converted from Digital (HDMI) to human audible “Analog Audio” can be prone to errors. This occurs when the Digital to Analog Converter (DAC) clock, which is derived from the HDMI TMDS clock or HDMI source, is “distorted” due to its jitter, resulting in erroneous sampling or outputting of vital audio samples, thereby reducing the audio quality of the experience. The present invention reduces the jitter on the TMDS clock, and hence the audio DAC clock, resulting in lower audio distortion.

Abstract: A phase-locked loop having: an oscillator for forming an oscillating output signal; a frequency divider connected to receive the output of the oscillator and frequency divide it by a value dependent on a division control signal; and a phase comparator for comparing the phase of the divided signal and a reference signal to generate a control signal, the operation of the oscillator being dependent on the control signal; a first mode of operation in which the frequency divider is configured to operate in dependence on a first division control signal such that the resultant oscillating output signal has a first frequency and first phase, a second mode of operation in which the frequency divider is configured to operate in dependence on a second division control signal such that the resultant oscillating output signal has a second frequency and second phase, the first division control signal being generated independently of the oscillating output signal such that the first phase is maintained when the phase-locked

Abstract: A technique for decoding a signal in a communication network is provided. A method implementation of the technique comprises the steps of receiving a signal; identifying a position in the signal; initializing a Viterbi state metric; and decoding the encoded signal by means of a wrap-around Viterbi algorithm. The received signal comprises information, wherein the signal is encoded by a tail-biting convolutional code. The identified position relates to a known portion of the information. The initialized Viterbi state metric is consistent with the known portion of the information. The decoding uses the initial Viterbi state metric, wherein the decoding starts at a decoding step following the identified position.

Abstract: An analog-to-digital converter (ADC) and a receiver that includes the ADC is disclosed. The ADC includes a first filter configured to receive a signal in an I-signal path of the receiver and a second filter configured to receive a signal in a Q-signal path of the receiver. The ADC further includes a quantizer alternatingly in connection with the first and second filters, and at least one DAC alternatingly in connection with the first and second filters. Switches in the ADC are configured to alternate connection between an input of the quantizer and outputs of the first and second filters, and are also configured to alternate connection between an output of the at least one DAC and inputs of the first and second filters.

Abstract: Circuits and techniques for operating an integrated circuit are disclosed. A disclosed method includes receiving a data packet with a first operating frequency rate with first and second receiver circuits. The data packet may include a plurality of preamble bits. The first and second receiver circuits may operate at second and third operating frequency rates, respectively. A portion of the data packet received at the first receiver circuit is transmitted to a control circuit. The plurality of preamble bits within the portion of the data packet is identified with the control circuit. A clock circuit is then calibrated based on the plurality of preamble bits. The first and second receiver circuits may be clocked with first and second clock outputs from the clock circuit.

Abstract: Systems, methods, and other embodiments associated with preamble detection based on repeated preamble codes are described. According to one embodiment, an apparatus is provided that wirelessly receives a signal and calculates a differential output corresponding to a multiplication of the signal and a delayed version of the signal. A cross correlation is performed between the differential output and a known preamble pattern to produce a cross correlation output. One or more peaks are detected in the cross correlation. The detected peaks are used in subsequent processing to detect the known preamble pattern in the wirelessly received signal.

Abstract: A clock data recovery circuit including a recovery unit and a loop control unit is provided. The recovery unit generates a recovery clock signal according to an original data signal. The recovery unit locks a frequency of the recovery clock signal to a correction frequency through a first loop, and locks the frequency of the recovery clock signal to a sampling frequency through a second loop. The correction frequency is smaller than the sampling frequency. The recovery unit adjusts the frequency of the recovery clock signal according to a reference clock signal and a first dividing signal in the first loop. The loop control unit switches the recovery unit to the first loop or the second loop according to a frequency difference between the reference clock signal and a second dividing signal.

Abstract: Disclosed is a spectrum spread communication system which is hardly influenced by noises, and in which a frame structure can be identified at a receiving side without use of a frame synchronization signal. A spread code generator switches spread codes (“Scai” and “Scbi”) in each frame, and outputs it to a spread modulation unit. The spread modulation unit performs spread modulation of transmission data, and transmits it to a direct current power line. A reference code generator generates reference codes (“Scai” and “Scbi”) in the same code phase. Spread demodulation units performs spread demodulation of the received signal with use of the reference codes (“Scai” and “Scbi”), and output it to a selection unit. A frame synchronization detection unit identifies a frame structure on the basis of switching of a synchronization state of a code phase in a code phase synchronization detection unit.

Abstract: A wireless communication device includes a BBIC for performing baseband signal processing, an RFIC for performing radio-frequency signal processing, and a quartz resonator. The RFIC has a storage unit which stores an adjustment value for adjustment of a clock frequency that is based on an oscillation frequency of the quartz resonator, and outputs the adjustment value when its resetting active state is canceled; a frequency adjusting unit for adjusting the clock frequency according to the adjustment value; and an RF signal processing unit which operates based on the clock signal and performs the radio-frequency signal processing.

Abstract: Various embodiments of the present invention relate to systems, devices and methods of oversampling electronic components where high frequency oversampling clock signals are generated internally. The generated oversampling clock is automatically synchronous with the input clock and the input serial data in a serial data link, and is adaptive to predetermined parameters, such as bit depth and oversampling rate.

Abstract: A reception circuit has: a phase detector that detects a phase code based on a phase of data in relation to a first clock signal; a calibration signal generator that, in a calibration mode, adjusts a frequency of the first clock signal or the data so that the phase code detected by the phase detector changes; a calibrator that, in the calibration mode, stores a difference between the phase code and an ideal value of the detected phase, and that, in a normal operation mode, outputs the ideal value in correspondence with the phase code detected by the phase detector; and a phase adjustor that, in the normal operation mode, adjusts a phase of the first clock signal based on the phase code detected by the phase detector and the ideal value, and that outputs to the phase detector.

Abstract: A system for synchronizing nodes in a wireless network comprises a first node and a second node. The first node comprising a transmitter, a receiver, and a first time keeper. The second node comprising a transmitter, a receiver, a second time keeper, a timing error measurer for making a timing error measurement between the first time keeper and the second time keeper. The second timekeeper is adjusted to target minimizing the timing error measurement.

Abstract: A CDR circuit includes an AD converter that converts an analog input signal to a digital output signal according to an operation clock signal; a phase adjuster that subtracts a first phase from a first clock signal having a first frequency equal to a frequency of the input signal to output a second clock signal having a second frequency as the operation clock signal to the AD converter; a phase detector that detects a second phase in the output signal of the AD converter; a filter that obtains a third phase by performing a filtering process based on the first phase, the second phase, and the third phase output from the filter; an adder that adds the first phase and the third phase to obtain a fourth phase; and a decision circuit that obtains recovered data from the output signal of the AD converter using the fourth phase.

Abstract: A transmitter includes an amplitude adjustment unit multiplying an amplitude adjustment sequence value for adjusting amplitude with a synchronization channel transmitted from a base station for establishing synchronization with a mobile station.

Abstract: A reception circuit includes: a plurality of block circuits that each include a phase control circuit that controls a phase of a first clock, and a plurality of internal circuits that are driven by a second clock generated based on the phase-controlled first clock, wherein the phase control circuit in each of the block circuits is controlled by means of a control signal from an operation phase control circuit in such a way that an error rate for reception data due to the plurality of block circuits decreases.

Abstract: A mechanism for dynamic skew correction in a multi-lane communication link includes a receiver unit including, for each of the lanes, a first-in first-out (FIFO). The FIFO may store received symbols to locations pointed to by a write pointer and output to downstream logic, symbols stored at locations pointed to by a read pointer. The receiver may also include a symbol drop unit that disables the write pointer in response to receiving a start alignment symbol, and enables the write pointer in response to receiving an end alignment symbol. The receiver also includes an alignment unit that disables the read pointer in response to detecting that the end symbol has been received at least one lane but not all lanes. In addition, the alignment unit may enable the read pointer in response to a determination that the end symbol has been received on all lanes.

Abstract: A secure optical communication system and method are disclosed. Short optical pulses are first modulated with data, then dispersed in time so that they spread out over multiple bit periods, then the desired code is applied to the dispersed pulses. The encoding may include frequency shifts or phase shifts or other. The dispersed optical symbols overlap in time so an applied code chip thus acts on multiple symbols simultaneously. There are generally multiple code chips per dispersed symbol. The coding device does not need to be synchronized to the data rate. Multiple wavelength division multiplexed channels may be encoded simultaneously. The signal propagates to a decoder that is synchronized with encoder to apply a complementary code thereby canceling out the effect of the encoder. The encoder and decoder can be realized by varying the wavelength of an optical pump to a parametric amplifier, allowing for a wide-band frequency shift.

Abstract: Semiconductor devices are provided. The semiconductor device includes an internal clock generator and an internal strobe signal generator. The internal clock generator generates an internal clock signal having a frequency which is higher than that of an input clock signal according to a phase difference between the input clock signal generated from an external device and a first input control signal. The internal strobe signal generator generates an internal strobe signal having a frequency which is higher than that of an input strobe signal according to a phase difference between the input strobe signal generated from the external device and a second input control signal.

Abstract: Symbol timing acquisition is described for a wireless broadband signal received at a user terminal from a gateway via a satellite. In-phase and quadrature channels of the wireless signal may each be sampled at a rate of one sample per symbol. The samples may be interpolated to generate an early interpolation and a late interpolation for each of the samples. A difference measurement is obtained between the early interpolation and the late interpolation for a set of the samples. A number of the difference measurements may be averaged, and symbol timing may be modified based on the average. This process may be continued on an iterative basis to acquire symbol timing.

Abstract: An exemplary embodiment of the present invention provides a latency stabilization system for stabilizing the display latency between a source and a renderer over an IP network. The latency stabilization system comprises a frequency syntonization module, a frequency lock detection module, and a phase correction module. The frequency syntonization module can be configured to syntonize a frequency of a source signal from the source and a frequency of a display signal to be displayed on the renderer. The frequency lock detection module can be configured to detect whether the frequency of the source signal and the frequency of the display signal are locked. The phase correction module can be configured to, synchronize a phase of the source signal and a phase of the display signal, and generate correction data based in part on synchronization of the phase of the source signal and the phase of the display signal.

Abstract: The present invention relates to a clock-embedded or source synchronous semiconductor transmitting and receiving apparatus and to a semiconductor system including same. The semiconductor apparatus according to one embodiment of the present invention includes: a data providing unit for providing differential data; a multi-phase clock generator for generating a first clock signal provided to the data providing unit, and a second clock signal having a different phase from the first clock signal; and a combining unit for receiving the differential data and the second clock signal and combining same to generate a combined signal, wherein the second clock signal is a single clock signal and has n (here, n is an integer of two or greater) times a symbol period of the differential data, the first and second clock signals have a 90 degree phase difference, and the combination signal is transmitted to the outside through differential transmission lines.

Abstract: In calibration mode, a clock signal and a data signal are respectively transmitted via a clock lane and a data lane of an MIPI. A test clock signal is provided by adjusting the phase of the clock signal, and a test data signal is provided by adjusting the phase of the data signal. By latching the test data signal according to the test clock signal, a latched data may be acquired for determining an optimized phase relationship corresponding to the clock lane and the data lane. When transmitting the clock signal and the data signal in normal mode, the signal delays of the clock lane and the data lane may be adjusted according to the optimized phase relationship.

Abstract: A synchronous data transmission system for transmission of data between two communication partners, of which one serves as a transmitter and one as a receiver, comprising a clock signal producer which produces a transmission clock signal with a transmission clock signal rate from the transmitter to the receiver, which during the occurrence of one of the events equals an event specific transmission clock signal rate associated with the arising event and during an event free period of time equals a fundamental clock rate different of all event specific transmission clock signal rates.

Abstract: A phase interpolator is provided. The phase interpolator includes a plurality of capacitors, a first input for a clock signal, a second input for a phase shifted clock signal, a reference input for a reference signal, and an output. The phase interpolator is configured to provide at its output an interpolated, modulated phase information signal by switching, dependent on a modulation information, a first number of the capacitors between the first input and the output, a second number of the capacitors between the second input and the output, and a third number of the capacitors to the reference input.

Abstract: Systems and methods for high-clock synchronization and stability are disclosed.

Abstract: A method is provided for improving synchronization and information transmission in a communication system, including: generating a signal with a centrally symmetric part s(k) exploitable for synchronization; and sending the signal over a communication channel. The signal is based on a uniquely identifiable sequence c(l) from a set of sequences exploitable for information transmission. The centrally symmetric part s(k) is centrally symmetric in the shape of absolute value thereof. The centrally symmetric part s(k) is of arbitrary length N.

Abstract: An apparatus for synchronizing an incoming signal with a clock signal comprises two or more synchronizer circuits, wherein each synchronizer circuit receives the incoming signal and the clock signal. Each synchronizer circuit generates a synchronized signal, wherein the state of each synchronized signal changes on a different phase of said clock signal in response to a change of the state of said incoming signal. A decision mechanism circuit receives the synchronized signals generated by each synchronizer circuit, wherein the decision mechanism circuit determines the output signal in response to the change of the state of the incoming signal. The decision mechanism circuit further comprises a memory element having a state which is set according to a previously detected state of said signal, wherein the output signal is determined according to the state of the memory element.

Abstract: A method is provided for synchronization in a communication system. A receiver receives and processes a signal with a centrally symmetric part s(k) exploitable for synchronization. The signal is based on a uniquely identifiable sequence c(l) from a set of sequences exploitable for information transmission. The centrally symmetric part s(k) is centrally symmetric in the shape of absolute value thereof. The centrally symmetric part s(k) is of arbitrary length N, and the sequence c(l) is a Zadoff-Chu sequence.

Abstract: A transmission system which couples a plurality of transmission devices to a control device includes a first transmission device which is one of the plurality of transmission devices; a first calculation circuit which calculates a first difference value indicating a frequency difference value between a common clock supplied from the control device and a first clock as a clock used in the first transmission device; and a transmitter which reports the first difference value to a second transmission device other than the first transmission device, wherein the second transmission device comprises: a second calculation circuit which calculates a second difference value indicating a frequency difference value between the common clock and a second clock used in the second transmission device, and a frequency controller which controls an oscillator generating the second clock so that the second difference value approaches the first difference value reported from the first transmission device.