Abstract: Aspects of a method and system for adaptation between different closed loop, open loop and hybrid techniques for multiple antenna systems may include a transmitting station that enables generation of a plurality of signals that are concurrently transmitted via a communication medium based on a selected one of: full feedback information, reduced quantity feedback information, or no feedback information. The selection may be determined at the transmitting station based on a determined Doppler shift frequency.

Abstract: In calibration mode, a clock signal and a data signal are respectively transmitted via a clock lane and a data lane of an MIPI. A test clock signal is provided by adjusting the phase of the clock signal, and a test data signal is provided by adjusting the phase of the data signal. By latching the test data signal according to the test clock signal, a latched data may be acquired for determining an optimized phase relationship corresponding to the clock lane and the data lane. When transmitting the clock signal and the data signal in normal mode, the signal delays of the clock lane and the data lane may be adjusted according to the optimized phase relationship.

Abstract: In one embodiment, the present invention includes a de-serializer to receive serial data at a first rate and to output a parallel data frame corresponding to the serial data aligned to a frame alignment boundary in response to a phase control signal received from a feedback loop coupled between the de-serializer and a receiver logic coupled to an output of the de-serializer. Other embodiments are described and claimed.

Abstract: A signal calibration method for synchronizing a clock signal and at least one data signal in a transmission system is disclosed. The signal calibration method comprises detecting at least one transmission time difference between the clock signal and the at least one data signal transmitted in the transmission system, calculating a plurality of delay periods of the clock signal and the at least one data signal according to the at least one transmission time difference, and respectively delaying the clock signal and the at least one data signal for the plurality of delay periods to synchronize the clock signal and the at least one data signal.

Abstract: While a phase of an output clock signal is varied, an input frame pulse is latched based on the output clock signal. Then, by using an output frame pulse, which is a result of the latching, generation of a racing state, which is caused by the phase relation between the output clock signal and the output frame pulse, is detected. Next, a phase adjustment amount is determined so that the phase of the output clock signal of the moment when the racing state is generated is shifted by a period corresponding to half a cycle of the output clock signal.

Abstract: A system and method for performing clock and data recovery. The system sets the phase of a recovered clock signal 30 according to at least three estimates of the rate of change of an offset between the frequency of the data transmitter clock and the frequency of a receiver clock 15.

Abstract: Methods and apparatus are provided for implementing a digital host-lock mode in a transceiver. The transmitter portion of a transceiver is synchronized to a recovered clock generated by the receiver portion of the transceiver by applying a receiver input signal to a clock and data recovery system in the receiver portion to generate the recovered clock and a frequency offset value. The frequency offset value comprises a digital word indicating a frequency offset between the recovered clock and the receiver input signal. A transmit clock is generated in the transmitter portion that is substantially synchronized to the recovered clock by applying the digital word to a clock signal generator.

Abstract: Methods and apparatus are provided for trimming one or more clock buffers in a clock and data recovery system in a receiver using a phase shift of the transmit data. At least one clock buffer is trimmed by synchronizing the clock and data recovery system to a transmit clock received from a transmitter. A transmit data signal that is received from the transmitter is then sampled using at least a first latch in the receiver. A phase of the transmit data signal is adjusted in the transmitter until values sampled by the first latch satisfy a first predefined criteria (such as approximately 50% binary ones and 50% binary zeroes). The phase of the transmit data signal is adjusted again to an approximate phase location of a second latch in the receiver, and the transmit data signal is sampled using the second latch. A phase of a clock buffer associated with the second latch is then adjusted until values sampled by the second latch satisfy a second predefined criteria.

Abstract: The invention relates to transmission and reception of clock synchronization data in a wireless communication system. According to the invention a device for transmitting clock synchronization data obtains at least one time reference of a wireless communication system clock, controls transmission of a frequency reference of the wireless communication system clock via an air interface of the wireless communication system, and provides transmission of the time reference via a transport network associated with the wireless communication system, while the base station receives the frequency reference, locks an own oscillator to the frequency of the frequency reference, receives the time reference from the transport network and adjusts timing that is controlled by the oscillator based on the time reference.

Abstract: A basestation for a cellular communication system has an interface, for connection to a computer network, and also includes an oscillator, for generating wireless transmit and receive frequencies. A controller receives timestamped response messages from a time server over the computer network, each response message being subject to a network propagation delay, which is a sum of a minimum network propagation delay and a jitter component. For each received response message an apparent network propagation delay is determined as a function of a difference between a first timestamp applied by the time server and a second timestamp based on a clock derived from said oscillator. A subset of the received response messages are selected, whose network propagation delays include minimal jitter components. The frequency accuracy of the oscillator is then determined based on changes over time in the apparent network propagation delays of the selected received response messages.

Abstract: A clock generator circuit for generating synchronization signals for a multiple chip system. The clock generator circuit comprises generation of a synchronization signal from a reference clock and chip global clock with edge detection logic. In high performance server system design with multiple chips, a common practice for server systems is to use feedback clock and delayed reference clock to generate the synchronization signal. The generated synchronization signal is transferred to latches clocked by the global clock to be used for chip synchronization functions. As the system clock frequency is pushed higher, the phase difference between generated synchronization signal clocked by feedback clock and receiving latch clocked by global clock is becoming such a large portion of cycle time that this signal cannot be transferred deterministically.

Abstract: The present invention relates to a linear time code (LTC) generator that is adapted to generate LTC data. The LTC generator comprises a rising edge detector that is adapted to detect a frame sync input corresponding to a beginning of a frame time of video data and to generate a first synchronization signal corresponding to the frame sync input and a frame length measurement block that is adapted to count a number of clock cycles in the frame time. The LTC generator further comprises a bit rate calculator that is adapted to determine a bit rate of the frame time based on the number of clock cycles in the frame time and a bit rate counter block that is adapted to generate a second synchronization signal corresponding to the bit rate.

Abstract: It is disclosed a network element for a communication network configured to synchronize its local clock to a reference clock signal. The network element comprises: a main board comprising an internal module configured to support an internal synchronization transport protocol, and a connector connected to the internal module; and a pluggable module configured to be removably connected to the connector. The pluggable module is configured to, when connected to the connector: exchange external synchronization information with a further network element, the external synchronization information being formatted according to an external synchronization transport protocol different from the internal synchronization transport protocol; exchange with the internal module internal synchronization information formatted according to the internal synchronization transport protocol; and interface the internal synchronization transport protocol and the external synchronization transport protocol.

Abstract: A method of frequency search for a digitally controlled oscillator (DCO) with multiple sub-bands. The method comprises providing multiple workable pre-control codes, each control code comprising a most significant bit (MSB), corresponding to each frequency of the DCO for selection, selecting one of the workable pre-control codes according to the MSBs thereof, and providing the selected control code to the DCO.

Abstract: In operation, a transmitting device selects a synchronization pattern associated with the desired timeslot that is at least mutually exclusive from synchronization patterns associated with other timeslots on the same frequency in the system. Once selected, the transmitting device transmits a burst embedding the synchronization pattern that was selected, where appropriate. If the receiving device detects the synchronization pattern, it immediately synchronizes with the timeslot with confidence that it is synchronizing to the desired timeslot by using sets of synchronization patterns associated with the desired timeslot that are at least mutually exclusive from synchronization patterns associated with the other timeslots on the same frequency.

Abstract: An apparatus for frequency synchronization is proposed to detect a synchronization signal from the baseband signals. It is featured that three types of detection values are introduced to detect whether the synchronization signal is received or not. More particularly, the claimed frequency synchronization apparatus provides at least one signal power generator for receiving a predetermined number of symbols of the baseband signals, and further calculating an average quality value therefore. Further, the apparatus includes a signal selector for producing a first detection value according to the average quality value. Still further, the apparatus provides a decision unit to produce a second detection value. After that, a signal processor inside the decision unit is used to calculate a third detection value as combining the first detection value and the second detection.

Abstract: An approach is provided for supporting carrier synchronization in a digital broadcast and interactive system. A carrier synchronization module receives one or more signals representing a frame that includes one or more overhead fields (e.g., preamble and optional pilot blocks and one or multiple segments separated by pilot blocks). The module estimates carrier frequency and phase on a segment by segment basis and tracks frequency between segments. Carrier phase of the signal is estimated based upon the overhead field. Estimates carrier phase of random data field are determined based upon the estimated phase values from the overhead fields, and upon both the past and future data signals. Further, the frequency of the signal is estimated based upon the overhead fields and/or the random data field. The above arrangement is particularly suited to a digital satellite broadcast and interactive system.

Abstract: An apparatus for transferring data in a non-spread domain to a spread domain. The apparatus comprises a first-in-first-out (FIFO) memory; a write pointer generator adapted to generate a write pointer for writing data into the FIFO memory in response to a non-spread clock signal; a spread-clock generator adapted to generate a spread clock signal based on the non-spread clock signal; a read pointer generator adapted to generate a read pointer for reading data from the FIFO memory in response to the spread clock signal; and a controller adapted to control the spread-clock generator in response to the read and write pointers indicating predetermined potential data overflow or underflow of the FIFO memory.

Abstract: According to an aspect of an embodiment, a communication system includes a transmission apparatus with a coding section that generates multi-level-coded signals and transmits the multi-level-coded signals; and a deskew signal generation section that generates and transmits a deskew signal related to the multi-level-coded signals. The communication system also includes a receiving apparatus with a decoding section that decodes the multi-level-coded signals to generate decoded signals, and a deskew processing section that performs deskew processing for compensating skew among the decoded signals of the multiple channels. The deskew signal generation section generates the deskew signal that has been framed by extracting a part of the data from each of the channels of the input signals, adding framing data for enabling a receiving apparatus to recognize which channel the extracted data has been extracted from, and performing rate conversion.

Abstract: Certain embodiments of the present disclosure relate to a method for tracking of a carrier frequency offset. A soft combined frequency tracking discriminator is proposed as a part of the closed loop structure that can provide fast tracking of the frequency offset in an initial pull-in mode, and can also track small residual frequency variance in a fine-tracking mode.

Abstract: In one embodiment, a method to generate a set of tone frequencies within an operating frequency range for use in a timing acquisition process in a wireless communication system comprises selecting a system frequency resolution generating a set of frequency tones which are relatively prime integers with respect to the frequency resolution and within an operating frequency range of the wireless communication system. Other embodiments may be described.

Abstract: A method of sampling phase calibration and a device thereof is suitable for an analog-to-digital converter and phase lock loop (ADC-PLL). The ADC-PLL conducts sampling on a periodic analog signal according to a sampling phase so as to produce a plurality of digital signals. The sampling phase calibration device includes a storage unit, a motion-detecting unit and a control unit. The motion-detecting unit is to calculate the number of motion data corresponding to a sampling phase. The control unit is coupled to the motion-detecting unit for changing the sampling phase so as to obtain the number of motion data corresponding to each sampling phase and selecting the sampling phase corresponding to the minimum number of motion data as an optimal sampling phase. The ADC-PLL can correctly sample an analog signal by using the optimal sampling phase and reduce the influence of clock jitter to the minimum.

Abstract: A method for detecting a specific timing from a synchronization channel is described. A signal with a known sequence is received. Two or more correlation values between the received signal and the known sequence are calculated at two or more positions. The two or more correlation values are compared. A determination is made whether the position of the known sequence has been shifted based on the comparison. A specific timing of a synchronization channel is detected based on the determination.

Abstract: Certain aspects of a method and system for satellite communication are disclosed. Aspects of one method may include a receiver that handles digital video broadcasting. The receiver may be enabled to dynamically vary spacing between one or more pilots within at least one frame based on a determined symbol rate. The size of each of a plurality of received programs may be determined and the spacing between one or more pilots may be dynamically varied based on the determined size of each of the plurality of received programs.

Abstract: A receiver may include a clock and data recovery circuit, a detection circuit and a sampling clock generator. The clock and data recovery circuit may receive first data and sample the first data to generate recovered data in response to a reception sampling clock signal. The detection circuit may detect a frequency difference between a transmission sampling clock signal and the reception sampling clock signal by comparing the first data and the reception sampling clock signal to generate a frequency difference detection signal. The sampling clock generator may generate the reception sampling clock signal based on the frequency difference detection signal and a first reference clock signal. Therefore, a communication system including the receiver may effectively reduce a jitter noise.

Abstract: The invention relates to a method or to a correspondingly equipped circuit for line-coupled generation of a clock (t), wherein the clock (t) is controlled in relation to a synchronization signal (hs) and by means of a closed loop (FLL) with respect to the phase and/or the frequency in relation to the synchronization signal (hs); wherein a plurality (n) of at least two count values (cn, c0-c7) is determined, wherein each of the count values (cn, c0-c7) is determined with at least one count duration number (z) of consecutive periods of the synchronization signal (hs), and wherein each of the count values (cn, c0-c7) is determined offset relative to at least one further count value (cn, c0-c7) with a count offset (v) which is different from the count duration number of consecutive periods of the synchronization signal (hs).

Abstract: A signal processing unit and a wireless communication device are provided for making it possible to detect a frequency by means of a small scale operation circuit in a short time.

Abstract: A wireless communications device may include a portable housing and a temperature-compensated clock circuit carried by the portable housing. The device may further include a wireless receiver carried by the portable housing for receiving timing signals, when available, from a wireless network, and a satellite positioning clock circuit carried by the portable housing. A clock correction circuit may be carried by the portable housing for correcting the temperature-compensated clock circuit based upon timing signals from the wireless network when available, and storing historical correction values for corresponding temperatures. The clock correction circuit may also correct the temperature-compensated clock circuit based upon the stored historical correction values when timing signals are unavailable from the wireless network, and correct the satellite positioning clock based upon the temperature-compensated clock circuit.

Abstract: There is provided a signal processing device and a wireless apparatus capable of not erroneously determining polarity, appropriately performing a spread modulation process, a carrier modulation process, and reception data demodulation process, improving reception accuracy, and miniaturizing a circuit, even when IF carrier frequency shift occurs.

Abstract: In an embodiment, a wireless communication system (100, FIG. 1) includes one or more nodes (102-108) and one or more user equipments (UE) (110). A node may apply (502, FIG. 5) a cell-specific spreading code to a cell identifier, which indicates an identity of a cell (113, FIG. 1) serviced by the node. The node may insert (504, FIG. 5), into a frame (200, FIG. 2), at least one synchronization channel symbol, which corresponds to the spread cell identifier, and the node may transmit (506, FIG. 5) the frame over an air interface. A UE may receive (702, FIG. 7) a frame from the air interface. The UE may despread (708) the spread cell identifier, and acquire (712) a cell identifier corresponding to a particular cell.

Abstract: Systems and methods are provided to generate a set of synchronization channel sequences that optimize time and frequency acquisition. A set of root indices of Zadoff-Chu sequences in a first domain (e.g., time domain) that optimize a performance metric or merit factor are identified. An optimal index is determined that also optimizes a performance metric in a reciprocal domain (e.g., frequency domain). Optimal indices satisfy a centro-symmetric relationship with respect to a half-value of sequence length: When 1 is an optimal index, N?1 is also an optimal root index. For sequences of length Q2=N, a base sequence generated with an optimal sequence can be utilized to generate at least two disparate optimal sequences through sign-flip, conjugation, and periodic modulation operations.

Abstract: A communication circuit includes a sampling clock generating circuit generating a sampling clock signal having a frequency that is “m” times greater than a bit rate of the communication data and containing “n” pulses in each bit period of the communication data; and a sampling circuit sampling the communication data based on the sampling clock signal to obtain “n” sets of received data in each bit period of the communication data. The sampling clock generating circuit delays the sampling clock signal when a first one or more of the “n” sets of received data are different from a value of the rest of the “n” sets of received data, and advances the sampling clock signal when a value of a last one or more of the “n” sets of received data is different from a value of the rest of the “n” sets of received data.

Abstract: A method for synchronizing a waveform received in a subterranean borehole with a transmitted waveform includes at least one of a phase synchronization, a symbol synchronization, or a frame synchronization method. The phase and symbol synchronization methods make use of distinct loop filters which process corresponding feedback signals so as to output phase clock and symbol clock adjustments. Frame synchronization methods accumulate a preamble correlation on a symbol stream having at least one repeating preamble.

Abstract: An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing reference signal. The data-sampling signal may be provided by adjustably delaying a clock signal according to the phase information acquired from the strobe signal. The data-sampling signal may also have an improved waveform compared to the timing reference signal, including a fifty percent duty cycle and sharp transitions. The phase information acquired from the timing reference signal may also be used for other purposes, such as aligning received data with a local clock domain, or transmitting data so that it arrives at a remote device in synchronism with a reference clock signal at the remote device.

Abstract: A control circuit receives a first clock signal at a first frequency, a frequency division signal specifying a divisor number, and a second clock signal at a second frequency (higher than the first frequency). The control circuit includes a phase control block that defines non-overlapping portions of a pulse of the second clock to include center, left and right portions. A determination is then made as to whether an edge of the first clock is located within the center portion. In response to such a determination, a number of periods of the second clock signal which occur within one or more periods of the first clock signal is compared to a number derived from the divisor number to generate a frequency selection signal indicative of that comparison. A controlled oscillator circuit generates the second clock signal at the second frequency, wherein the second frequency is specified by the frequency selection signal.

Abstract: A broadcast transmitting system and a method of processing broadcast data in the broadcast transmitting system are disclosed. Herein, the broadcast transmitting system includes a group formatting unit for mapping mobile service data into at least one region of a plurality of regions within a data group and adding a plurality of known data sequences to the data group, a deinterleaver for deinterleaving data in the data group, a first multiplexer for multiplexing mobile service data packets including the deinterleaved data with main service data packets including main service data, an interleaver for interleaving data in the multiplexed data packets, a trellis encoding unit for trellis encoding the interleaved data, a second multiplexer for multiplexing the trellis-encoded data with segment synchronization data and field synchronization data, and a modulator for modulating a broadcast signal including the multiplexed data.

Abstract: The phase detector compares the phase of a synchronous clock signal from the clock interpolator with the phase of serial data and outputs a phase error signal corresponding to a comparison result. The first integrator performs integration of the phase error signal and obtains a phase correction control signal for tracking phase shift of the serial data. The second integrator further performs integration of the phase correction control signal and obtains an up/down signal. The pattern generator generates a frequency correction control signal for tracking frequency shift of the serial data from the up/down signal. The product of the pattern length of the pattern generator and the count width of the second integrator is equal to or larger than a threshold that becomes larger as the count width of the first integrator is larger.

Abstract: A method and apparatus are provided for identifying a cell and a sub-frame by detecting a part of a secondary synchronization signal including a sequence of N OFDM symbols. For each OFDM symbol, the method obtains a set of metrics, each metric being associated with a predetermined combination of a cell identifier and a sub-frame alignment (CID/SF). For each metric, the method counts the number of times a metric exceeds a first predetermined threshold, delivering a summed value, and applies an M of N criterion to the summed value, delivering a ratio value. The ratios values are analyzed in order to identify the cell and the sub-frame, corresponding to a cell identifier and a sub-frame alignment, associated to a particular ratio value among the ratios values, which exceeds a second predetermined threshold.

Abstract: Systems and methods for operating of one or more devices before, during, and/or after a power-save mode are provided. The system may include a transmitter device that configures the differential signal lines to low-impedance and a predetermined low-voltage during the power-save mode (such as connecting the differential signal lines to ground). The system may also include a receiver device that senses a wake-up signal, determines the type of wake-up signal, and wakes-up according to the type of wake-up signal.

Abstract: A method of operating a phase locked loop (FIG. 5) for a wireless receiver is disclosed. The method includes receiving a reference signal (503) having a first and a second plurality of cycles and receiving a feedback signal (512) having the first and the second plurality of cycles. The feedback signal is compared (504) to the reference signal. A plurality of phase errors is produced for each cycle of (UP, FIG. 10A) the first plurality of cycles in response to the step of comparing.

Abstract: Symbol timing acquisition is described for a wireless broadband signal received at a user terminal from a gateway via a satellite. In-phase and quadrature channels of the wireless signal may each be sampled at a rate of one sample per symbol. The samples may be interpolated to generate an early interpolation and a late interpolation for each of the samples. A difference measurement is obtained between the early interpolation and the late interpolation for a set of the samples. A number of the difference measurements may be averaged, and symbol timing may be modified based on the average. This process may be continued on an iterative basis to acquire symbol timing.

Abstract: A technique for operating a wireless communication device includes assigning a reference signal bandwidth to a reference signal. Cyclic shift control bits (associated with the reference signal) are then allocated based on the assigned reference signal bandwidth. The allocated cyclic shift control bits specify a cyclic shift associated with the reference signal.

Abstract: Methods and apparatus are disclosed, such as those involving an inter-chip interface configured to receive and process electronic data. One such interface includes a receiver circuit that includes a clock tree configured to receive a clock signal at a clock tree input. The clock tree distributes a plurality of clock signals delayed from the clock signal such that one or more of the clock signals have a delay different from the delays of the other clock signals. The receiver circuit further includes a plurality of data input latches configured to receive a plurality of data elements over two or more different points in time. This configuration at least partially reduces crosstalk and simultaneous switching output noise.

Abstract: There is provided a communication apparatus capable of reducing power consumption. The communication apparatus in accordance with the present invention includes a synchronization detection block 30 which detects synchronization by performing a receiving process using a plurality of clocks whose phase differs from each other with respect to synchronization information contained in a first frame as well as identifies the synchronization detected clocks as candidate clocks to be selected; a clock phase selection block 40 which selects a sampling clock to be used for sampling of the transmission signal from the candidate clocks to be selected, selects a stop clock separated by a predetermined phase from the selected sampling clock, and outputs an instruction for the stop clock; and a clock gate unit 60 which, terminates supplying the stop clock from the plurality of clocks to the synchronization detection block 30 as well as supplies other clocks to the synchronization detection block 30.

Abstract: A communication system including a plurality of communication devices configured to operate according to a plurality of communication clock signals, respectively, wherein the plurality of communication clock signals are based on a common reference clock signal. The communication system further includes a phase-locked loop configured to generate an output signal in response to the common reference clock signal, wherein the output signal is in phase lock with the common reference clock signal; a signal division controller configured to generate a divider reset signal in response to a binary select signal; and a divider configured to generate one of the plurality of communication clock signals by performing frequency division of the output signal, wherein the divider reset signal controls a start time of the frequency division.

Abstract: A method for joint secondary synchronization signal detection and frame timing synchronization includes: (1) generating local secondary synchronization sequences SSC1—n and SSC2—n according to a sector number of a cell group; (2) converting a received time domain signal to a frequency domain signal to obtain secondary synchronization signals S1 and S2 to be detected; (3) performing inner product operation to obtain P1—n=P1—n?1+[S1,SSC1—n]+[S2,SSC2—n], and P2—n=P2—n?1+[S1,SSC2—n]+[S2,SSC1—n]; (4) selecting the maximum value P of absolute values of correlation values in the P1—n and P2—n, and judging whether the maximum value P is greater than a preset threshold Tmax, (5) if yes, taking the index of the maximum value P as an ID number of the cell group, or else, further carrying out step (2), and then further carrying out step (3).

Abstract: Methods for processing a signal of interest in an electrical power system are provided, as well as systems and computer program products for carrying out the methods. The methods include obtaining a representative window of data points from the signal of interest; obtaining a window of interest containing data points from the signal of interest; and comparing a phase drift compensated window to the representative window, wherein the compensated window is calculated in accordance with the window of interest and a phase drift that is present in the window of interest relative to the representative window.

Abstract: Disclosed is a method and apparatus for clock checking, to solve the problem of high resource occupation in existing clock checking methods. The method includes: a programmable device for performing frequency division on the source clock signal to obtain a reference clock signal; treating the source clock signal as a counting work clock to determine the counting value of rising edges and counting value of high levels of a clock signal being checked during each high level period out of N continuous high levels of the reference clock signal; and determining whether the clock signal being checked is valid according to the magnitude relationship between the counting value of the high levels of the clock signal being checked during each high level period and a first expected value, as well as the magnitude relationship between the counting value of the rising edges and a second expected value.

Abstract: A near field RF communicator has: an antenna operable to generate an RF signal to enable inductive coupling via the magnetic field of the RF signal between the antenna and another near field RF communicator or RF transponder in near field range; and a signal generator operable to generate a multi-level digital sine wave drive signal to drive the antenna to generate the RF signal, wherein the signal generator comprises a selector operable to select one or more digital sequences to provide one or more digital signals from which the digital sine wave drive signal is generated.

Abstract: A method of determining a residual frequency offset between a transmitter and a receiver in a transmission of data via a communication channel, is described, wherein the message is transmitted from the transmitter to the receiver via the communication channel and the message comprises at least one short preamble (201), at least one long preamble (202) and user data (203). The at least one long preamble (202) comprises residual frequency offset determination information based on which the residual frequency offset is determined.