With Frequency Detector And Phase Detector Patents (Class 375/375)
  • Patent number: 10340189
    Abstract: A method of forming a semiconductor device that includes providing a first set of fin structures having a first pitch, and a second set of fin structure having a second pitch, wherein the second pitch is greater than the first pitch. An epitaxial semiconductor material on the first and second set of fin structures. The epitaxial semiconductor material on the first fin structures is merging epitaxial material and the epitaxial material on the second fin structures is non-merging epitaxial material. A dielectric liner is formed atop the epitaxial semiconductor material that is present on the first and second sets of fin structures. The dielectric liner is removed from a portion of the non-merging epitaxial material that is present on the second set of fin structures. A bridging epitaxial semiconductor material is formed on exposed surfaces of the non-merging epitaxial material.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: July 2, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Balasubramanian Pranatharthiharan, Junli Wang, Ruilong Xie
  • Patent number: 10263761
    Abstract: This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: April 16, 2019
    Assignee: Rambus Inc.
    Inventors: Masum Hossain, Brian Leibowitz, Jihong Ren
  • Patent number: 10236212
    Abstract: A method of forming a semiconductor device that includes providing a first set of fin structures having a first pitch, and a second set of fin structure having a second pitch, wherein the second pitch is greater than the first pitch. An epitaxial semiconductor material on the first and second set of fin structures. The epitaxial semiconductor material on the first fin structures is merging epitaxial material and the epitaxial material on the second fin structures is non-merging epitaxial material. A dielectric liner is formed atop the epitaxial semiconductor material that is present on the first and second sets of fin structures. The dielectric liner is removed from a portion of the non-merging epitaxial material that is present on the second set of fin structures. A bridging epitaxial semiconductor material is formed on exposed surfaces of the non-merging epitaxial material.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: March 19, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Balasubramanian Pranatharthiharan, Junli Wang, Ruilong Xie
  • Patent number: 10090202
    Abstract: A method of forming a semiconductor device that includes providing a first set of fin structures having a first pitch, and a second set of fin structure having a second pitch, wherein the second pitch is greater than the first pitch. An epitaxial semiconductor material on the first and second set of fin structures. The epitaxial semiconductor material on the first fin structures is merging epitaxial material and the epitaxial material on the second fin structures is non-merging epitaxial material. A dielectric liner is formed atop the epitaxial semiconductor material that is present on the first and second sets of fin structures. The dielectric liner is removed from a portion of the non-merging epitaxial material that is present on the second set of fin structures. A bridging epitaxial semiconductor material is formed on exposed surfaces of the non-merging epitaxial material.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: October 2, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Balasubramanian Pranatharthiharan, Junli Wang, Ruilong Xie
  • Patent number: 10084623
    Abstract: Apparatus and methods are provide for a multichannel clock and data recovery (CDR) device that shares information between channels. In an example, a multiple channel communication circuit can include a plurality of clock and data recovery (CDR) circuits, each CDR circuit of the plurality of CDR circuits associated with a channel of the multiple channel communication circuit. In certain examples, each CDR circuit can be configured to detect an incoming stream of data from the channel, to determine a setting of one or more parameters for correctly sampling the data from the incoming stream, and to share an indication of the setting of the one or more parameters to an adjacent CDR circuit of the plurality of CDR circuits.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: September 25, 2018
    Assignee: Fmax Technologies, Inc.
    Inventors: Iain Ross Mactaggart, David Erich Tetzlaff
  • Patent number: 10057869
    Abstract: Disclosed is a network synchronization apparatus and method of a time division multiple access (TDMA)-based mesh network satellite communication system, the network synchronization method of a terminal in a satellite communication system including receiving timing error information from a central station, generating a mesh superframe start time (SST?) by reversing a sign of the timing error information, and receiving traffic information transmitted by a transmission terminal using the mesh SST?.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: August 21, 2018
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Joon Gyu Ryu, Soo Yeob Jung, Deock Gil Oh, Jonggyu Oh
  • Patent number: 10050771
    Abstract: This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: August 14, 2018
    Assignee: Rambus Inc.
    Inventors: Masum Hossain, Brian Leibowitz, Jihong Ren
  • Patent number: 10018674
    Abstract: Described is an apparatus which comprises: a state detector which is operable to detect logic states of zero and one in response to a clock edge; and an error detector coupled to the state detector, wherein the error detector is to detect an error in the detected logic states.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: July 10, 2018
    Assignee: Intel Corporation
    Inventors: Vinayak Honkote, Sriram R. Vangal
  • Patent number: 9769003
    Abstract: This application presents a direct data recovery from subspaces or parameters subranges of a received OFDM signal preidentified as corresponding to specific data symbols, by applying adaptive inverse signal transformation (AIST) method for reversing both original data coding and deterministic and random distortions introduced by a transmission channel, wherein both reversals are achieved by the same conversion of the subspaces or parameter subranges into data transmitted originally in order to eliminate an intermediate recovery of signals or parameters transmitted originally within the received OFDM signal. The AIST includes using both amplitudes and gradients of amplitudes of OFDM tone signals.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: September 19, 2017
    Inventor: John W Bogdan
  • Patent number: 9768947
    Abstract: This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: September 19, 2017
    Assignee: Rambus Inc.
    Inventors: Masum Hossain, Brian Leibowitz, Jihong Ren
  • Patent number: 9698969
    Abstract: A half-rate clock data recovery circuit includes: a voltage-controlled oscillator (VCO) for generating a data sampling clock and an edge sampling clock according to a control voltage; an adjusting circuit for dynamically controlling the VCO to adjust the phase difference between the data sampling clock and the edge sampling clock to be different from 90 degrees in multiple test periods; and a control circuit for instructing the adjusting circuit to respectively utilize different control value combinations to control the VCO in the multiple test periods, and for recording multiple recovered-signal quality indicators respectively corresponding to the multiple test periods. Afterwards, the control circuit instructs the adjusting circuit to utilize a control value combination corresponding to the best quality indicator among the multiple recovered-signal quality indicators to control the VCO.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: July 4, 2017
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Jian Liu
  • Patent number: 9680481
    Abstract: A phase detection circuit includes: a first circuit configured to generate a first phase detection signal that indicates a result of sampling a first clock signal at a transition timing of an input data signal; a second circuit configured to generate a second phase detection signal that indicates a result of sampling a second clock signal at the transition timing of the input data signal, a phase of the second clock signal being different from a phase of the first clock signal; and a third circuit configured to generate a third phase detection signal that indicates a phase of the first clock signal with respect to the input data signal based on the first phase detection signal and the second phase detection signal.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: June 13, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Yukito Tsunoda
  • Patent number: 9571144
    Abstract: Synchronized radio transceivers Disclosed are a method of and apparatus for controlling a first radio transceiver (18) and a second radio transceiver (20) which are connected to a common oscillator (16), wherein each transceiver (18, 20) is capable of communicating with one or more remote radio transceivers (12, 14). The method comprises: •the first transceiver (18) sending a synchronization signal to the second transceiver (20); and •the second transceiver (20) using the synchronization signal to en sure that neither transceiver (18, 20) transmits data while the other transceiver is in a receiving state.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: February 14, 2017
    Assignee: NORDIC SEMICONDUCTOR ASA
    Inventors: Kenneth Megard, Ole Saether, Ola Marvik, Frank Berntsen
  • Patent number: 9553684
    Abstract: A data frame generation circuit, includes: a frame generation unit configured to output a first data frame including client signals and a first signal count of the client signals included in the first data frame, the client signal being stored in the first data frame in accordance with a system clock; a storage unit configured to store a signal count range; a comparison unit configured to compare the first signal count to the signal count range; and a control unit configured to control a frequency of the system clock based on a comparison result, wherein, if the first signal count falls within the signal count range, the control unit changes the frequency of the system clock.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: January 24, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Hironobu Hongou
  • Patent number: 9407474
    Abstract: A phase detecting device and a clock data recovery circuit are provided. The phase detecting device includes a decision feedback equalizer having first and second sample-hold sub-circuits, an edge detector having a third sample-hold sub-circuit, a first XOR gate, and a second XOR gate. The first sample-hold sub-circuit, the second sample-hold sub-circuit and the third sample-hold sub-circuit obtain first sample data, second sample data and transition data, respectively. The first XOR gate executes an XOR operation for the first sample data and the transition data to generate first clock phase shift information. The second XOR gate executes the XOR operation for the second sample data and the transition data to generate second clock phase shift information. Therefore, high-frequency noise disturbance generated from conventional clock data recovery circuit and decision feedback equalizer can be avoided.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: August 2, 2016
    Assignee: National Chiao Tung University
    Inventors: Wei-Zen Chen, Yu-Ping Huang, Yau-Chia Liu, Zheng-Hao Hong
  • Patent number: 9385859
    Abstract: A serial data link receiver and method are provided. In one implementation, the receiver includes a first equalizer for receiving a first received signal and outputting a first equalized signal, and a second equalizer for receiving a second received signal and outputting a second equalized signal. The receiver further includes an analog CDR (clock-data recovery) circuit for receiving the first equalized signal and outputting a first recovered bit stream and a first recovered clock generated in accordance with an analog control voltage, and a digital CDR circuit for receiving the second equalized signal and the first recovered clock and outputting a second recovered bit stream and a second recovered clock based on selecting a phase of the first recovered clock in accordance with a digital phase selection signal.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: July 5, 2016
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Chi-Kung Kuan, Chia-Liang Lin
  • Patent number: 9379720
    Abstract: Clock data recovery can be accomplished using a phase path circuit that is configured to receive a data signal and a clock signal. A phase detection circuit detects phase differences between the data signal and a plurality of clock signals and generates a phase adjustment signal based upon a majority voting of the detected phase differences. Speculative calculation circuits generate speculative phase selection signals. Selection circuits select, in response to the phase adjustment signal, from speculative phase selection signals to provide outputs of the phase path circuit.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: June 28, 2016
    Assignee: XILINX, INC.
    Inventors: Yu Xu, Santiago G. Asuncion, Tianqi Tang, Toan Pham, Kun-Yung Chang
  • Patent number: 9344269
    Abstract: A receiving circuit includes circuits arranged in parallel, each circuits including a voltage-controlled-oscillator (VCO) configured to generate a clock having an oscillation frequency according to an inductor and a capacitor, and a gain circuit. Each circuit is configured to sample a piece of input data with an output clock of the VCO and adjust the oscillation frequency of the VCO based on a phase difference and a frequency difference between the piece of input data and the output clock, thereby recovering data and a clock based on the piece of input data. The gain circuit is configured to adjust ratios of gains of up and down of the oscillation frequency of the VCO in a loop in each circuit arranged adjacent to each other, based on a phase difference between the pieces of input data and a phase difference between the output clocks of the respective circuits.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: May 17, 2016
    Assignee: Fujitsu Limited
    Inventor: Takayuki Shibasaki
  • Patent number: 9337848
    Abstract: A clock and data recovery device is provided which includes a phase detector, a charge pump unit, a loop filter unit, and a voltage controlled oscillator. The phase detector detects a phase of a data clock signal to output a comparison signal. The charge pump unit adjusts the amount of charges to be supplied according to the comparison signal. The loop filter unit accumulates the amount of charges to be supplied to output an adjustment signal. The voltage controlled oscillator generates an output clock signal variable according to the adjustment signal. The phase detector compares phases of the data clock signal and each of modulated clock signals sequentially received to output the comparison signal. The modulated clock signals are signals modulated from the output clock signal to have different phases.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: May 10, 2016
    Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Woo-Young Choi, Dae-hyun Kwon, Young-Seok Park
  • Patent number: 9264026
    Abstract: A phase interpolation clock generator includes: a phase detector configured to detect a phase difference between an input signal and a clock; a phase control signal generator configured to generate a phase control signal that is inverted for a certain phase difference and changes between a high level and a low level based on the phase difference; a controller configured to generate a combining control signal for combining a plurality of phase clocks and performing phase interpolation based on the phase control signal; an overshoot detector configured to detect overshoot in which the phase control signal rises above the high level; an overshoot canceller configured to lower the phase control signal which rises above the high level at an occurrence of the overshoot; and a phase interpolator configured to generate the clock by combining the plurality of phase clocks in accordance with the combining control signal.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: February 16, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Takayuki Shibasaki, Yukito Tsunoda
  • Patent number: 9225344
    Abstract: A method of aligning clock signals in multiple transceiver channels on an integrated circuit may include adjusting a slave clock signal at a slave transceiver channel based on a master clock signal received from a master transceiver channel. A clock generation circuit and/or a delay circuit in the slave transceiver channel may be used to adjust the slave clock signal to produce an intermediate slave clock signal. The master clock signal may be adjusted based on the intermediate slave clock signal received at the master transceiver channel to obtain a total adjustment value. The phase of the intermediate slave clock signal may further be adjusted at the slave transceiver channel based on the total adjustment made at the master transceiver channel.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: December 29, 2015
    Assignee: Altera Corporation
    Inventors: Jakob Raymond Jones, David W. Mendel
  • Patent number: 9166843
    Abstract: A digital pulse width generator and a method for generating a digital pulse width are provided. The method for generating a digital pulse width includes the following. Generating a first period according to first set of bits of pulse data. The first period includes an interval. First phase signals are set to a first logic value in the interval and are generated according to first phase clock signals after an end of the interval. Second phase signals are set to the first logic value in the first period and are generated according to second phase clock signals after an end of the first period. Selecting a first signal from the first phase signals and the second phase signals according to second set of bits of the pulse data as a pulse width signal.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: October 20, 2015
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chao-Jen Huang, Ya-Ting Chang, Ke-Horng Chen
  • Patent number: 9093986
    Abstract: The present disclosure is directed generally to switch mode power supplies operating in a master-slave configuration and provides a method of synchronizing the PWM outputs from the master and slave devices to avoid problems such, for example, as the generation of beat frequencies.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: July 28, 2015
    Assignee: Powervation Limited
    Inventors: Eamon O'Malley, Paul Kelleher, Karl Rinne, Basil Almukhtar
  • Patent number: 9086437
    Abstract: Embodiments of this disclosure include methods in which spurs generated by the drifting of an oscillation frequency of an oscillation signal provided by a free-running oscillator may be minimized and/or eliminated from an output signal of a phase locked loop (PLL). Methods include minimizing the mixing gain between the oscillation signal and a power signal provided to the PLL. The oscillation signal and the power signal may be mixed in a phase frequency detector (PFD) included in the PLL. The minimizing of the mixing gain for the PFD also minimizes the degrading effect that the spurs have on the overall performance of the communications device. The mixing gain may be minimized by minimizing the impedance provided at nodes included in the PFD where the oscillation signal and the power signal mix. The mixing gain may also be minimized by maximizing the power supply rejection ratio for the PFD.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: July 21, 2015
    Assignee: Broadcom Corporation
    Inventors: Nikolaos Haralabidis, Ioannis Kokolakis, Georgios Konstantopoulos
  • Patent number: 9058465
    Abstract: Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may include a counter suitable for counting a number of times a programmable element in the lattice detects a condition. The counter may be configured to output in response to counting the condition was detected a certain number of times. For example, the counter may be configured to output in response to determining a condition was detected at least (or no more than) the certain number of times, determining the condition was detected exactly the certain number of times, or determining the condition was detected within a certain range of times. The counter may be coupled to other counters in the device for determining high-count operations and/or certain quantifiers.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: June 16, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Harold B Noyes, David R. Brown, Paul Glendenning
  • Patent number: 9036762
    Abstract: Techniques are disclosed relating to generating compatible clock signals. In one embodiment, an apparatus is configured to receive an input clock signal and a reference clock signal. In this embodiment, the apparatus includes a rate estimation unit and a phase-locked loop (PLL) unit. In this embodiment, the PLL unit is configured to generate, using a control signal from the rate estimation unit and the input clock signal, a PLL output clock signal. In this embodiment, the rate estimation unit is configured to adjust the control signal such that the PLL output clock signal and the reference clock signal are compatible. In this embodiment, the rate estimation unit is configured to adjust the control signal based on the reference clock signal and a comparison clock signal generated by the apparatus based on the PLL output clock signal.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: May 19, 2015
    Assignee: Silicon Laboratories Inc.
    Inventor: Brian D. Green
  • Patent number: 9031181
    Abstract: A multi-port information communication system includes a reference clock signal generator configured to generate a reference clock signal. The system also includes a phase controller configured to generate a plurality of information communication clock signals based on the reference clock signal by staggering a phase of each of the information communication clock signals. The phase controller includes a delay-locked loop configured to generate a plurality of delay-locked loop signals based on the reference clock signal, and a plurality of time delay elements. Each time delay element is configured to produce a respective one of the information communication clock signals by adding a respective delay to a respective one of the delay-locked loop signals. The system includes information communication devices each including a respective transmitter. Each of the transmitters is configured to operate in response to a respective one of the information communication clock signals.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: May 12, 2015
    Assignee: Marvell International Ltd.
    Inventor: Pierte Roo
  • Patent number: 9025650
    Abstract: A signal receiver is configured to receive multiple time-domain input signals. A plurality of the input signals among the multiple time-domain input signals is selected and transformed into frequency-domain signals. The frequency-domain signals are shifted in phase by a negative value of a respective reference phase, and the phase-shifted signals are combined into one signal. The combined signal is then multiplied with a stored signal to generate a signal product and transformed into a time-domain signal. Peak detection is performed on the time-domain signal.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: May 5, 2015
    Assignee: Neocific, Inc.
    Inventors: Titus Lo, Xiaodong Li
  • Patent number: 9025965
    Abstract: Disclosed are a phase locked loop (PLL) of a digital scheme and a method thereof. More specifically, disclosed are a digital phase locked loop having a time-to-digital converter (TDC), a digital loop filter (DLF), and a digitally controlled oscillator (DCO), and that is designed to have a constant jitter characteristic at all times even though an operating condition of a circuit varies according to a process, voltage, temperature (PVT) change, and a method thereof.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: May 5, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Seung Woo Lee, Kwang Chun Choi, Woo Young Choi, Bhum Cheol Lee
  • Patent number: 9020088
    Abstract: The present invention proposes a digital system and method of measuring (estimating) non-energy parameters of the signal (phase, frequency and frequency rate) received in additive mixture with Gaussian noise. The first embodiment of the measuring system consists of a PLL system tracking variable signal frequency, a block of NCO full phase computation (OFPC), a block of signal phase primary estimation (SPPE) and a first type adaptive filter filtering the signal from the output of SPPE. The second embodiment of the invention has no block SPPE, and NCO full phase is fed to the input of a second type adaptive filter. The present invention can be used in receivers of various navigation systems, such as GPS, GLONASS and GALILEO, which provide precise measurements of signal phase at different rates of frequency change, as well as systems using digital PLLs for speed measurements.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: April 28, 2015
    Assignee: Topcon Positioning Systems, Inc.
    Inventors: Mark I. Zhodzishsky, Victor A. Prasolov, Alexey S. Lebedinsky, Daniel S. Milyutin
  • Publication number: 20150103872
    Abstract: A method of compensating carrier tone generation between duty cycles includes receiving a carrier frequency signal and a reference frequency signal, where the carrier frequency signal is mixed with a communication signal in a signal path. The method includes determining a first and second time differences between the carrier frequency signal and the reference frequency signal at respective clock edges of the reference frequency signal. The method includes converting the first time difference to a first corresponding phase value and the second time difference to a second corresponding phase value based on an operating frequency, and determining a phase difference between the first corresponding phase value and the second corresponding phase value. In turn, the method includes adjusting the communication signal with the phase difference independent of the signal path to maintain phase continuity in the signal path between the duty cycles.
    Type: Application
    Filed: October 18, 2013
    Publication date: April 16, 2015
    Applicant: Broadcom Corporation
    Inventor: Alireza TARIGHAT MEHRABANI
  • Patent number: 9008196
    Abstract: A computer system includes a processor, and the processor includes at least one interface for communicating with an electronic component. Each of the at least one interface has a set of interface settings. The computer system further includes a memory containing machine executable instructions. Execution of the instructions causes the processor to: monitor communications traffic on the at least one interface; store, eye distribution data acquired during the monitoring of the communications traffic in a database; compare the eye distribution data to a set of predetermined criteria; and generate a set of updated interface settings if the eye distribution does not satisfy the set of predetermined criteria.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Frank W. Angelotti, Michael D. Campbell, Kenneth L. Christian, Martin Eckert, Hubert Harrer, Rohan Jones, Neil A. Malek, Gary A. Peterson, Andrew A. Turner, Dermot Weldon
  • Patent number: 9001869
    Abstract: A device for high-speed clock generation may include an injection locking-ring oscillator (ILRO) configured to receive one or more input clock signals and to generate multiple clock signals with different equally spaced phase angles. A phase-interpolator (PI) circuit may be configured to receive the multiple coarse spaced clock signals and to generate an output clock signal having a correct phase angle. The PI circuit may include a smoothing block that may be configured to smooth the multiple clock signals with different phase angles and to generate multiple smooth clock signals. A pulling block may be configured to pull edges of the multiple smooth clock signals closer to one another.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: April 7, 2015
    Assignee: Broadcom Corporation
    Inventors: Mahmoud Reza Ahmadi, Siavash Fallahi, Tamer Ali, Ali Nazemi, Hassan Maarefi, Burak Catli, Afshin Momtaz
  • Patent number: 9001275
    Abstract: HDMI is a digital audio and video communications protocol commonly used in consumer electronics. HDMI is particularly synonymous with high fidelity audio and video. Even though HDMI is a digital communications protocol, the audio quality can be impaired by analog signal impairments and distortions even if there are no digital decoding errors. In particular, the very process by which the audio is converted from Digital (HDMI) to human audible “Analog Audio” can be prone to errors. This occurs when the Digital to Analog Converter (DAC) clock, which is derived from the HDMI TMDS clock or HDMI source, is “distorted” due to its jitter, resulting in erroneous sampling or outputting of vital audio samples, thereby reducing the audio quality of the experience. The present invention reduces the jitter on the TMDS clock, and hence the audio DAC clock, resulting in lower audio distortion.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: April 7, 2015
    Inventors: Andrew Joo Kim, David Anthony Stelliga
  • Patent number: 8995598
    Abstract: A clock recovery circuit includes a first phase detector for measuring the phase difference between a first clock signal from a voltage controlled oscillator (VCO) and a data signal. A phase shifter responsive to a control signal based on this phase difference adjusts the phase of an incoming clock signal to yield a second clock signal. The phase difference between the first clock signal and the second clock signal is measured and the resulting signal is low-pass filtered to derive a control signal for controlling the VCO. The phase locked loop including the VCO filters out jitter.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: March 31, 2015
    Assignee: Rambus Inc.
    Inventor: Carl William Werner
  • Patent number: 8994425
    Abstract: A circuit includes first and second aligner circuits and a deskew circuit. The first aligner circuit is operable to align a first input serial data signal with a control signal to generate a first aligned serial data signal. The second aligner circuit is operable to align a second input serial data signal with the control signal to generate a second aligned serial data signal. The deskew circuit is operable to reduce skew between the first and the second aligned serial data signals to generate first and second output serial data signals.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: March 31, 2015
    Assignee: Altera Corporation
    Inventors: Ramanand Venkata, Henry Lui, Arch Zaliznyak
  • Patent number: 8989329
    Abstract: Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 24, 2015
    Assignee: Intel Corporation
    Inventors: Dima Hammad, Vadim Levin, Amir Laufer, Ron Bar-Lev, Noam Familia, Itamar Levin
  • Patent number: 8982974
    Abstract: Receiver synchronization techniques (RST), contributing more accurate synchronization of receiver clock to OFDM composite frame combined with much faster acquisition time and better stability of the receiver clock, and phase and frequency recovery techniques, comprising a software controlled clock synthesizer (SCCS) for high accuracy phase & frequency synthesis producing synchronized low jitter clock from external time referencing signals or time referencing messages wherein SCCS includes a hybrid PLL (HPLL) enabling 1-50,000 frequency multiplication with very low output jitter independent of reference clock quality.
    Type: Grant
    Filed: February 10, 2013
    Date of Patent: March 17, 2015
    Inventor: John W Bogdan
  • Publication number: 20150055552
    Abstract: A method and system is includes configurable carrier phase noise shaping. A fractional phase locked loop (PLL) uses a bank of delta-sigma modulators (DSM) to generate fractional ratios of the reference signal frequency. The bank of delta-sigma modulators provides for dynamic adjustments in the fractional PLL based phase noise performance of the communications network. The bank of DSMs is designed such that they have different and conflicting phase noise profiles. The communication network parameters are monitored and utilized for selecting a specific DSM from the bank of DSMs which most closely resembles a desired communications network phase noise profile.
    Type: Application
    Filed: September 30, 2013
    Publication date: February 26, 2015
    Inventors: Alireza Tarighat Mehrabani, Behzad Nourani
  • Patent number: 8964919
    Abstract: A system and method are provided for determining a time for safely sampling a signal of a clock domain. In one embodiment, a phase estimate of a first clock domain is calculated based on a relative frequency estimate between a second clock domain and the first clock domain and, based on the phase estimate, a first time during which a signal from the first clock domain is unchanging such that the signal is capable of being safely sampled by the second clock domain is determined to generate a first sampled signal in the second clock domain. Additionally, an updated phase estimate is calculated, and, based on the updated phase estimate, a second time during which the signal from the first clock domain is changing such that the signal is not capable of being safely sampled by the second clock domain is determined. During the second time the first sampled signal in the second clock domain is maintained.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: February 24, 2015
    Assignee: NVIDIA Corporation
    Inventor: Stephen G. Tell
  • Patent number: 8964922
    Abstract: Various embodiments of the present invention relate to systems, devices and methods of oversampling electronic components where high frequency oversampling clock signals are generated internally. The generated oversampling clock is automatically synchronous with the input clock and the input serial data in a serial data link, and is adaptive to predetermined parameters, such as bit depth and oversampling rate.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: February 24, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Matthew Felder, Mark Summers
  • Patent number: 8964899
    Abstract: Disclosed is a receiving circuit which includes: a data selection circuit selecting two input data located while placing in between the center phase of one unit interval of a binary input data; a correction circuit correcting the two input data selected by the data selection circuit; a phase detection circuit detecting a phase at which the level of input data changes as a boundary phase in the one unit interval, based on the two input data corrected by the correction circuit; an arithmetic unit calculating the center phase, based on the boundary phase detected by the phase detection circuit; and data decision circuit determining and outputting the level of one of the two input data, based on the center phase and the boundary phase, the correction circuit implements the correction based on a correction value corresponded to the past data level output by the data decision circuit.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: February 24, 2015
    Assignee: Fujitsu Limited
    Inventor: Hirotaka Tamura
  • Patent number: 8964925
    Abstract: Methods and systems to generate control signals for timing recovery of a signal received over baseband communications systems are disclosed. The timing control circuit uses a multi-rate DSP structure for the implementation of the DSP functions in the control loop for use in an ASIC and requires a reduced DSP clock rate, which in turn reduces the need for pipelining and/or high-speed libraries. Thus lower latency, better tracking performance and lower power consumption are achieved. An example embodiment involves splitting the timing error signal, supplied at a given update rate, into a sum and a difference component, and processing each component in separate circuit chains at half the update rate. The resultant half-rate control signals from each separate circuit chain are joined to provide a control signal at the full update rate. Thus, implementations of the present disclosure perform like a full-rate structure, but require a halved DSP clock rate.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: February 24, 2015
    Assignee: PMC-Sierra US, Inc.
    Inventor: Aryan Saed
  • Publication number: 20150043698
    Abstract: Systems and methods for stabilizing clock data recovery (CDR) by filtering the abrupt phase shift associated with data pattern transition in the input signal. The CDR circuit includes a data pattern detector coupled to a data pattern filter. The data pattern detector is capable of detecting the data patterns of the input signal. Accordingly, the data pattern filter can selectively generate a filter indication indicating to freeze or suppress the CDR phase caused by data pattern transition. The filter indication can be incorporated to a phase error signal, a gain function, and/or the control voltage driving the VCO.
    Type: Application
    Filed: August 12, 2013
    Publication date: February 12, 2015
    Applicant: NVIDIA CORPORATION
    Inventors: Yu CHANG, Huabo CHEN, Hakki OZGUC, Michael HOPGOOD
  • Patent number: 8948333
    Abstract: A clock frequency error detecting device includes a system storage portion which stores a synchronization system based on at least one of several types of frame synchronization signals included in a received signal in which a frame synchronization signal in each frame includes a part obtained by shifting of a frame synchronization signal of another frame by a symbol by using a predetermined rule; a pattern matching portion which performs pattern matching between the received signal and the synchronization system; a symbol counter which outputs a symbol number; a timing detection portion which detects the frame synchronization signal of each frame based on a pattern matching processing result and to output the symbol number at the detection timing; and a frequency error detection portion which detects a change of the symbol number and to detect a clock frequency error of the symbol period based on the detection.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: February 3, 2015
    Assignee: Kabiushiki Kaisha Toshiba
    Inventors: Noboru Taga, Tatsuhisa Furukawa
  • Patent number: 8947167
    Abstract: Embodiments provide a reference-less frequency detector that overcomes the “dead zone” problem of conventional circuits. In particular, the frequency detector is able to accurately resolve the polarity of the frequency difference between the VCO clock signal and the data signal, irrespective of the magnitude of the frequency difference and the presence of VCO clock jitter and/or ISI on the data signal.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: February 3, 2015
    Assignee: Broadcom Corporation
    Inventors: Mahyar Kargar, Siavash Fallahi, Namik Kocaman, Mehdi Khanpour, Afshin Momtaz
  • Patent number: 8942333
    Abstract: Apparatuses and methods for phase aligning at least two clocks used by respective first and second circuitry systems, such as a memory controller and a DDR PHY interface in a system on a chip system. A first circuit samples a phase of a first clock used by the first circuitry system, and then a delay circuit selectively delays a second clock used by the second circuitry system and sets a delayed timing of the second clock. To economize resources and reduce chip area, a logic circuit receives the sampled phase of the first clock, determines which delayed timing matches timing of the sampled phase, and sets the delay circuit to a fixed delayed timing corresponding to the delayed timing that matches the sampled phase. Thus, phase alignment of the two clocks is achieved with fewer resources.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: January 27, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Arvind Kumar, Shobhit Singhal, Vikas Lakhanpal, Kalpesh Amrutlal Shah
  • Patent number: 8942317
    Abstract: Apparatuses, methods and systems for mitigating carrier offset of a received signal are disclosed. One embodiment of a receiver includes a receiver chain operative to receive a communication signal from a desired transmitter, and a controller operative to determine a carrier offset correction based on prior reception of communication signals from the desired transmitter. The receiver chain is operative to generate a carrier offset corrected received signal by applying the carrier offset correction to the received communication signal, and a correlation processor operative to correlate the carrier offset corrected received communication signal with a known sequence.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: January 27, 2015
    Assignee: Imagination Technologies, LLC
    Inventor: Sujai Chari
  • Patent number: 8929500
    Abstract: The disclosed clock-data recovery architecture includes out-of-lock (including false lock) detection. Out-of-lock detection is accomplished by sampling retimed/recovered data with positive and negative edges of the received data. In example embodiments, an out-of-lock condition is determined either by detecting the occurrence of, or counting, missed edges corresponding to the failure of received data sampling to detect corresponding positive/negative edges of the retimed/recovered data.
    Type: Grant
    Filed: January 21, 2013
    Date of Patent: January 6, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Tonmoy S. Mukherjee, Arlo J. Aude
  • Patent number: 8923468
    Abstract: An exemplary clock and data recovery circuit includes a serial data input node arranged for receiving a serial data; a reference clock input node arranged for receiving a reference clock; a control circuit arranged for generating a control signal to selectively configure the clock and data recovery to operate in one of a plurality of phases; a detective circuit arranged for generating a first adjusting signal while the clock and data recovery operates in a frequency locking phase, and for generating a second adjusting signal while the clock and data recovery circuit operates in a clock and data recovery phase; and a controllable oscillator arranged for generating a recovered clock according to the first adjusting signal in the frequency locking phase, and for generating the recovered clock according to the second adjusting signal in the clock and data recovery phase.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: December 30, 2014
    Assignee: Realtek Semiconductor Corp.
    Inventors: Wei-Zen Chen, Ming-Chiuan Su, Yu-Hsiang Chen