Abstract: Methods and systems to generate control signals for timing recovery of a signal received over baseband communications systems are disclosed. The timing control circuit uses a multi-rate DSP structure for the implementation of the DSP functions in the control loop for use in an ASIC and requires a reduced DSP clock rate, which in turn reduces the need for pipelining and/or high-speed libraries. Thus lower latency, better tracking performance and lower power consumption are achieved. An example embodiment involves splitting the timing error signal, supplied at a given update rate, into a sum and a difference component, and processing each component in separate circuit chains at half the update rate. The resultant half-rate control signals from each separate circuit chain are joined to provide a control signal at the full update rate. Thus, implementations of the present disclosure perform like a full-rate structure, but require a halved DSP clock rate.

Abstract: Disclosed is a receiving circuit which includes: a data selection circuit selecting two input data located while placing in between the center phase of one unit interval of a binary input data; a correction circuit correcting the two input data selected by the data selection circuit; a phase detection circuit detecting a phase at which the level of input data changes as a boundary phase in the one unit interval, based on the two input data corrected by the correction circuit; an arithmetic unit calculating the center phase, based on the boundary phase detected by the phase detection circuit; and data decision circuit determining and outputting the level of one of the two input data, based on the center phase and the boundary phase, the correction circuit implements the correction based on a correction value corresponded to the past data level output by the data decision circuit.

Abstract: A system and method are provided for determining a time for safely sampling a signal of a clock domain. In one embodiment, a phase estimate of a first clock domain is calculated based on a relative frequency estimate between a second clock domain and the first clock domain and, based on the phase estimate, a first time during which a signal from the first clock domain is unchanging such that the signal is capable of being safely sampled by the second clock domain is determined to generate a first sampled signal in the second clock domain. Additionally, an updated phase estimate is calculated, and, based on the updated phase estimate, a second time during which the signal from the first clock domain is changing such that the signal is not capable of being safely sampled by the second clock domain is determined. During the second time the first sampled signal in the second clock domain is maintained.

Abstract: Various embodiments of the present invention relate to systems, devices and methods of oversampling electronic components where high frequency oversampling clock signals are generated internally. The generated oversampling clock is automatically synchronous with the input clock and the input serial data in a serial data link, and is adaptive to predetermined parameters, such as bit depth and oversampling rate.

Abstract: Systems and methods for stabilizing clock data recovery (CDR) by filtering the abrupt phase shift associated with data pattern transition in the input signal. The CDR circuit includes a data pattern detector coupled to a data pattern filter. The data pattern detector is capable of detecting the data patterns of the input signal. Accordingly, the data pattern filter can selectively generate a filter indication indicating to freeze or suppress the CDR phase caused by data pattern transition. The filter indication can be incorporated to a phase error signal, a gain function, and/or the control voltage driving the VCO.

Abstract: A clock frequency error detecting device includes a system storage portion which stores a synchronization system based on at least one of several types of frame synchronization signals included in a received signal in which a frame synchronization signal in each frame includes a part obtained by shifting of a frame synchronization signal of another frame by a symbol by using a predetermined rule; a pattern matching portion which performs pattern matching between the received signal and the synchronization system; a symbol counter which outputs a symbol number; a timing detection portion which detects the frame synchronization signal of each frame based on a pattern matching processing result and to output the symbol number at the detection timing; and a frequency error detection portion which detects a change of the symbol number and to detect a clock frequency error of the symbol period based on the detection.

Abstract: Embodiments provide a reference-less frequency detector that overcomes the “dead zone” problem of conventional circuits. In particular, the frequency detector is able to accurately resolve the polarity of the frequency difference between the VCO clock signal and the data signal, irrespective of the magnitude of the frequency difference and the presence of VCO clock jitter and/or ISI on the data signal.

Abstract: Apparatuses and methods for phase aligning at least two clocks used by respective first and second circuitry systems, such as a memory controller and a DDR PHY interface in a system on a chip system. A first circuit samples a phase of a first clock used by the first circuitry system, and then a delay circuit selectively delays a second clock used by the second circuitry system and sets a delayed timing of the second clock. To economize resources and reduce chip area, a logic circuit receives the sampled phase of the first clock, determines which delayed timing matches timing of the sampled phase, and sets the delay circuit to a fixed delayed timing corresponding to the delayed timing that matches the sampled phase. Thus, phase alignment of the two clocks is achieved with fewer resources.

Abstract: Apparatuses, methods and systems for mitigating carrier offset of a received signal are disclosed. One embodiment of a receiver includes a receiver chain operative to receive a communication signal from a desired transmitter, and a controller operative to determine a carrier offset correction based on prior reception of communication signals from the desired transmitter. The receiver chain is operative to generate a carrier offset corrected received signal by applying the carrier offset correction to the received communication signal, and a correlation processor operative to correlate the carrier offset corrected received communication signal with a known sequence.

Abstract: The disclosed clock-data recovery architecture includes out-of-lock (including false lock) detection. Out-of-lock detection is accomplished by sampling retimed/recovered data with positive and negative edges of the received data. In example embodiments, an out-of-lock condition is determined either by detecting the occurrence of, or counting, missed edges corresponding to the failure of received data sampling to detect corresponding positive/negative edges of the retimed/recovered data.

Abstract: A system and method for performing clock and data recovery. The system sets the phase of a recovered clock signal according to at least three estimates of the rate of change of an offset between the frequency of the data transmitter clock and the frequency of a receiver clock.

Abstract: An exemplary clock and data recovery circuit includes a serial data input node arranged for receiving a serial data; a reference clock input node arranged for receiving a reference clock; a control circuit arranged for generating a control signal to selectively configure the clock and data recovery to operate in one of a plurality of phases; a detective circuit arranged for generating a first adjusting signal while the clock and data recovery operates in a frequency locking phase, and for generating a second adjusting signal while the clock and data recovery circuit operates in a clock and data recovery phase; and a controllable oscillator arranged for generating a recovered clock according to the first adjusting signal in the frequency locking phase, and for generating the recovered clock according to the second adjusting signal in the clock and data recovery phase.

Abstract: A phase/frequency detector module, applicable to a digital phase-locked loop, includes: an edge detector for receiving a reference clock signal and a counting clock signal, where when a positive edge of the counting clock signal occurs, if a positive edge of the reference clock signal has occurred, the edge detector outputs an edge-detected signal, else the edge detector outputs an edge-not-detected signal; a counter coupled to the edge detector, where if receiving the edge-detected signal, the counter outputs a counting result forming a frequency error signal, resets, and loads a count value, and if receiving the edge-not-detected signal, the counter continues to count on the positive edge of the counting clock signal; and a frequency phase converter for performing integration over the counting result, where the integral forms a phase error signal.

Abstract: A correcting apparatus for timing recovery of a receiver is provided. The receiver includes a timing recovery module that outputs a first symbol and a second symbol. The correcting apparatus includes: a channel impulse response module, configured to generate a first set of peak times and a second set of peak times according to the first symbol and the second symbol, respectively; and a calculation module, configured to calculate a correction signal according to a relationship between the first and second sets of peak times and to send the correction signal to the timing recovery module.

Abstract: An N-phase clock generation circuit includes an input clock signal comprising a first phase signal, a phase interpolator configured to receive the input clock signal and generate a second phase signal, a first divider element configured to receive the first phase signal and generate an in-phase divided clock signal, a second divider element configured to receive the second phase signal and generate a quadrature divided clock signal, a first delay element configured to receive the in-phase divided clock signal and an in-phase control signal, the first delay element configured to generate a delayed in-phase divided clock signal, an a second delay element configured to receive the quadrature divided clock signal and a quadrature control signal, the second delay element configured to generate a delayed quadrature divided clock signal.

Abstract: The invention generally relates to phase locked loops (PLL), and more specifically to ultra-low bandwidth phase locked loops. The invention may be for example embodied in an integrated circuit implementing a phase locked loop or a method for operating a phase locked loop. The invention provides a PLL with a control stage that uses only two storage cells, a counter and a digital-to-analog (DAC) converter. In comparison to prior-art PLLs using storage cells the configuration of the invention's control stage reduces the chip area required for the PLL reduced. The invention further suggests PVT compensation mechanisms for a PLL and implementing a PLL that has lower peaking in its frequency response, which results in better settling response.

Abstract: A clock recovery circuit includes a first phase detector for measuring the phase difference between a first clock signal from a voltage controlled oscillator (VCO) and a data signal. A phase shifter responsive to a control signal based on this phase difference adjusts the phase of an incoming clock signal to yield a second clock signal. The phase difference between the first clock signal and the second clock signal is measured and the resulting signal is low-pass filtered to derive a control signal for controlling the VCO. The phase locked loop including the VCO filters out jitter.

Abstract: An approach is provided to mitigate phase noise by correcting common phase error and inter-carrier-interference in a received signal. The approach involves determining a received signal includes phase noise comprising at least a common phase error component and an inter-carrier-interference component. The approach also involves causing the common phase error to be corrected based on one or more pilot carriers. The approach further involves causing an estimate of a main signal component to be subtracted from the one or more pilot carriers. The approach additionally involves determining a sequence of estimated coefficients of a multiplicative phase noise sequence. The approach also involves causing the inter-carrier-inference to be corrected by processing the multiplicative phase noise sequence using the sequence of estimated coefficients. The approach further involves causing an equalized data signal to be output based on the corrected common phase error and the corrected inter-carrier-interference.

Abstract: A transmission apparatus for transmitting frames accommodating client data over a transmission network, comprising a clock generation unit that generates a clock for timing processing period of signal processing, a deviation detection unit that detects clock deviation between the clock generated by the clock generation unit and the clock used for timing processing period of signal processing by other transmission apparatus that receives the client data from outside the transmission network and adds them to frames, and a timing generation unit that generates timing signal of processing period of signal processing corrected with the clock deviation.

Abstract: A phase-locked loop system has a controlled oscillator that provides an output clock signal based on a oscillator control signal, a feedback path configured to provide a feedback signal based on the output clock signal, a phase detector configured to provide a phase dependent signal based on the feedback signal and a reference clock signal, a phase evaluation block configured to provide the oscillator control signal based on the phase dependent signal, a frequency detector that determines whether the frequency ratio between the output clock signal and the reference clock signal has a desired value, and a control logic. The control logic is configured to, during a start-up period, disable the phase evaluation block upon determination of the desired value of the frequency ratio; detect, after disabling the phase evaluation block, a subsequent clock edge of the reference clock signal; and enable, in response to the detection of the subsequent clock edge, the phase evaluation block.

Abstract: An ultra low power radio receiver architecture based on phase locked loop is provided. Embodiments of an ultra low power radio receiver architecture based on phase locked loop can detect a complex modulated MSK signal with only a single path receiver chain. According to an embodiment of the present invention, the overall power consumption of the radio receiver in the present invention can be reduced by almost fifty percent compared to that of the conventional complex path radio receiver architecture. The radio receiver architecture of the invention is suitable for the ultra low power radio application such as wireless sensor networks (WSN).

Abstract: A phase locked loop (PLL) device is configurable in an analog phase locked loop and a hybrid analog-digital phase locked loop. In an analog mode, at least a phase detector, an analog loop filter, and a voltage controlled oscillator (VCO), are connected to form an analog loop. In a digital mode, at least the phase detector, the voltage controlled oscillator (VCO), a time to digital converter (TDC), a digital loop filter and a digital to analog converter (DAC) are connected to form the hybrid digital-analog loop.

Abstract: Apparatuses, systems, and methods are directed to maintaining optimal carrier tracking performance in view of operating conditions that prevail. Such configurations employ a phase lock loop that configured to generate an estimated phase error value, a variance module configured to calculate a phase noise variance based on the estimated phase error value, and a loop control bandwidth module that calculates a loop bandwidth value based on a detected lower phase noise variance, generates modified loop filter values in accordance with the calculated loop bandwidth value, and updates the phase lock loop with the modified loop filter values. During subsequent iterations, the modified loop filter values are incrementally adjusted along a particular direction until the phase noise variance increases at which point the modified loop filter values are incrementally adjusted in an opposite direction to converge on an optimal loop bandwidth value.

Abstract: A system and method are provided for determining a time for safely sampling a signal of a dock domain. In one embodiment, a frequency estimate of a first clock domain is calculated utilizing a frequency estimator. Additionally, a time during which a signal from the first clock domain is unchanging is determined such that the signal is capable of being safely sampled by a second clock domain, using the frequency estimate. In another embodiment, a frequency estimate of a first dock domain is calculated utilizing a frequency estimator. Further, a phase estimate of the first clock domain is calculated based on the frequency estimate, utilizing a phase estimator. Moreover, a time during which a signal from the first clock domain is unchanging is determined such that the signal is capable of being safely sampled by a second clock domain, using the phase estimate.

Abstract: In one embodiment, a method includes adjusting a first frequency of a first clock signal based on a frequency difference between the first frequency and a reference clock signal frequency of a reference clock signal, and further adjusting the first frequency and a first phase of the first clock signal based on a phase difference between the first clock signal and an input data bit stream and the frequency difference between the first frequency and the reference clock signal frequency to substantially lock the first frequency and the first phase of the first clock signal to the input data bit frequency and input data bit phase of the input data bit stream.

Abstract: A temperature sensing circuit includes a signal generation unit including a delay line and generating a source signal with a pulse width corresponding to a delay value of the delay line, a pulse width expansion unit configured to generate a comparison signal by expanding a pulse width of the source signal, and a change detection unit configured to sense a temperature change using a difference between the pulse widths of the comparison signal and a reference signal.

Abstract: The present invention discloses a clock dejitter method comprising: a data sending adapter module inputting data with a system clock and using a sending clock to send data; a clock dejitter module associating the system clock with the sending clock of the data sending adapter module using; and the clock dejitter module tracking variations in the system clock and a data enable signal reflecting data sending state by referring to the system clock, and dynamically generating the sending clock varying with the data sending state. The present invention also discloses a clock dejitter apparatus and a data transmission system. The present invention greatly improves the free scheduling processing ability of services and reduces the bit error rate of data transmission while increasing efficiency of large capacity data switch transmission by dynamically adjusting the sending clock.

Abstract: Methods and apparatus are provided for determining one or more channel compensation parameters based on data eye monitoring. According to one aspect of the invention, a method is provided for evaluating the quality of a data eye associated with a signal. The received signal is sampled for a plurality of different phases, for example, using at least two latches, and the samples are evaluated to identify when the signal crosses a predefined amplitude value, such as a zero crossing. It is determined whether the points of predefined amplitude crossing satisfy one or more predefined criteria. One or more parameters of one or more channel compensation techniques can optionally be adjusted based on a result of the determining step. One or more parameters of an adjacent transmitter can also be adjusted to reduce near end cross talk based on a result of the determining step.

Abstract: A system and method are provided for resynchronizing a transmission signal using a jitter-attenuated clock derived from an asynchronous gapped clock. A first-in first-out (FIFO) memory accepts an asynchronous gapped clock derived from a first clock having a first frequency. The gapped clock has an average second frequency less than the first frequency. The input serial stream of data is loaded at a rate responsive to the gapped clock. A dynamic numerator (DN) and dynamic denominator (DD) are iteratively calculated for the gapped clock, averaged, and an averaged numerator (A and an averaged denominator (AD) are generated. The first frequency is multiplied by the ratio of AN/AD to create a jitter-attenuated second clock having the second frequency. The FIFO memory accepts the jitter-attenuated second clock and supplies data from memory at the second frequency. A framer accepts the data from the FIFO memory and the jitter-attenuated second clock.

Abstract: Mechanisms and techniques to evaluate data for a high speed I/O receiver logic. In an embodiment, a receiver circuit shifts a bit into a shift circuit in response to a rising edge of a data signal, where a count is started in response to the bit being subsequently shifted out of the shift circuit. Based on a value of the count, the receiver circuit generates a control signal for preparing physical layer receiver logic to transition to a burst mode of operation. In another embodiment, a receiver circuit includes a frequency divider to operate based on a data signal and a clock signal, wherein, based on operation of the frequency counter, a control signal is generated to indicate a line reset for physical layer receiver logic. The receiver circuit provides a feedback signal, based on the control signal, which is to limit activation of the frequency divider.

Abstract: Embodiments of the present disclosure provide a transmitter, a receiver and methods of operating a transmitter and a receiver. In one embodiment, the transmitter has at least three transmit antennas and includes a feedback decoding portion configured to recover at least one group-based channel quality indicator provided by a feedback signal from a receiver, wherein each group-based channel quality indicator corresponds to one of a set of transmission layer groupings. The transmitter also includes a modulator portion configured to generate at least one symbol stream and a mapping portion configured to multiplex each symbol stream to at least one transmission layer grouping. The transmitter further includes a pre-coder portion configured to couple the transmission layers to the transmit antennas for a transmission. The receiver includes a decoder portion which is configured to use decoded signals from at least one group to decode the other groups.

Abstract: A method for plesiochronous clock generation for parallel wireline transceivers, includes: inputting, into at least one decoder, at least one digital frequency mismatch number; decoding, with the at least one decoder, the at least one digital frequency mismatch number to obtain at least one digital frequency divider number that represents a transmit frequency associated with at least one signal; inputting the at least one digital frequency divider number into at least one fractional-N phase lock loop; and utilizing, by the at least one fractional-N phase lock loop, the at least one digital frequency divider number and an analog reference signal produced by a reference oscillator to produce a resultant signal at the transmit frequency; wherein the at least one decoder and the at least one fractional-N phase lock loop are contained on a single integrated circuit.

Abstract: An integrated circuit (“IC”) may include clock and data recovery (“CDR”) circuitry for recovering data information from an input serial data signal. The CDR circuitry may include a reference clock loop and a data loop. A retimed (recovered) data signal output by the CDR circuitry is monitored by other control circuitry on the IC for a communication change request contained in that signal. Responsive to such a request, the control circuitry can change an operating parameter of the CDR circuitry (e.g., a frequency division factor used in either of the above-mentioned loops). This can help the IC support communication protocols that employ auto-speed negotiation.

Abstract: Apparatuses, circuits, and methods are disclosed for reducing or eliminating unintended operation resulting from metastability in data synchronization. In one such example apparatus, a sampling circuit is configured to provide four samples of a data input signal. A first and a second of the four samples are associated with a first edge of a latching signal, and a third and a fourth of the four samples are associated with a second edge of the latching signal. A masking circuit is configured to selectively mask a signal corresponding to one of the four samples responsive to the four samples not sharing a common logic level. The masking circuit is also configured to provide a decision signal responsive to selectively masking or not masking the signal.

Abstract: An apparatus comprises a clock and data recovery system, and a loss of lock detector at least partially incorporated within or otherwise associated with the clock and data recovery system. The loss of lock detector is configured to generate a loss of lock signal responsive to phase adjustment requests generated for a clock signal in the clock and data recovery system. By way of example, the loss of lock signal may have a first logic level indicative of the phase adjustment requests occurring at a first rate associated with a lock condition and a second logic level indicative of the phase adjustment requests occurring at a second rate lower than the first rate. Absolute values of respective phase increments each associated with multiple up and down phase requests may be accumulated, and the loss of lock signal generated as a function of the accumulated phase increment absolute values.

Abstract: The PLL includes a voltage-controlled oscillator (VCO), a frequency down conversion circuit, a phase-frequency detector (PFD), and an adjusting circuit. The VCO is configured to generate an output clock signal. The frequency down conversion circuit is configured to receive the output clock signal and an auxiliary clock signal, and to mix the output clock signal and the auxiliary clock signal to generate a feedback clock signal. By detecting the strength of the feedback clock signal, it provides an auxiliary signal to adjust the frequency of the output clock signal. The PFD is configured to compare the frequencies and the phases of the feedback clock signal and a reference clock signal to generate an adjusting signal. The adjusting circuit is configured to receive the adjusting signal, and to adjust the frequency of the output clock signal generated by the VCO according to the adjusting signal.

Abstract: A method for frequency acquisition comprising steps of, acquiring samples of an input signal, each sample having edges, making sets with a fixed number of consecutively taken samples, numbering the edges in each set and determining a number of edges, comparing the number of edges in each set with an expected number of edges in the sets, increasing a frequency of a reference oscillator used in acquiring samples if the actual number of edges exceeds the expected number of edges, and decreasing the frequency of the reference oscillator used in acquiring samples if the expected number of edges exceeds the actual number of edges in a set.

Abstract: A clock and data recovery device receives a serial data stream and produces recovered clock and data signals. The clock and data recovery device operates over a range of frequencies and without use an external reference clock. A first loop supplies a first clock signal to a second loop. The second loop modifies the first clock signal to produce the recovered clock signal and uses the recover clock signal to produce the recovered data signal. The first loop changes the frequency of the first clock signal based on frequency comparison and data transition density metrics.

Abstract: The present disclosure provides a clock data recovery circuit that includes a phase locked loop unit, a delay locked loop unit and digital clock data recovery unit. The phase locked loop unit generates a clock signal based on a reference signal. The delay locked loop unit receives the clock signal from the phase locked loop, divides the clock signal into a plurality of clock signals and outputs the clock signals. The digital clock data recovery unit receives an input current signal, estimates a frequency of the input current signal, outputs a reference signal having the frequency, which can be transmitted to the phase locked loop unit, receives the clock signals from the delay locked loop, aligns a phase of the input current signal based on the clock signals and outputs an aligned current signal.

Abstract: An apparatus for correcting a phase error is provided. The apparatus includes an error estimating module and a correcting module. The error estimating module receives a phase-shift keying signal, and calculates a phase error according to the phase-shift keying signal, a plurality of known candidate signals and Bayesian estimation. The correcting module corrects the phase-shift keying signal according to the phase error.

Abstract: A frequency detector includes a multi-phase clock generation unit, a sampling unit connected to the multi-phase clock generation unit and a digital logic unit connected to the sampling unit. An inputted single-phase clock is received by the multi-phase clock generation unit and transformed into a multi-phase clock. Inputted random data are received by the sampling unit and sampled by the multi-phase clock. Each data bit of the random data is divided into several sampling intervals according to a phase number of the multi-phase clock. The digital logic unit analyzes sampling values logically, judges the corresponding sampling interval of each sampling value and outputs signals for indicating that a frequency of the random data is higher or lower than the frequency of the single-phase clock based on differences in the corresponding sampling intervals of the sampling values at two adjacent times. A method for detecting frequencies is further provided.

Abstract: A cascaded phase-locked loop (PLL) clock generation technique reduces frequency drift of a low-jitter clock signal in a holdover mode. An apparatus includes a first PLL circuit configured to generate a control signal based on a first clock signal and a first divider value. The apparatus includes a second PLL circuit configured to generate the first clock signal based on a low-jitter clock signal and a second divider value. The apparatus includes a third PLL circuit configured to generate the second divider value based on the first clock signal, a third divider value, and a second clock signal. The low-jitter clock signal may have a greater temperature dependence than the second clock signal and the second clock signal may have a higher jitter than the low-jitter clock signal.

Abstract: A semiconductor device includes: a clock and data recovery unit to which a receive signal is inputted and which extracts, based on an operation clock signal, a clock signal and a data signal from the receive signal; a frequency error adjusting unit which generates a frequency error signal indicating a frequency error between the clock signal extracted from the receive signal and the operation clock signal; a frequency error signal storage unit which stores the frequency error signal; an operation clock generation unit which controls, based on the frequency error signal, a frequency of the operation clock signal; and an SSCG unit which, based on the value of the frequency error signal stored in the frequency error signal storage unit, varies the operation clock signal generated by the operation clock generation unit by spreading the spectrum of the operation clock signal.

Abstract: A circuit for performing clock recovery according to a received digital signal 30. The circuit includes at least an edge sampler 105 and a data sampler 145 for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock 25 and data clock 20 signals offset in phase from one another to the respective clock inputs of the edge sampler 105 and the data sampler 145. The clock signal supply circuit is operable to selectively vary a phase offset between the edge and data clock signals.

Abstract: Circuit and method for resetting clock circuitry. The circuit includes a chain of cascading units, each of which receives an input of a number of parallel bit streams and outputs a different number of parallel bit streams. A chain of dividers provides one or more divided clock signals to the cascading units, wherein the divided clock signals are based on a gated common clock signal. An asynchronous reset signal is delivered to the dividers, and when asserted sets the dividers to a reset state. A clock source provides an ungated common clock signal. A clock gating circuit generates the gated common clock signal based on the ungated common clock signal, and is configured to hold the gated common clock signal while the asynchronous reset signal is asserted. The clock gating circuit provides the gated common clock signal to the dividers when the asynchronous reset signal is de-asserted.

Abstract: A clock data recovery circuit includes: an oscillator that outputs a clock signal; a phase comparator that outputs a signal corresponding to a phase difference between an input reception data signal and the clock signal; a divider that outputs a feedback clock signal; a first variable delay circuit that outputs a delay data signal; a second variable delay circuit that outputs a delay feedback clock signal; a frequency phase comparator that outputs a signal corresponding to a frequency difference and a phase difference between the delay data signal and the delay feedback clock signal; a lock detector that outputs a determination signal indicating whether or not the frequency difference and the phase difference are within a predetermined range; and a multiplexer that receives the determination signal and select a signal of the phase comparator and a signal of the frequency phase comparator.

Abstract: Embodiments of this disclosure include methods in which spurs generated by the drifting of an oscillation frequency of an oscillation signal provided by a free-running oscillator may be minimized and/or eliminated from an output signal of a phase locked loop (PLL). Methods include adjusting the free-running oscillator to prevent the oscillation frequency from drifting so that the spurs are eliminated. Performance data generated when the communications device engages a communications channel that is known not to generate spurs is compared to performance data generated when the communications device engages a desired communications channel. The free-running oscillator is adjusted until the two types of performance data are matched. Other methods include adjusting the dithering module of the PLL to prevent the oscillation frequency from drifting so that the spurs are eliminated.

Abstract: A frequency calibration apparatus and method are provided. A frequency calibration method includes determining a frequency band according to results of frequency comparisons between a synchronized reference signal whose phase is synchronized to a phase of a prescale signal and a divided signal, and performing a Phase Locked Loop (PLL) operation on a reference signal and the divided signal at the determined frequency band to lock the divided signal.

Abstract: The present invention relates to a phase error estimator, a coherent receiver and a phase error estimating method. The phase error estimator estimates a phase error in an inputted base band electric signal and feeds back said phase error; said phase error estimator comprises: a pre-decider, for judging a phase of data in said base band electric signal in accordance with said feedback phase error; a phase error complex value extracting section, for extracting a real part and an imaginary part of the phase error in accordance with the judgment result of said pre-decider; a phase error determining section, for determining said phase error in accordance with the real part and the imaginary part of the phase error extracted by the phase error complex value extracting section; and a time delay feeding back section, for delaying said phase error by N number of symbols and feeding back the delayed phase error to said pre-decider, wherein N is an integer greater than 1.

Abstract: A frequency synthesizer and a frequency synthesis method thereof are provided. The frequency synthesizer includes a phase-locked loop unit, a voltage-controlled oscillating unit, and a frequency mixing unit. The phase-locked loop unit receives a reference signal and a feedback injection signal and generates a first oscillating signal according to the reference signal and the feedback injection signal. The voltage-controlled oscillating unit receives the feedback injection signal and generates a second oscillating signal according to the feedback injection signal. The frequency mixing unit is coupled to the phase-locked loop unit and the voltage-controlled oscillating unit, receives the first oscillating signal and the second oscillating signal, and mixes the first oscillating signal and the second oscillating signal to generate the feedback injection signal and an output signal.