Abstract: A phase shift generation circuit has an edge detector, which outputs a first and a second edge signal. The circuit also has a divide by N circuit, which receives a first clock signal and a group of signals representing a number N, and outputs a second clock signal. The circuit further comprises a pulse counter, which receives the first edge signal and the second clock signal, and outputs a group of signals representing the number of the second clock pulses between occurrences of the first edge signal. The circuit has first and second recycling timers, which output a group of pulses approximating a uniformly spaced group across the time duration of the period of the input pulse. The circuit also comprises at least one flip flop which generates a phase shifted output pulse.

Abstract: This is a data reproduction circuit for receiving data and reproducing the data and its clock which has an over-sampling determination circuit for sampling the received data by a clock with frequency higher than the data rate of the received data and converting the sampled data into digital signals, a circuit for selecting and outputting the reproduced data, a phase error detection circuit for detecting a phase error from its timing deviation with the received data, based on the reproduced clock, a data selection circuit for adjusting its phase, based on the output of the phase error detection circuit, a phase adjustment circuit for adjusting the phase of the reproduced clock to reproduce a new clock and a clock generation circuit for supplying the over-sampling determination circuit and the data selection circuit with the newly reproduced clock.

Abstract: A Phase-Locked Loop (PLL) includes a Phase-to-Digital Converter (PDC), a programmable digital loop filter, a Digitally-Controlled Oscillator (DCO), and a loop divider. Within the PDC, phase information is converted into a stream of digital values by a charge pump and an Analog-to-Digital Converter (ADC). The stream of digital values is supplied to the digital loop filter which in turn supplies digital tuning words to the DCO. A number of types of ADCs can be used for the ADC including a continuous-time delta-sigma oversampling Digital ADC and a Successive Approximation ADC. The voltage signal on the charge pump output is a small amplitude midrange voltage signal. The small voltage amplitude of the signal leads to numerous advantages including improved charge pump linearity, reduced charge pump noise, and lower supply voltage operation of the overall PLL.

Abstract: A clock recovery circuit includes a first phase detector for measuring the phase difference between a first clock signal from a voltage controlled oscillator (VCO) and a data signal. A phase shifter responsive to a control signal based on this phase difference adjusts the phase of an incoming clock signal to yield a second clock signal. The phase difference between the first clock signal and the second clock signal is measured and the resulting signal is low-pass filtered to derive a control signal for controlling the VCO. The phase locked loop including the VCO filters out jitter.

Abstract: A transceiver node includes a pulse coupled oscillator in an integrated circuit, which can synchronize with other nodes to generate a global clock subsequently used to facilitate synchronous communications between individual nodes. Known potential uses include a low power sensor node radio for an ad-hoc network for military applications and medical applications such as ingestible and implantable radios, self powered radios, and medical monitoring systems such as cardiac and neural monitoring patches.

Abstract: A method of compensating for carrier frequency and phase errors of a received multi-carrier modulated signal. The received multi-carrier signal including modulated carriers for transmitting known data and unmodulated carriers for error correction, comprising, time domain down converting the received multi-carrier signal to base-band to provide a down-converted signal, the down-converted signal including a plurality of modulated carriers for transmitting known data and unmodulated carriers for error correction. Sampling an unmodulated carrier of the down-converted signal to provide received data samples. Providing a reference signal derived from the unmodulated carrier of the down-converted signal. And, estimating phase errors from a phase difference between the ummodulated carrier and the reference signal derived from the unmodulated carrier of the down-converted signal to provide a plurality of received sample phase error estimates for each modulated carrier.

Abstract: A technique that is readily implemented in monolithic integrated circuits includes a method including generating an output clock signal during a presence of a reference clock signal based, at least in part, on a digital control value indicating a phase difference between a feedback signal of a PLL and a reference clock signal. The method includes generating the output clock signal during an absence of the reference clock signal and based, at least in part, on an average digital control word indicating an average value of a number of samples of the digital control value during the presence of the reference clock signal, the number of samples preceding the absence of the reference clock signal by a delay period. The number of samples is selected from a plurality of numbers of samples and the delay period is selected from a plurality of delay periods.

Abstract: A phase detector includes a first sampling unit, a sampling module and a phase determining module. The first sampling unit is arranged for sampling a first data input signal to generate a first data signal according to a first clock signal. The sampling module includes a second sampling unit and a third sampling unit. The second sampling unit is arranged for sampling a second data input signal to generate a second data signal according to a second clock signal. The third sampling unit is arranged for sampling the second data signal to generate a third data signal according to the first clock signal. The phase determining module is arranged for generating a phase detecting result according to the first data signal and the third data signal.

Abstract: A device characteristic compensation circuit includes a device characteristic detection block configured to detect one or more of a frequency of a clock signal and characteristics of devices, and generate a control code signal according to a detection result; and an internal voltage regulation unit configured to regulate a level of an internal voltage in response to the control code signal and generate a corrected internal voltage.

Abstract: Methods and apparatus are provided for pseudo asynchronous testing of receive paths in serializer/deserializer (SerDes) devices. A SerDes device is tested by applying a source of serial data to a receive path of the SerDes device during a test mode. The receive path substantially aligns to incoming data using a bit clock. A phase is adjusted during the test mode of the bit clock relative to the source of serial data to evaluate the SerDes device. The source of serial data may be, for example, a reference clock used by a phase locked loop to generate the bit clock. The phase of the bit clock can be directly controlled during the test mode, for example, by a test phase control signal, such as a plurality of interpolation codes that are applied to an interpolator that alters a phase of the bit clock.

Abstract: A circuit includes a receiver circuit, a data valid monitor circuit, a clock signal generation circuit, and a phase shift circuit. The receiver circuit is operable to generate a first periodic signal, a sampled data signal based on an input data signal, and a data valid signal based on a predefined number of bits in the sampled data signal. The data valid monitor circuit is operable to generate a count value by counting periods of the first periodic signal. The data valid monitor circuit is operable to generate a phase error signal based on the data valid signal and the count value. The clock signal generation circuit is operable to generate a second periodic signal. The phase shift circuit is operable to generate a third periodic signal based on the second periodic signal and to adjust a phase of the third periodic signal based on the phase error signal.

Abstract: A phase locked loop device includes a phase detector that measures a difference in phase between a reference clock signal and an output clock signal provided to a device module. The phase detector provides a pulse having a width indicative of the phase difference. If the phase difference exceeds one of a plurality of threshold values, an indicator can be asserted. Based on the indicator, a control module can take remedial action, such as providing a different clock signal to the device module or triggering an interrupt at a processor device.

Abstract: A continuous-rate clock and data recovery circuit includes a delay locked loop with a first integrator and a phase locked loop with a separate integrator. The delay locked loop and the phase locked loop are in a dual loop architecture. The first integrator is a digital accumulator that wraps upon exceeding a maximum or minimum value. The second integrator is a digital accumulator that saturates at its maximum or minimum value.

Abstract: The invention relates to a clock generation circuit and a signal reproduction circuit including the clock generation circuit, and, more particularly, the invention provides a data judgment/phase comparison circuit capable of performing both of data judgment and phase comparison by a single-phase clock, and provides a CDR (Clock Data Recovery) circuit including the data judgment/phase comparison circuit. The same data and clock are inputted to two data judging units C_GOOD and C_BAD each having a different data determination period (setup/hold time) required for correctly judging a data, and an output of the data judging unit C_GOOD having a shorter required data determination period is taken as a data output of the data judgment/phase comparison circuit. When the outputs of both of the data judging units are different from each other, a signal Early indicating that a clock phase is too early or a signal Late indicating that the clock phase is too late is outputted.

Abstract: A method and mechanism for reducing lock time of a dual-path phase lock loop (PLL). The PLL comprises a dual-path low-pass filter (LPF). The LPF includes a first filter and a second filter. The first filter comprises a passive second-order lead-lag low-pass filter. The second filter comprises a first-order lag low-pass filter. During a lock-acquisition state, an impedance value within the second stage is bypassed, which increases the loop bandwidth of the PLL. In addition, a resistance within the first stage is increased in order to increase the gain of the first stage and maintain stability within the PLL. During a lock state, the impedance value may no longer be bypassed and the increased resistance may be returned to its original value.

Abstract: Embodiments provide a reference-less frequency detector that overcomes the “dead zone” problem of conventional circuits. In particular, the frequency detector is able to accurately resolve the polarity of the frequency difference between the VCO clock signal and the data signal, irrespective of the magnitude of the frequency difference and the presence of VCO clock jitter and/or ISI on the data signal.

Abstract: A communication device includes: a reception unit that receives a signal transmitted from another communication device via a transmission path; a transmission unit that transmits a signal to the another communication device via the transmission path; an error rate measurement unit that measures an error rate representing a probability of occurrence of errors in a signal received by the reception unit in a case where a bi-directional communication with the another communication device is performed; and a phase adjustment unit that adjusts a phase of a signal transmitted from the transmission unit to the another communication device based on an error rate measured by the error rate measurement unit.

Abstract: A transmission circuit that performs modulation based on a phase difference signal and an amplitude signal includes an asymmetrical phase rotation device. The asymmetrical phase rotation device performs an operation of subtracting 2? from a value of the phase difference signal when the value of the phase difference signal is greater than a predetermined positive threshold value, or an operation of adding 2? to the value of the phase difference signal when the value of the phase difference signal is less than a predetermined negative threshold value. Accordingly, the transmission circuit has distortion reduction characteristics improved uniformly over a range of frequencies higher or lower than a carrier wave band.

Abstract: The present invention relates to a multi-antenna subsystem for a SDR (software defined radio) capable of supporting a multi-antenna technique to an antenna system using a multi-antenna subsystem. The multi-antenna subsystem of a multi-antenna system includes an algorithm executing unit for carrying out an algorithm for a multi-antenna technique to be required in the multi-antenna system, a frame synchronization unit for a synchronization acquisition, and a control unit for controlling the algorithm executing unit and the frame synchronization. The algorithm executing unit has a plurality of functional blocks and the functional block has state information, which can be referred by other functional blocks, for supporting SDR system.

Abstract: A receiving circuit which receives serial data, includes: a voltage controlled oscillator which generates a sampling clock signal having a frequency based on an input control voltage; a first frequency divider which divides the frequency of the sampling clock signal at a division rate M; a second frequency divider which divides a frequency of a clock signal based on the received serial data at a division rate N, N being a real number represented by M×q/p; a frequency comparator which generates a phase/frequency difference signal based on a phase difference between an output signal of the first frequency divider and an output signal of the second frequency divider; and a control voltage generating circuit which generates the control voltage to control a frequency of the voltage controlled oscillator based on the phase/frequency difference signal.

Abstract: One embodiment of the present invention provides a phase-locked loop (PLL) for synthesizing a fractional frequency. The PLL can include a 1/N frequency divider, a voltage-controlled oscillator (VCO), a programmable phase mixer, and a phase detector. The programmable phase mixer can be coupled between an output of the VCO and an input of the frequency divider, wherein the programmable phase mixer is configured to receive the output clock signal from the VCO and generate a first clock signal of frequency f1 by varying a phase of the output clock signal. The frequency divider is configured to receive the first clock signal from the programmable phase mixer and generate a second clock signal of frequency f2=f1/N. The phase detector can receive a reference clock signal and the second clock signal as inputs, and the phase detector's output can be used to generate the control voltage for the VCO.

Abstract: A clock and data recovery circuit injects a noise waveform into the control loop to offset the data sampling point artificially in order to induce errors. The amplitude of the injected waveform can be varied to ascertain the effect on the bit error rate (BER) so as to be able to evaluate the temporal noise margin.

Abstract: A phase detection and decision feedback equalization circuit is provided. A first latch and a second latch are coupled to an input of the circuit. A third latch and a fourth latch are respectively coupled in series to outputs of the first latch and second latch. The first and fourth latches are enabled by a clock signal, and the second and third latches are enabled by a complement of the clock signal. A first feedback circuit is configured to provide a signal output from the first latch and a first feedback signal derived from the output of the fourth latch to an input of the third latch. A second feedback circuit is configured to provide a signal output from the second latch and a second feedback signal derived from the output of the third latch to an input of the fourth latch.

Abstract: According to one embodiment, a register outputs a first control code in first and second operation modes, saves the first control code as a third control code at an end of the first operation mode, and outputs the third control code at a beginning of a third operation mode. In the first operation mode, a digital-to-analog converter supplies a control signal with a control voltage to a voltage controlled oscillator. In the second operation mode, the control signal is supplied to a buffer amplifier, the amplifier drives a bandlimiting filter, and the filter generates the control voltage. In the third operation mode, the control signal is supplied to the filter, and the filter generates the control voltage.

Abstract: A communication system includes: a transmitter adapted to transmit a synchronizing clock and serial data synchronous with the synchronizing clock over a line at low amplitude; and a receiver adapted to receive the serial data and synchronizing clock from the transmitter. The receiver includes an amplifier adapted to amplify the received synchronizing clock of low amplitude to restore the clock to its original amplitude, a latched comparator adapted to latch the received serial data in synchronism with a reproduction clock, and a phase-locked circuit.

Abstract: One embodiment relates to an integrated circuit which includes a transmitter buffer circuit, a duty cycle distortion (DCD) detector, correction logic, and a duty cycle adjuster. The DCD detector is configured to selectively couple to the serial output of the transmitter buffer circuit. The correction logic is configured to generate control signals based on the output of the DCD detector. The duty cycle adjuster is configured to adjust a duty cycle of the serial input signal based on the control signals. Another embodiment relates to a method of correcting duty cycle distortion in a transmitter. Other embodiments and features are also disclosed.

Abstract: A transmitter includes a resistor, a protection unit, and a transmission unit. The resistor control unit controls a connection of a termination resistor between first and second transmission lines. The protection unit reduces first and second voltages, respectively, from the first and second transmission lines during a power-down mode. The transmission unit receives the dropped first and second voltages during the power-down mode and transmits first and second signals through the protection unit during a power-on mode. The resistor control unit connects the termination resistor to the first and second transmission lines when a transmission rate of the first and second signals is equal to or greater than a predetermined value. The resistor control unit is disconnected from at least one of the first and second transmission lines when the transmission rate is less than the predetermined value.

Abstract: A clock and data recovery (CDR) architecture which includes a frequency detector, a phase detector, a phase charge pump circuit, a frequency charge pump circuit and a voltage controlled oscillator is provided. The phase detector is configured to only include four AND gates to receive and evaluate the intermediate signals, generated by the frequency detector, and accordingly generate a phase control signal. The voltage controlled oscillator is configured to output a plurality of clock signals with different phases according to the current signals outputted from the phase and frequency charge pump circuits, and select at least one of the plurality of clock signals with different phases for sampling a data signal.

Abstract: A system and method for performing clock and data recovery. The system sets the phase of a recovered clock signal according to at least three estimates of the rate of change of an offset between the frequency of the data transmitter clock and the frequency of a receiver clock.

Abstract: Provided is a signal processing apparatus including: an equalizer circuit that amplifies a predetermined frequency band of an input signal and outputs an output signal; a sampler circuit that samples the output signal amplified by the equalizer circuit with the output signal being offset in an amplitude direction using a multiphase clock system; an area information calculation circuit that calculates area information of an eye opening in an eye diagram of the output signal based on the output signal sampled by the sampler circuit; and a control circuit that controls amplification of the equalizer circuit based on the area information of the eye opening calculated by the area information calculation circuit.

Abstract: A linear phase detector includes an up/down pulse generator operating in response to received data signals and a recovered clock signal. The phase detector generates up and down pulses that have pulse widths proportional to the phase differences between transitions of the received data signals and edges of the recovered clock signal. By generating up and down pulses using a linear phase detector in proportion to a phase error, data signals are effectively recovered, even data signals with significant jitter.

Abstract: A method and apparatus for generating a carrier frequency signal is disclosed. The method includes generating a first frequency signal; injecting a modulation signal at a first point of the two-point modulation architecture; generating a second frequency signal from the modulation signal; introducing the second frequency signal by mixing the first frequency signal and the second frequency signal to generate a mixed frequency signal and outputting the carrier frequency signal selected from the mixed frequency signal.

Abstract: A phase locked loop includes a voltage controlled oscillator operable to generate an output signal corresponding to a reference signal in response to a control voltage signal outputted by a filter in response to a current signal, and a variable frequency divider operable to perform frequency division on the output signal using a variable divisor so as to generate a divided feedback signal. A charge pump outputs the current signal in response to a phase detecting output from a phase/frequency detector indicating phases of the divided feedback signal and the reference signal. A phase error comparator outputs, in accordance with the phase detecting output, a digital output indicating whether the divided feedback signal lags or leads the reference signal and further indicating a phase difference between the divided feedback signal and the reference signal.

Abstract: A spread spectrum clock generator includes a triangular modulator, a delta sigma modulator, a frequency divider, and a phase lock loop. The triangular modulator generates a digital modulation signal, representing a decimal, according to a digital parallel signal, in which the spread amount is in proportion to the digital parallel signal. The delta sigma modulator, electrically connected to the triangular modulator, generates a divider divisor, including the decimal and an integer, according to the digital modulation signal. The frequency divider divides the frequency of the output signal clock according to the divider divisor to generate a divided clock signal, in which the frequency of the divided clock signal is substantially equal to a quotient result from dividing the frequency of the output clock signal with the divider divisor. The phase lock loop adjusts the frequency of the output clock signal according to the divided clock signal and a reference clock signal.

Abstract: A clock data recovery circuit includes a receiving circuit that takes in input data based on a sampling clock, a demultiplexer that converts serial data output from the receiving circuit into parallel data, a clock/data recovery part that detects phase information from the parallel data output from the demultiplexer and generates the sampling clock by adjusting the phase of a reference clock based on the phase information, a data pattern analyzer that carries out frequency analysis of the parallel data output from the demultiplexer, and an aliasing detector that detects a clock recovery state based on the analysis result of the frequency of the parallel data.

Abstract: A computer system with a phase detector that generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating select signals having duty cycles corresponding to the phase relationship between the clock edges of the first and second clock signals. The phase detector also includes a charge pump that receives select signals from the phase detector circuits and produces an increasing or decreasing control signal when the first and second clock signals do not have the predetermined phase relationship, and a non-varying control signal when the first and second clock signals do have the predetermined phase relationship. The delay value of a voltage-controlled delay circuit and the phase relationship between the first and second clock signals to a predetermined phase relationship are thereby adjusted.

Abstract: A digital waveform synthesizer (1) is implemented as a single chip integrated circuit on a single chip (2) and comprises a direct digital synthesizer (10) which produces a synthesized output signal waveform on an output terminal (4) which is substantially phase and frequency locked to the phase and frequency of an externally generated input signal applied to an input terminal (5).

Abstract: A system and method are provided for determining a time for safely sampling a signal of a clock domain. In one embodiment, a frequency estimate of a first clock domain is calculated utilizing a frequency estimator. Additionally, a time during which a signal from the first clock domain is unchanging is determined such that the signal is capable of being safely sampled by a second clock domain, using the frequency estimate. In another embodiment, a frequency estimate of a first clock domain is calculated utilizing a frequency estimator. Further, a phase estimate of the first clock domain is calculated based on the frequency estimate, utilizing a phase estimator. Moreover, a time during which a signal from the first clock domain is unchanging is determined such that the signal is capable of being safely sampled by a second clock domain, using the phase estimate.

Abstract: A circuit with adaptive synchronization and a method thereof is provided. The synchronous receiving circuit adaptively adjusts the timing of a clock signal generated therein for receiving data without accompanying a clock signal for synchronization. The synchronous receiving circuit includes a clock generator, an edge detector, a synchronization unit and a latch. The clock generator generates a first clock signal according to an input data signal. The edge detector detects edges to generate an indication signal. The synchronization unit is coupled to the clock generator and the edge detector, and adaptively adjusts the first clock signal according to the indication signal. The latch latches the input data signal according to the adjusted first clock signal.

Abstract: Disclosed herein is a synchronization circuit including: a first phase-locked loop circuit; a second phase-locked loop circuit; a first output circuit; a second output circuit; a first detection circuit; a second detection circuit; and a control circuit.

Abstract: In the following B cycles, the second frequency-divided signal fA is maintained at a low level, while the third frequency-divided signal fB is maintained at a high level. The three-modulus prescaler 13 has a frequency division value (M?1) if the pseudo random values are negative values, and a frequency division value (M+1) if the pseudo random values are positive values, in accordance with the signs of the pseudo random values outputted from the ?? modulator 8. After that, the frequency division value becomes M. A frequency division value of (MN+A+Bx) including the pseudo random value Bx is obtained in the comparison frequency divider 4. A fractional frequency division operation can be realized through ?? modulation by using the pseudo random numbers including negative values, as they are.

Abstract: A circuit comprises a first phase detector, a second phase detector, and combinational logic. The first phase detector is for detecting a phase difference between a rising edge of a first clock signal and a rising edge of a second clock signal, and for providing a first difference signal indicating the phase difference. The second phase detector is for detecting a phase difference at a time of a falling edge of the first clock signal and a time of a falling edge of the second clock signal, and for providing a second difference signal indicating the phase difference. The combinational logic is coupled to receive the first difference signal and the second difference signal, and for preventing the second difference signal from being provided when the first difference signal is being provided.

Abstract: A method for countervailing clock skew between a first clock signal and a second clock signal in a core logic circuit. The second clock signal is sampled based on the first clock signal in a sampling cycle to obtain a sampling result. When the sampling result indicates a non-compliant pattern, the phase of at least one of the first clock signal and the second clock signal is adjusted. Desirably, the core logic circuit keeps on working with the current first and second clock signals while continuing the sampling procedure of the second clock signal based on the first clock signal when the sampling result indicates a compliant pattern.

Abstract: A data receiver circuit includes: a clock/data recovery circuit to recover a clock and data from a received signal; a fixed pattern generation circuit to generate fixed pattern data; a first selection circuit to select and output one of the fixed pattern data generated by the fixed pattern generation circuit and recovered data recovered by the clock/data recovery circuit; a second selection circuit to select and output one of a reference clock and recovered clock recovered by the clock/data recovery circuit; and a switching circuit to make the first selection circuit output the fixed pattern data and to make the second selection circuit output the reference clock, when an input signal is lost or the clock/data recovery circuit is in a loss-of-lock state.

Abstract: Consistent with the present disclosure, clock-and-data recovery (CDR) circuitry and driver circuitry are provided on a chip that is separate from the driver circuitry, thereby reducing the amount of power consumed by the driver circuitry and simplifying system design. In one example, timing of the ERZ signals is controlled by a feedback loop that adjusts the phase of a data carrying signal relative to a clock signal, such that the phase has a desired value. Timing of the ERZ signals may thus be adjusted to minimize errors.

Abstract: Disclosed herein are embodiments of an improved built-in self-test (BIST) circuit and an associated method for measuring phase and/or cycle-to-cycle jitter of a clock signal. The embodiments of the BIST circuit implement a Variable Vernier Digital Delay Locked Line method. Specifically, the embodiments of the BIST circuit incorporate both a digital delay locked loop and a Vernier delay line, for respectively coarse tuning and fine tuning portions of the circuit. Additionally, the BIST circuit is variable, as the resolution of the circuit changes from chip to chip, and digital, as it is implemented with standard digital logic elements.

Abstract: A method of dynamically adjusting phase-chasing speed for increasing efficiency of a DLL circuit includes detecting an overall loop delay for an input clock signal in the DLL circuit, obtaining an optimal divisor according to the overall loop delay, and in the phase-locking period of the DLL circuit, dividing the frequencies of the input clock signal and a feedback clock signal corresponding to the input clock signal according to the optimal divisor.

Abstract: A VCO oscillates at a frequency that corresponds to a control voltage. A frequency mixer performs frequency mixing of the output signal of the VCO and a local signal having a local frequency. A first filter extracts a difference frequency signal obtained by the mixing operation of the mixer. A phase difference detection unit makes a comparison between the phase of the difference frequency signal extracted by the first filter and the phase of a reference signal having a reference frequency, and generates a phase difference signal that corresponds to the phase difference. A loop filter performs filtering of the phase difference signal so as to generate the control signal. A second filter extracts a summation frequency signal obtained by the mixing operation of the mixer, and outputs the summation frequency signal via an output terminal thereof.

Abstract: A programmable filter for LC tank voltage controlled oscillator (VCO) and a design structure for a programmable filter for LC tank VCO. The programmable filter includes a proportional control comprising a plurality of capacitance biased by different input voltages and an integral control comprising a filter element with a capacitance C1 and a set of capacitance biased by a voltage output of the filter element.

Abstract: Apparatus, methods, and systems are disclosed, including, for example, a data receiver to receive a calibration voltage and a reference voltage to calibrate the data receiver. The output of the data receiver is provided to a first ripple counter that counts the outputs from the data receiver and provides an output count. The ripple counter may count either ones or zeros. A second ripple counter counts the number of a clock signals over the same period of time. The output count is either multiplied by two or the count of clock signals is divided by two. A ripple comparator may then compare the outputs and adjust the reference voltage based upon the comparison results.