Abstract: A multi-link input/output (I/O) interface uses both feed-forward and feedback signaling to reduce the impact of noise on data capture at a memory controller. To transfer data from a source module to a destination module, a defined pattern is communicated from the memory module along a master channel concurrent with the memory module providing data via one or more slave channels. Based on the phase of the defined pattern as it is received, the multi-link I/O interface feeds forward to the slave channels control signaling whose phase reflects a predicted noise pattern for the system. Each slave channel performs CDR by adjusting timing of its corresponding capture clock signal based on the fed forward control signaling and based on feedback signaling for the corresponding slave channel, whereby the feedback signaling reflects an error measurement between a phase of a capture clock signal and transitions in received data.

Abstract: A method for clock recovery and data recovery from a data stream on a communication channel includes sampling a data stream on the communication channel at a sampling frequency determined by a clock signal and generating a sampled signal. The method further includes determining a phase shift between the communication data stream and the sampled signal and modifying the phase of the clock signal on the basis of the phase shift to obtain a desired phase difference between the sampled signal and the data stream.

Abstract: A multi-port information communication system includes a reference clock signal generator configured to generate a reference clock signal. The system also includes a phase controller configured to generate a plurality of information communication clock signals based on the reference clock signal by staggering a phase of each of the information communication clock signals. The phase controller includes a delay-locked loop configured to generate a plurality of delay-locked loop signals based on the reference clock signal, and a plurality of time delay elements. Each time delay element is configured to produce a respective one of the information communication clock signals by adding a respective delay to a respective one of the delay-locked loop signals. The system includes information communication devices each including a respective transmitter. Each of the transmitters is configured to operate in response to a respective one of the information communication clock signals.

Abstract: A method of generating an unambiguous correlation function for a TMBOC(6,1,4/33) signal, an apparatus for tracking a TMBOC signal, and a satellite navigation signal receiver system using the same are disclosed herein.

Abstract: Disclosed are a phase locked loop (PLL) of a digital scheme and a method thereof. More specifically, disclosed are a digital phase locked loop having a time-to-digital converter (TDC), a digital loop filter (DLF), and a digitally controlled oscillator (DCO), and that is designed to have a constant jitter characteristic at all times even though an operating condition of a circuit varies according to a process, voltage, temperature (PVT) change, and a method thereof.

Abstract: Embodiments are described for a method and system of enabling updates from a clock controller to be sent directly to a predictive synchronizer to manage instant changes in frequency between transmit and receive clock domains, comprising receiving receive and transmit reference frequencies from a phase-locked loop circuit, receiving receive and transmit constant codes from a controller coupled to the phase-locked loop circuit, obtaining a time delay factor to accommodate phase detection between the transmit and receive clock domains, and calculating new detection interval and frequency information using the time delay factor, the reference frequencies, and the constant codes.

Abstract: This disclosure describes techniques for generating signals that have relatively steep frequency profiles with a phase-locked loop (PLL) circuit architecture. In some examples, the techniques for generating signals that have relatively steep frequency profiles may include modulating an amplitude of a forward path signal in a PLL circuit at a location in a forward circuit path of the PLL circuit based on a control signal. The control signal may have an amplitude profile that is determined based on a target frequency profile to be generated by the PLL circuit. Modulating the forward circuit path of the PLL circuit with a signal that is determined based on a target frequency profile may allow a PLL-based frequency synthesizer to generate signals with relatively steep frequency profiles while still maintaining acceptable levels of phase noise.

Abstract: An integrated circuit (10) has an internal RC-oscillator (20) for providing an internal clock signal (CLI) having an adjustable oscillator frequency. The integrated circuit (10) further comprises terminals (101, 102) for connecting an external LC tank (30) having a resonance frequency and a calibration circuit (40) which is configured to adjust the oscillator frequency based on the resonance frequency of the LC tank (30) connected during operation of the integrated circuit (10). An internal auxiliary oscillator (46) is connected to the terminals (101, 102) in a switchable fashion and is configured to generate an auxiliary clock signal (CLA) based on the resonance frequency. The calibration circuit (40) comprises a frequency comparator (47) which is configured to determine a trimming word (TRW) based on a frequency comparison of the internal clock signal (CLI) and the auxiliary clock signal (CLA). The LC tank (30) to be connected is an antenna for receiving a radio signal.

Abstract: The present invention proposes a digital system and method of measuring (estimating) non-energy parameters of the signal (phase, frequency and frequency rate) received in additive mixture with Gaussian noise. The first embodiment of the measuring system consists of a PLL system tracking variable signal frequency, a block of NCO full phase computation (OFPC), a block of signal phase primary estimation (SPPE) and a first type adaptive filter filtering the signal from the output of SPPE. The second embodiment of the invention has no block SPPE, and NCO full phase is fed to the input of a second type adaptive filter. The present invention can be used in receivers of various navigation systems, such as GPS, GLONASS and GALILEO, which provide precise measurements of signal phase at different rates of frequency change, as well as systems using digital PLLs for speed measurements.

Abstract: A calibration system may be provided for calibrating wireless communications circuitry in an electronic device during manufacturing. The calibration system may include data acquisition equipment and calibration computing equipment for receiving and processing test and calibration signals from wireless communications circuitry to be calibrated. During testing and calibration operations, a device may be provided with initial pre-distortion calibration values. The initial pre-distortion calibration values may be generated at least in part based on calibration operations performed for other wireless electronic devices. The device may generate a test signal using the initial pre-distortion calibration values. The calibration system may determine whether the test signal is within an acceptable range of a known reference signal.

Abstract: A digitally controlled oscillator has a high-order ?? modulator configured to be of at least an order higher than a first order and configured to input a digital control signal and output a pseudorandom digital output signal, a first-order ?? modulator configured to input the pseudorandom digital output signal and generate a control pulse signal including a pulse width corresponding to the pseudorandom digital output signal, a low pass filter configured to pass a low frequency component of the control pulse signal, and an oscillator configured to generate a high-frequency output signal whose frequency is controlled based on the control pulse signal outputted by the low pass filter so as to be a frequency corresponding to the digital control signal.

Abstract: The present invention relates to a method includes: implementing, by the board in the BBU1, frequency synchronization between a system clock of the board in the BBU1 and a system clock of the board in the BBU0 by using a synchronous Ethernet clock that is output by the board in the BBU0; and implementing, by the board in the BBU1, time synchronization between the system clock of the board in the BBU1 and the system clock of the board in the BBU0 by using an IEEE1588 clock that is output by the board in the BBU0. The present invention can enable the multimode base station to support more standards.

Abstract: Systems and methods for efficient jitter mitigation or removal from a gapped signal. A phase mitigation module is employed to generate discrete correction values for modifying phase error signals detected between a gapped signal and a feedback signal of the PLL. The correction values can be digitally subtracted from the output of a phase frequency detector associated with the PLL. The sequence of correction values can be determined based on phase frequency differences between the input signal and a targeted feedback signal that is free of jitter and has a period equal to an average period of the input signal. An average of the correction values is substantially equal to zero, and an average of the modified phase error signal is substantially equal to zero.

Abstract: In an example embodiment, a phase-locked loop circuit may include a first circuitry to receive a reference signal and a source signal. The first circuitry may generate a correction signal for demonstrating a difference in phase between the reference signal and the source signal. The phase-locked loop may include a second circuitry to receive the correction signal. The second circuitry may generate a digital signal for demonstrating a phase-to-digital conversion of the correction signal. The phase-locked loop may include a third circuitry to receive the digital signal. The third circuitry may generate a control signal for demonstrating a converted voltage of the digital signal. The phase-locked loop may include a fourth circuitry to receive the control signal. The fourth circuitry may generate the source signal in response to the control signal.

Abstract: Various aspects of the present disclosure are directed apparatuses and methods including a first phase locked loop (PLL) circuit and a second PLL circuit. The first PLL circuit receives a carrier signal that is transmitted over a communications channel from a non-synchronous device, and generates a PLL-PLL control signal. The second PLL circuit receives a stable reference-oscillation signal, and, in response to the PLL-PLL control signal indicating a frequency offset, adjusts a fractional divider ratio of the second PLL circuit. The first PLL circuit and the second PLL circuit are configured to produce an output frequency signal that is synchronous to the carrier signal.

Abstract: A transceiver comprising a first frequency signal generator for generating a reception frequency signal, and a second frequency signal generator for generating a transmission frequency signal. The first frequency signal generator is coupled to the second frequency signal generator to supply the reception frequency signal to the second frequency signal generator as a reference frequency signal.

Abstract: A method for generating an output clock comprising: detecting a timing difference between a first input clock and a second input clock to generate a phase error signal; generating a masked phase error signal by masking the phase error signal based on a deterministic jitter indicator signal; generating an oscillator control signal by filtering the masked phase error signal; and generating the output clock in accordance with the oscillator control signal.

Abstract: A control method utilized in a clock data recovery device supporting a plurality of frequency bands, for controlling the clock data recovery device to select an operating frequency band from the plurality of frequency bands and to generate a recovery clock for generating retimed data, includes receiving a serial data stream with a data frequency; making each frequency band of the plurality of frequency bands correspond to a plurality of frequency band groups, wherein each frequency band group includes at least one frequency band and corresponds to different frequency ranges; selecting a frequency band group from the plurality of frequency band groups as a coarse-tuned frequency band group according to the data frequency and a locking voltage range; and selecting a frequency band from the plurality of frequency bands according to the data frequency, the locking voltage range and the coarse-tuned frequency band group for generating the recovery clock.

Abstract: A spurious frequency attenuation servo is provided. The spurious frequency attenuation servo includes a first function generator that generates a first signal at a first frequency and at a spurious frequency; a second function generator that generates a second signal in-phase with the first signal and at the spurious frequency; a third function generator that generates a third signal ninety degrees out-of-phase with the first signal and at the spurious frequency; in-phase and quadrature-phase mixers to input a feedback signal and the second and third signals, respectively; in-phase and quadrature-phase error accumulators; an in-phase and quadrature-phase multiplier to multiply an output from the in-phase and quadrature-phase error accumulators with the second and third signals, respectively; and a summing node to sum the first signal with output from the in-phase and quadrature-phase multipliers to form an output signal that is fed back to the in-phase mixer and the quadrature-phase mixer.

Abstract: A phase-locked loop digital bandwidth calibrator includes a digital loop filter having a gain multiplier memory and a perturbation unit configured to generate a calibration offset signal to initiate a calibration. Additionally, the phase-locked loop digital bandwidth calibrator also includes a digital bandwidth calibration unit configured to provide a corrected nominal gain for storage in the gain multiplier memory, wherein a digital gain correction for the corrected nominal gain is determined by a digital integration stage and a correction database. A phase-locked loop digital bandwidth calibration method is also provided.

Abstract: Systems and methods for efficient jitter mitigation or removal from a gapped signal. A phase mitigation module is employed to generate discrete correction values for modifying phase error signals detected between a gapped signal and a feedback signal of the PLL. The correction values can be digitally subtracted from the output of a phase frequency detector associated with the PLL. The sequence of correction values can be determined based on phase frequency differences between the input signal and a targeted feedback signal that is free of jitter and has a period equal to an average period of the input signal. An average of the correction values is substantially equal to zero, and an average of the modified phase error signal is substantially equal to zero.

Abstract: A device for high-speed clock generation may include an injection locking-ring oscillator (ILRO) configured to receive one or more input clock signals and to generate multiple clock signals with different equally spaced phase angles. A phase-interpolator (PI) circuit may be configured to receive the multiple coarse spaced clock signals and to generate an output clock signal having a correct phase angle. The PI circuit may include a smoothing block that may be configured to smooth the multiple clock signals with different phase angles and to generate multiple smooth clock signals. A pulling block may be configured to pull edges of the multiple smooth clock signals closer to one another.

Abstract: A phase-locked loop having: an oscillator for forming an oscillating output signal; a frequency divider connected to receive the output of the oscillator and frequency divide it by a value dependent on a division control signal; and a phase comparator for comparing the phase of the divided signal and a reference signal to generate a control signal, the operation of the oscillator being dependent on the control signal; a first mode of operation in which the frequency divider is configured to operate in dependence on a first division control signal such that the resultant oscillating output signal has a first frequency and first phase, a second mode of operation in which the frequency divider is configured to operate in dependence on a second division control signal such that the resultant oscillating output signal has a second frequency and second phase, the first division control signal being generated independently of the oscillating output signal such that the first phase is maintained when the phase-locked

Abstract: HDMI is a digital audio and video communications protocol commonly used in consumer electronics. HDMI is particularly synonymous with high fidelity audio and video. Even though HDMI is a digital communications protocol, the audio quality can be impaired by analog signal impairments and distortions even if there are no digital decoding errors. In particular, the very process by which the audio is converted from Digital (HDMI) to human audible “Analog Audio” can be prone to errors. This occurs when the Digital to Analog Converter (DAC) clock, which is derived from the HDMI TMDS clock or HDMI source, is “distorted” due to its jitter, resulting in erroneous sampling or outputting of vital audio samples, thereby reducing the audio quality of the experience. The present invention reduces the jitter on the TMDS clock, and hence the audio DAC clock, resulting in lower audio distortion.

Abstract: A circuit includes first and second aligner circuits and a deskew circuit. The first aligner circuit is operable to align a first input serial data signal with a control signal to generate a first aligned serial data signal. The second aligner circuit is operable to align a second input serial data signal with the control signal to generate a second aligned serial data signal. The deskew circuit is operable to reduce skew between the first and the second aligned serial data signals to generate first and second output serial data signals.

Abstract: A clock recovery circuit includes a first phase detector for measuring the phase difference between a first clock signal from a voltage controlled oscillator (VCO) and a data signal. A phase shifter responsive to a control signal based on this phase difference adjusts the phase of an incoming clock signal to yield a second clock signal. The phase difference between the first clock signal and the second clock signal is measured and the resulting signal is low-pass filtered to derive a control signal for controlling the VCO. The phase locked loop including the VCO filters out jitter.

Abstract: A phase interpolator (PI) is provided to adjust the phase of a clock such that the phase is aligned to an incoming data pattern from a data stream. The data can be captured from a device such as a flip-flop or the like. The present technique uses a PI (digital to phase) and a digital state machine in a feedback loop to set the correct digital code to the PI inputs to achieve an appropriate clock phase. Of course, there can be variations.

Abstract: A phase-locked loop circuit includes phase detection circuitry to generate a first control signal based on a phase comparison between first and second periodic signals. An oscillator circuit causes a frequency of a third periodic signal to vary based on the first control signal. A frequency divider circuit divides the frequency of the third periodic signal by a frequency division value to generate a frequency of the second periodic signal. A delta sigma modulator circuit controls the frequency division value based on second control signals. First storage circuits store the second control signals based on third control signals in response to a fourth periodic signal. A second storage circuit stores an output signal based on a fourth control signal. The fourth periodic signal is generated based on the output signal of the second storage circuit.

Abstract: A frequency synthesizer capable of generating a clock signal having reduced digital spurs and reduced jitter is described. An apparatus includes a frequency modulator configured to generate a divide control signal and a digital quantization error signal in response to a divide ratio. The apparatus includes a phase modulator configured to generate a phase error signal based on the digital quantization error signal. The phase modulator is an n-order sigma-delta modulator module, n being an integer greater than one. The apparatus may include an interpolative divider configured to generate a feedback signal in a phase-locked loop (PLL) based on an output signal of the PLL, the divide control signal, and the phase error signal. The interpolative divider may include the frequency modulator and the phase modulator. The phase modulator may have a unity gain signal transfer function.

Abstract: A clock data recovery method includes: integrating an input data signal over a number of cycles of a sample clock to generate an integrated signal; performing a digital process on the integrated signal to output a first digital signal; interpolating the first digital signal in accordance with phase information to generate interpolation data; outputting phase difference data indicating a difference in phase of the interpolation data from the sample clock; performing a filtering process on the phase difference data to generate the phase information; performing an equalization process on the interpolation data in accordance with output data; and performing a binary decision on results of the equalization process to generate the output data.

Abstract: A clock and data recovery circuit with built in jitter tolerance test is disclosed. Imposing jitter on a filter inside a CDR loop to cause phase disturbances to the clock and data recovery circuit, thereby to test the jitter tolerance of the clock and data recovery circuit. Accordingly, IC test cost is significantly reduced by increasing few circuit sizes.

Abstract: Disclosed are systems and method for controlling frequency synthesizers. A control system can be implemented in a phase-locked loop (PLL), such as a Frac-N PLL of a frequency synthesizer, to reduce or eliminate reference spurs. In some embodiments, such a control system can include a phase detector configured to receive a reference signal and a feedback signal. The phase detector can be configured to generate a first signal representative of a phase difference between the reference signal and the feedback signal. The control system can further include a charge pump configured to generate a compensation signal based on the first signal. The control system can further includes an oscillator configured to generate an output signal based on the compensation signal. The compensation signal can be configured to reduce or substantially eliminate one or more reference spurs associated with the frequency synthesizer.

Abstract: Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.

Abstract: The present invention provides a receiver, including: a crystal oscillator, a phase-locked loop, a radio frequency module, an analog baseband processing module, an adjusting module, and a digital baseband processing module, where the radio frequency module demodulates a radio signal to obtain an original analog baseband signal; the analog baseband processing module processes the original analog baseband signal to obtain a first digital baseband signal; when demodulating the first digital baseband signal, the digital baseband processing module detects the rate deviation and sends the rate deviation to the phase-locked loop; and the adjusting module adjusts the first digital baseband signal, so that a rate of an adjusted first digital baseband signal is consistent with a rate of a preset reference signal.

Abstract: A clock alignment detector described herein can detect alignment between clock signals within a defined margin of error, such as a defined margin of phase error. The margin of phase error can be varied to achieve various degrees of lock detection precision. Clock alignment detector can detect alignment between rising edges of the clock signals, falling edges of the clock signals, or both the rising and falling edges of the clock signals. The clock alignment detector can be implemented as a lock detector for a phase-locked loop that is configured to detect and maintain a phase relationship between a reference clock signal and a feedback clock signal, where the clock alignment detector detects alignment between the reference clock signal and the feedback clock signal.

Abstract: To reduce the influence of a spurious in a high-frequency signal processing device and a wireless communication system each provided with a digital type PLL circuit. In a digital type PLL circuit including a digital phase comparator unit, a digital low-pass filter, a digital control oscillator unit, and a multi-module driver unit (frequency divider unit), the clock frequency of a clock signal in the digital phase comparator unit is configured selectably among a plurality of options. The clock frequency is selected among frequencies which are integer multiples of a reference frequency, in accordance with which frequency band of a standard is to be set for an oscillation output signal of the digital control oscillator unit.

Abstract: Aspects of the disclosure provide a phase-locked loop (PLL). The PLL includes a voltage-controlled oscillator (VCO), a detector module, and a ramp module. The VCO has a first capacitor unit and a second capacitor unit. The VCO is configured to generate an oscillating signal having a frequency based on a first capacitance of the first capacitor unit and a second capacitance of the second capacitor unit. The detector module is configured to generate a voltage signal as a function of the oscillating signal and a reference signal. The voltage signal is used to control the first capacitor unit to stabilize the frequency of the oscillating signal. The ramp module is configured to generate a ramp signal based on the voltage signal. The ramp signal is used to control the second capacitor unit to ramp the second capacitance from a first value to a second value.

Abstract: Receiver synchronization techniques (RST), contributing more accurate synchronization of receiver clock to OFDM composite frame combined with much faster acquisition time and better stability of the receiver clock, and phase and frequency recovery techniques, comprising a software controlled clock synthesizer (SCCS) for high accuracy phase & frequency synthesis producing synchronized low jitter clock from external time referencing signals or time referencing messages wherein SCCS includes a hybrid PLL (HPLL) enabling 1-50,000 frequency multiplication with very low output jitter independent of reference clock quality.

Abstract: An encoder includes an encoding unit that performs encoding according to a predetermined encoding method, a production unit that produces a special code which is not stipulated in the predetermined encoding method and which exhibits a higher bit change rate than that produced according to the predetermined encoding method does, and an encoding output unit that, if input data items which have not been encoded by the encoding unit are identical to each other, outputs encoded data into which a preceding one of the input data items is encoded by the encoding unit, and outputs a special code as encoded data, into which the succeeding one of the input data items is encoded, successively to the encoded data.

Abstract: In order to provide a circuit which can realize high-speed frequency tracking performance while satisfying jitter/wander suppression performance, the circuit controls loop gain of a PLL means, which extracts a clock signal of a SDH signal or an Ethernet signal from an OTN signal, on the basis of a result of processing a jitter/wander component and a frequency change state on the basis of phase comparison data of the PLL means.

Abstract: Aspects of the present disclosure relate to floating point timers and counters that are used in a variety of contexts. In some implementations, a floating point counter can be used to generate a wave form made up of a series of pulses with different pulse lengths. An array of these floating point counters can be used to implement a pool of delays. In other implementations, an array of floating point counters can be used to analyze waveforms on a number of different communication channels. Analysis of such waveforms may be useful in automotive applications, such as in wheel speed measurement for example, as well as other applications.

Abstract: According to some embodiments, a method and apparatus are provided to vary a clock signal frequency for a first time period between a lower limit of a range of problematic frequencies and a frequency lower than the lower limit, and vary the clock signal frequency for a second period of time between an upper limit of the range of problematic frequencies and a frequency greater than the upper limit.

Abstract: A device communicating with a node, includes a communication unit configured to transmit a transmitting data segment to the node, and receive a receiving data segment from the node. The device further includes a phase locked loop (PLL) configured to generate an operating frequency for the communication unit. The device further includes a PLL controller configured to control a hold time and a lock time, of the PLL, that are shared between the node and the device. The device further includes a scheduler configured to schedule the transmitting data segment and the receiving data segment based on the controlled hold time and lock time.

Abstract: A time-to-digital conversion circuit for converting a time difference between two input signals to a 1-bit digital value, and adjusting the time difference between the two input signals to generate two output signals includes: a phase comparator configured to compare phases of the two input signals with each other to generate the digital value; a phase selector configured to output one of the two input signals which has a leading phase as a first signal, and the other of the two input signals which has a lagging phase as a second signal; and a delay unit configured to output the first signal with a delay, wherein the time-to-digital conversion circuit outputs the signal output from the delay unit and the second signal as the two output signals.

Abstract: Various aspects of the present disclosure are directed apparatuses and methods including a first phase locked loop (PLL) circuit and a second PLL circuit. The first PLL circuit receives a carrier signal that is transmitted over a communications channel from a non-synchronous device, and generates a PLL-PLL control signal. The second PLL circuit receives a stable reference-oscillation signal, and, in response to the PLL-PLL control signal indicating a frequency offset, adjusts a fractional divider ratio of the second PLL circuit. The first PLL circuit and the second PLL circuit are configured to produce an output frequency signal that is synchronous to the carrier signal.

Abstract: According to one embodiment, a wireless transceiver system includes a transmitter and a receiver. The transmitter includes a first generator, a second generator, a third generator. The second generator generates fixed data item that has bit values corresponding to the clock signal. The third generator performs OFDM modulation for the fixed data item. The receiver includes a first detector, a second detector, a PLL, a controller. The first detector is configured to detect an envelope that indicates amplitude in a time waveform. The controller is configured to control to operate the PLL from a first time point when the head part is detected to a second time point when a first period is elapsed.

Abstract: A signal processing circuit includes a PLL circuit configured to lock to a frequency contained in an input signal, a signal generating circuit configured to detect a direct-current component of a signal that is obtained by shifting frequencies of the input signal by a displacement equal to the locked frequency, and to generate a signal that has an amplitude responsive to the detected direct-current component and that has the same frequency and phase as a signal component of the locked frequency of the input signal, and a subtraction circuit configured to subtract the signal generated by the signal generating circuit from the input signal.

Abstract: In one example, a system includes an oscillator adapted to provide an oscillator signal, a frequency divider adapted to divide the oscillator signal to provide a divided oscillator signal, and a phase-frequency detector adapted to provide phase-frequency detection signals in response to a reference clock signal and the divided oscillator signal. The system also includes a charge pump adapted to provide first output signals in response to the phase-frequency detection signals, a phase detector adapted provide second output signals in response to an incoming data signal and the oscillator signal, and one or more switches adapted to pass the first output signals during a frequency acquisition mode and pass the second output signals during a phase lock mode. The system also includes an active filter adapted to filter the passed first or second output signals. The oscillator is adapted to adjust a frequency of the oscillator signal in response to the filtered first or second output signals.

Abstract: A method includes relocating, to a frequency outside a cut-off frequency of a phase-locked loop, a spur frequency component at an input of the phase-locked loop coupled thereto due to an interference of a divided frequency component of an output frequency of the phase-locked loop with a reference clock frequency input thereto through a feedback path thereof when there is a near-integer relationship between the reference clock frequency input and the output frequency. The method also includes filtering the spur frequency component through the phase-locked loop.

Abstract: Disclosed is a receiving circuit which includes: a data selection circuit selecting two input data located while placing in between the center phase of one unit interval of a binary input data; a correction circuit correcting the two input data selected by the data selection circuit; a phase detection circuit detecting a phase at which the level of input data changes as a boundary phase in the one unit interval, based on the two input data corrected by the correction circuit; an arithmetic unit calculating the center phase, based on the boundary phase detected by the phase detection circuit; and data decision circuit determining and outputting the level of one of the two input data, based on the center phase and the boundary phase, the correction circuit implements the correction based on a correction value corresponded to the past data level output by the data decision circuit.