Abstract: The present invention relates to an information processing apparatus, a method, and a program capable of suppressing deterioration of content quality. An integrated reception buffer time adjustment unit 114 obtains a maximum transmission delay time that is the longest delay time among the transmission delays of data transmission performed by each reception unit 113. The reception buffer time setting unit 208 calculates a reception buffer time using the maximum transmission delay time, a transmission delay time of the data transmission by the reception unit 113, and a prescribed reception buffer time. The reception buffer time setting unit 208 sets various delay times and waiting times such as a variable compression encoding delay time, a redundant encoding block reception waiting time, an ARQ retransmission packet waiting time, and a network jitter handling buffer time from the reception buffer time. The present invention can be applied to an information processing apparatus, for example.

Abstract: A system and method are provided for determining a time for safely sampling a signal of a clock domain. In one embodiment, a phase estimate of a first clock domain is calculated based on a relative frequency estimate between a second clock domain and the first clock domain and, based on the phase estimate, a first time during which a signal from the first clock domain is unchanging such that the signal is capable of being safely sampled by the second clock domain is determined to generate a first sampled signal in the second clock domain. Additionally, an updated phase estimate is calculated, and, based on the updated phase estimate, a second time during which the signal from the first clock domain is changing such that the signal is not capable of being safely sampled by the second clock domain is determined. During the second time the first sampled signal in the second clock domain is maintained.

Abstract: A phase-locked loop (PLL) circuit is provided. The PLL circuit includes a phase frequency detector (PFD), a first charge pump (CP), a second CP, a first loop component set, a second loop component set, a voltage control oscillator (VCO) and a frequency divider. The first CP and the second CP are coupled to the PFD. The first loop component set is coupled between the first CP and the VCO. The second loop component set is coupled between the second CP and the VCO. The frequency divider is coupled between the PFD and the VCO. The first loop component set generates an offset current to adjust the working range of the first CP and the second CP. The second loop component set generates an offset current and a DC adjustment voltage to control the control voltage outputted to the VCO.

Abstract: Methods and systems to generate control signals for timing recovery of a signal received over baseband communications systems are disclosed. The timing control circuit uses a multi-rate DSP structure for the implementation of the DSP functions in the control loop for use in an ASIC and requires a reduced DSP clock rate, which in turn reduces the need for pipelining and/or high-speed libraries. Thus lower latency, better tracking performance and lower power consumption are achieved. An example embodiment involves splitting the timing error signal, supplied at a given update rate, into a sum and a difference component, and processing each component in separate circuit chains at half the update rate. The resultant half-rate control signals from each separate circuit chain are joined to provide a control signal at the full update rate. Thus, implementations of the present disclosure perform like a full-rate structure, but require a halved DSP clock rate.

Abstract: There is described a time-to-digital conversion scheme using an arrangement of delay elements based Time-to-Digital Converter, TDC (20), wherein dithering is built in the digital domain and introduced in the analog domain as a modulation of a supply voltage (TDC-supply) supplying delay elements of the TDC, each having a propagation delay which exhibits a dependency to their supply voltage.

Abstract: Various embodiments of the present invention relate to systems, devices and methods of oversampling electronic components where high frequency oversampling clock signals are generated internally. The generated oversampling clock is automatically synchronous with the input clock and the input serial data in a serial data link, and is adaptive to predetermined parameters, such as bit depth and oversampling rate.

Abstract: A connecting interface unit and a memory storage device without a crystal oscillator are provided and include following circuits. A phase detector detects a phase difference between a first reference signal and an input signal from a host system to generate a phase signal. A signal detecting circuit detects a signal character difference between the input signal and the first reference signal for a signal generating circuit to generate a second reference signal. A phase interpolator generates a clock signal according to the phase signal and the second reference signal. A sampling circuit generates an input data signal according to the clock signal. A transmitter circuit modulates an output data signal according to the clock signal or the second reference signal to generate an output signal, and transmits it to the host system. Accordingly, the connecting interface unit conforms to the specification of a transmission standard.

Abstract: Described is an apparatus comprising: a first phase frequency detector (PFD) to determine a coarse phase difference between a first clock signal and a second clock signal, the first PFD to generate a first output indicating the coarse phase difference; and a second PFD, coupled to the first PFD, to determine a fine phase difference between the first clock signal and the second clock signal, the second PFD to generate a second output indicating the fine phase difference.

Abstract: According to one embodiment, a phase locked loop (PLL) circuit includes an application unit, a correlator, an integrator and a power supply noise canceller. The application unit applies the test signal to a power supply voltage. The correlator extracts a frequency error signal as a monitor signal and calculates a correlation value for the test signal and the monitor signal to generate a correlation signal. The integrator integrates the correlation signal to generate an integral signal. The power supply noise canceller provides a cancellation gain corresponding to the integral signal to the power supply voltage to which the test signal is applied, to generate a control signal.

Abstract: A system includes a managing terminal, a mobile device, and cameras. The mobile device sends, when it is near one of the cameras, positional information of the mobile device and a uniquely created identifier via a network to the managing terminal and displays information indicating the identifier in the form of a video image. The camera shoots the video image being displayed by the mobile device and including the information indicating the identifier to create a second video image including the information and sends the second video image via a network to the managing terminal. The managing terminal receives the second video image, extracts the identifier therefrom, and stores, if the identifier matches the identifier sent from the mobile device, the IP address assigned to the camera and the positional information with a correspondence established therebetween.

Abstract: A phase locked loop circuit (30, 100, 110) includes a controllable oscillator (42) for generating an output signal of desired frequency responsive to a control signal, a first phase detection circuit (32, 102, 112) for generating an output indicative of phase differential responsive to the output signal and a first edge of a reference signal and a second phase detection circuit (34, 104, 114) for generating an output indicative of phase differential responsive to the output signal and a second edge of a reference signal. The control signal to the controllable oscillator (42) is driven by the outputs of the first and second phase detections circuits.

Abstract: A clock and data recovery circuit with built in jitter tolerance test is disclosed. Imposing jitter on a filter inside a CDR loop to cause phase disturbances to the clock and data recovery circuit, thereby to test the jitter tolerance of the clock and data recovery circuit. Accordingly, IC test cost is significantly reduced by increasing few circuit sizes.

Abstract: A phased lock loop (PLL) including a retimer unit, rotator unit, and clock selection unit. The retimer unit is configured for sampling a divided clock generated by a divide-by-N unit with a plurality of phases of an oscillator clock generated by a ring oscillator to generate a plurality of phase shifted divide-by-N clocks. The rotator unit is configured for selectively rotating through the plurality of phase shifted divide-by-N clocks based on a constant phase shift interval, wherein the rotator unit controls a clock selection unit to produce a single output phase selected from a plurality of generated divide-by-N clock phases.

Abstract: A communications device is disclosed that implements a phase-locked-loop to multiply a clock signal provided to a power management unit (PMU) by a variable integer value. Multiplying the PMU clock signal provides a second clock signal where the second clock signal is characterized by a fundamental component with one or more harmonics of the fundamental component that differ from the fundamental component and the one or more harmonics of the PMU clock signal. The fundamental component with one or more harmonics of the second clock signal does not occupy the same communication channel as the transmission communication signal of the communications device. Thus, minimizing the degradation of the transmission communication signal.

Abstract: A circuit for controlling a mixed mode controlled oscillator. The circuit comprises a charge pump, and a digital loop filter. The charge pump is coupled to the mixed mode controlled oscillator. The charge pump receives an up/down signal and sends a current signal to the mixed mode controlled oscillator. The digital loop filter receives the up/down signal and generates a digital code signal to the mixed mode controlled oscillator. An output frequency of the mixed mode controlled oscillator is controlled by the current signal and the digital code signal.

Abstract: A frequency modulator includes a digitally-controlled oscillator (DCO) arranged for producing a frequency deviation in response to a modulation tuning word and a phase-locked loop (PLL) tuning word. In addition, another frequency modulator includes a DCO and a DCO interface circuit. The DCO is arranged for producing a frequency deviation in response to an integer tuning word and a fractional tuning word. The DCO interface circuit is arranged for generating the integer tuning word and the fractional tuning word to the DCO, wherein the fractional tuning word is obtained through asynchronous sampling of a fixed-point tuning word.

Abstract: A phase locked loop includes a phase difference detector configured to receive a reference frequency and a divider frequency and output a phase difference signal. The phase locked loop includes a code generator configured to receive the reference frequency and the phase difference signal, and output a coarse tuning signal and a reset signal. The phase locked loop includes a digital loop filter configured to receive the phase difference signal and output a fine tuning signal. The phase locked loop includes a voltage control oscillator configured to receive the coarse and fine tuning signals, and output an output frequency. The phase locked loop includes a divider configured to receive the reset signal, a divider number control signal and the output frequency, and output the divider frequency. The phase locked loop includes a delta-sigma modulator configured to receive a divisor ratio and the reset signal, and output divider number control signal.

Abstract: A method and apparatus are described for regenerating a local clock within a wireless module and synchronizing the local clock with a wireless host clock. For one embodiment, the wireless module generates a local clock, counts the cycles of the clock during a common timing reference period maintained wirelessly between the wireless module and the host, receives a count of the host clock during the same common timing reference period, and adjusts the local clock signal based upon a comparison of the two counts. For one embodiment, the wireless module further receives timing references from the host and, in addition, receives packets of audio samples from the host accompanied by a timestamp, the timestamp based upon the host timing reference, and outputs the audio sample at the time designated by the timestamp.

Abstract: A frequency modulating path for generating a frequency modulated clock includes a direct feed input arranged for directly modulating frequency of an oscillator, and a compensating feed input arranged for compensating effects of frequency modulating on a phase error; wherein the compensating feed input is resampled by a down-divided clock that is an integer edge division of the oscillator. A reference phase generator for generating a reference phase output includes a resampling circuit, an accumulator and a sampler. The resampling circuit is for resampling a modulating frequency command word (FCW) input to produce a plurality of samples. The accumulator is for accumulating the samples to generate an accumulated result. The sampler is for sampling the accumulated result according to a frequency reference clock, and accordingly generating a sampled result, wherein the reference phase output is updated according to at least the sampled result.

Abstract: In accordance with an embodiment of the disclosure, systems and methods are provided for aligning signals in a timing recovery system. In certain implementations, a coarse phase error indicative of a phase offset between a reference signal and a signal is identified. The signal is transformed based at least in part on the coarse phase error, and operation of a phase-locked loop is initiated based at least in part on the coarse phase error.

Abstract: A timing jitter measurement circuit for measuring timing jitter in the digital domain may use an interpolator bank to over-sample a signal from a media reader, a zero crossing estimator to estimate a zero crossing moment in the output of the interpolator bank and a time interval analyzer (TIA) to calculate the timing jitter as the deviation of the estimated zero crossing moment from an expected zero crossing moment in a clock signal. The timing jitter measurement circuit may be integrated into digital circuitry since it avoids using analog devices. Consequently, it may simplify the chip design, lower power consumption and save space.

Abstract: Apparatuses and methods for phase aligning at least two clocks used by respective first and second circuitry systems, such as a memory controller and a DDR PHY interface in a system on a chip system. A first circuit samples a phase of a first clock used by the first circuitry system, and then a delay circuit selectively delays a second clock used by the second circuitry system and sets a delayed timing of the second clock. To economize resources and reduce chip area, a logic circuit receives the sampled phase of the first clock, determines which delayed timing matches timing of the sampled phase, and sets the delay circuit to a fixed delayed timing corresponding to the delayed timing that matches the sampled phase. Thus, phase alignment of the two clocks is achieved with fewer resources.

Abstract: A circuit, use, and method for controlling a receiver circuit is provided, wherein a complex baseband signal is generated from a received signal, a phase difference between a phase of the complex baseband signal and a phase precalculated from previous sampled values is determined, the phase difference is compared with a first threshold, a number is determined by counting the exceedances of the first threshold by the phase difference, a number of the counted exceedances is compared with a second threshold, and the receiver circuit is turned off if the number of counted exceedances exceeds the second threshold within a time period.

Abstract: A ring oscillator in a receiver in a multimedia network is adjusted to compensate for factors that may decrease its accuracy over time using a link training signal from a transmitter device in the network. An incoming signal having a known frequency is received at a receiver or sink device from a transmitter, the signal may be a link training signal used for configuring a link between the two devices. In the receiver, an internally generated clock signal is created, the signal having an internal frequency. The incoming signal and the internally generated clock signal are input into a frequency detector which outputs frequency comparison-based data. The internal frequency is based on the comparison-based data such that it is adjusted to be closer to the known frequency of the incoming signal.

Abstract: Exemplary embodiments of the present invention relate to a clock and data recovery (CDR) apparatus with adaptive optimum CDR bandwidth estimation by using a Kalman gain extractor. The Kalman gain extractor includes an off chip digital processor which receives a phase update information from the CDR outputs an estimated optimum Kalman gain obtained by extracting the standard deviation of step sizes of the accumulation jitter from the power spectral density (PSD) of the phase update information, and a on chip digital loop filter consists of a cyclic accumulator which accumulates the phase detector's output, a gain multiplier and a phase interpolator (or DCO) controller. The off chip digital processor includes a storage register, a fast Fourier transform (FFT) processor and an optimum Kalman gain estimator. The storage register stores the phase update information, from which the FFT processor extracts the PSD of the absolute input jitter.

Abstract: A transceiver includes a phase lock loop (PLL) and a clock data recovery circuit (CDR). The phase lock loop generates a first level control signal. The clock data recovery circuit, coupled to the phase lock loop, locks an incoming data signal to generate a data recovery clock according to a second level control signal. Wherein the clock data recovery circuit receives the first level control signal to further control a frequency range of the data recovery clock.

Abstract: A circuit includes phase detection, frequency adjustment, sampler, and control circuits. The phase detection circuit compares phases of first and second periodic signals to generate a control signal. The frequency adjustment circuit adjusts a frequency of the second periodic signal and a frequency of a third periodic signal based on the control signal. The sampler circuit samples a data signal to generate a sampled data signal in response to the third periodic signal. The control circuit adjusts the frequency of the third periodic signal based on the data signal changing from a first data rate to a second data rate while maintaining the frequency of the second periodic signal constant. The control circuit adjusts the frequency of the second periodic signal and the frequency of the third periodic signal based on the data signal changing from the second data rate to a third data rate.

Abstract: A one-wire communication bus for transferring a sequence of digital data from a transmitter to a receiver includes (a) an ECDD signal modulation circuit to create an electrical pulse train wherein each pulse's edge is used as clock signal and each pulse's duty cycle is used to represent digital value of zero and one; (b) an ECDD signal demodulation circuit to receive the ECDD pulse train using a group of sampling cells and to decode the sampled results using a majority voting circuit; (c) an electrical connection between a transmitter wherein the ECDD signal modulation circuit resides and a receiver wherein the ECDD signal demodulation circuit resides. Said ECDD signal is sent from the transmitter to the receiver through the electrical connection. Methods of creating the ECDD pulse train in the transmitter and decoding the ECDD pulse train in the receiver are also disclosed.

Abstract: To reduce the influence of a spurious in a high-frequency signal processing device and a wireless communication system each provided with a digital type PLL circuit. In a digital type PLL circuit including a digital phase comparator unit, a digital low-pass filter, a digital control oscillator unit, and a multi-module driver unit (frequency divider unit), the clock frequency of a clock signal in the digital phase comparator unit is configured selectably among a plurality of options. The clock frequency is selected among frequencies which are integer multiples of a reference frequency, in accordance with which frequency band of a standard is to be set for an oscillation output signal of the digital control oscillator unit.

Abstract: A semiconductor device comprises sampling logic, comprising: input sample path selection logic arranged to enable at least one input sample path; sampler logic arranged to receive and sample an input data signal in a serial data stream in accordance with a phase of the at least one enabled input sample path; and transition detection logic arranged to detect transitions within the received input data signal. The input sample path selection logic is further arranged, upon detection of a transition within the received input data signal, to determine if the phase of the at least one input sample path is a phase having a largest window between logic values; and if it is determined that the phase of the at least one input sample path is not the phase having a largest window between logic values, to enable at least one input sample path comprising a more appropriate phase.

Abstract: When receiving data in a unit of frame, each frame including a plurality of bits, based on a spread clock signal, a receiving time per bit of receiving data is calculated based on a receiving rate, and the change cycle of the spread clock signal is adjusted according to the receiving time per bit.

Abstract: A circuit for producing one of a plurality of output clock frequencies from a single, constant input reference clock frequency. The circuit comprises a reference clock system and a phase lock loop. The reference clock system includes a bypass path, a divider path including a first integer divider, and a multiplexer. A divisor of the first integer divider is based on a selected communications protocol of a group of possible communications protocols. The multiplexer is configured to route the bypass path or the divider path based on the selected communications protocol. The phase lock loop includes a voltage controlled oscillator and a feedback path. The feedback path includes a second integer divider. A divisor of the second integer divider is based on the selected communications protocol. The reference clock system is configured to receive a constant reference clock frequency.

Abstract: A frequency calibration method for a programmable oscillator includes the steps of: counting an oversampling number of an oversampling signal and estimating an accumulated bit number of a USB data stream according to the oversampling signal; calculating a difference between the oversampling number and M times of the accumulated bit number when the accumulated bit number is larger than a predetermined value; and determining a frequency calibration step of the oversampling signal according to the difference. The present invention further provides a frequency calibration device for a programmable oscillator.

Abstract: There is provided a solution for simultaneous reception of dual channel transmission. The solution is based on applying a first and a second oscillating signals, mixing and adding in order to separate the in-phase and quadrature components of first and second signals from a combined radio frequency signal received as input.

Abstract: A clock recovery circuit includes a first phase detector for measuring the phase difference between a first clock signal from a voltage controlled oscillator (VCO) and a data signal. A phase shifter responsive to a control signal based on this phase difference adjusts the phase of an incoming clock signal to yield a second clock signal. The phase difference between the first clock signal and the second clock signal is measured and the resulting signal is low-pass filtered to derive a control signal for controlling the VCO. The phase locked loop including the VCO filters out jitter.

Abstract: A method and apparatus for non-linear frequency control tracking of a control loop of a voltage controlled oscillator (VCO) in a wireless mobile device receiver is provided. A channel metric based on one or more channel quality indicators associated with a received radio frequency channel is determined and a state metric associated with the current operating state of the control loop are determined. One or more state metric threshold value associated with the determined channel metric, providing hysteresis between operating states, are determined wherein each state metric threshold value is associated with a transition to a possible operating state of the control loop. The control loop transitions from the current operating state to the operating state associated with an exceeded state metric threshold value. Coefficients are provided to an adaptive loop filter of the control loop, wherein the coefficients are associated with the transitioned operating state.

Abstract: A clock data recovery circuit (CDR) extracts bit data values from a serial bit stream without reference to a transmitter clock. A controllable oscillator produces a regenerated clock signal controlled to match the frequency and phase of transitions between bits and the serial data is sampled at an optimal phase. A phase detector generates early-or-late indication bits for clock versus data transition times, which are accumulated and applied to a second order feedback control with two distinct feedback paths for frequency and phase, combined for correcting the controllable oscillator, selecting a sub-phase and/or determining an optimal phase at which the bit stream data values are sampled. The second order filter is operated at distinct rates such that the phase correction has a latency as short as one clock cycle and the frequency correction latency occurs over plural cycles.

Abstract: The invention generally relates to phase locked loops (PLL), and more specifically to ultra-low bandwidth phase locked loops. The invention may be for example embodied in an integrated circuit implementing a phase locked loop or a method for operating a phase locked loop. The invention provides a PLL with a control stage that uses only two storage cells, a counter and a digital-to-analog (DAC) converter. In comparison to prior-art PLLs using storage cells the configuration of the invention's control stage reduces the chip area required for the PLL reduced. The invention further suggests PVT compensation mechanisms for a PLL and implementing a PLL that has lower peaking in its frequency response, which results in better settling response.

Abstract: An oscillation device includes a voltage control oscillation unit, a dividing unit, an output phase comparison unit, and a control voltage supply unit. The voltage control oscillation unit is configured to oscillate an oscillation frequency signal with a frequency f1 according to a control voltage. The dividing unit is configured to divide the frequency of the oscillation frequency signal into 1/N (N is a natural number) to match with a frequency f2 of a reference frequency signal input from outside. The output phase comparison unit is configured to compare a phase of the divided oscillation frequency signal with a phase of the reference frequency signal and output a signal according to a phase difference. The control voltage supply unit is configured to generate a control voltage according to the signal according to the phase difference and supply the control voltage to the voltage control oscillation unit.

Abstract: A system includes a memory controller and a plurality of semiconductor devices that are series-connected. Each of the devices has memory core for storing data. The memory controller provides a clock signal for synchronizing the operations of the devices. Each device includes a phase-locked loop (PLL) that is selectively enabled or disabled by a PLL enable signal. In each group, the PLLs of a selected number of devices are enabled by PLL enable signals and the other devices are disabled. The enabled PLL provides a plurality of reproduced clock signals with a phase shift of a multiple of 90° in response to an input clock signal. The data transfer is synchronized with at least one of the reproduced clock signals. In the devices of disabled PLLs, the data transfer is synchronized with the input clock signal. The enabled PLL and disabled PLL cause the devices to be the source and the common synchronous clocking, respectively. The devices can be grouped.

Abstract: A transponder unit for the contactless transmission of modulated data to a reader is provided. The transponder unit includes a clock generator configured to generate a clock signal and to synchronize the clock signal in a synchronization mode, on the basis of a signal received from the reader, and a modulator, the modulator configured to modulate data on the basis of the clock signal from the clock generator. The modulator is configured to generate a modulation pause by masking out at least one modulation component, the modulation component being smaller than a modulation pulse. The modulator is further configured to send the signal for starting the synchronization mode to the clock generator during this modulation pause.

Abstract: A signal generator for a transmitter or a receiver for transmitting or receiving RF-signals according to a given communication protocol includes an oscillator and a mismatch compensator. The oscillator is configured to provide a signal generator output signal having a signal generator output frequency and comprises a fine tuning circuit for providing a fine adjustment of the signal generator output frequency based on a fine tuning signal and a coarse tuning circuit for providing a course adjustment of the signal generator output frequency based on a coarse tuning signal.

Abstract: One bit is a smallest increment of binary measurement in first and second digital values. The first digital value is converted into a first analog signal. The second digital value is converted into a second analog signal. The first analog signal is augmented by a first amount that equates to less than the smallest increment of binary measurement, so that the augmented first analog signal by definition does not equal the second analog signal. The second analog signal is augmented by a second amount that equates to less than the smallest increment of binary measurement, so that the augmented second analog signal by definition does not equal the first analog signal. The augmented first analog signal is compared to the second analog signal, and a first signal is output in response thereto. The augmented second analog signal is compared to the first analog signal, and a second signal is output in response thereto.

Abstract: A digital fractional PLL introduces an accumulated phase offset before the digital VCO to achieve the fractional part of the division ratio. To provide this phase offset, the digital accumulator can integrate a fractional component ?n. By forcing ?n to zero, the PLL becomes an integer-N PLL. A de-skew timing configuration can be used to remove any time mismatch between integer and fractional counters of the PLL. A digital PLL can merge the function of frequency generation (DVCO) and that of fractional frequency counting into the same circuit block by reusing various phases of the frequency output to generate a fractional frequency count. A digital integer PLL can include a comparator, wherein the feedback loop of this PLL forces the phase difference between the reference clock and feedback signals to approach zero. By changing the duty cycle of feedback signal, the frequency tracking behavior of the loop can be varied.

Abstract: A wideband frequency synthesizer and a frequency synthesizing method thereof are provided. The wideband frequency synthesizer includes a phase-locked loop unit, a first voltage-controlled oscillating unit and a first frequency mixer unit. The phase-locked loop unit receives a reference signal and a feedback signal and generates a first oscillating signal according to the reference signal and the feedback signal. The first voltage-controlled oscillating unit generates a second oscillating signal. The first frequency mixer is coupled to the phase-locked loop unit and the first voltage-controlled oscillating unit, receives the first oscillating signal and the second oscillating signal for mixing frequencies of the first oscillating signal and the second oscillating signal to generate an output signal and taking the output signal as the feedback signal for outputting to the phase-locked loop unit.

Abstract: A frequency synthesizer for a WLAN transceiver is disclosed that may be used to generate 5.4 GHz and 2.4 GHz signals. The frequency synthesizer may be configured to minimize VCO pulling by using VCO operating frequencies that are not integer multiples of the RF bands. Further, the frequency synthesizer may be configured to minimize interference with other frequency bands used by existing wireless systems.

Abstract: Navigation satellite receivers have a large number of channels, where phase discriminators and loop filter of a PLL operate in phase, with data bits and control of numerically controlled oscillator (NCO) carried out simultaneously on all channels. Since symbol boundaries for different satellites do not match, there is a variable time delay between the generation of control signals and NCO control time. This delay may be measured by counting a number of samples in the delay interval. A proposed system measures non-energy parameters of the BPSK signal carrier received in additive mixture with noise when a digital loop filter of PLL controls NCO with a constant or changing in time delay. A control unit controls bandwidth and a LF order by changing transfer coefficients based on analyzing estimated signal parameters and phase tracking error at a PD output.

Abstract: An apparatus for measuring a high speed signal may comprise a plurality of Analog-Digital converters (AD converter) that are arranged in parallel to each other to sample an input signal at different frequencies; a plurality of frequency synthesizers configured to provide each AD converter with a different sampling frequency; a signal processor configured to receive an output of the plurality of AD converters to reconstruct the input signal; and/or a controller configured to receive and process a trigger signal.

Abstract: A clock a data recovery circuit (CDR) operates recovers data from a serial input signal. The CDR uses oversampling to sample the serial input signal at multiple phases. The multiple phases are generated from a reference clock that is not locked to the data rate of the serial input signal. A maximum of two phases are used at a time. The resulting CDR provides high performance while having low power consumption.

Abstract: A circuit may include a phase detector configured to generate a phase error signal based on a feedback signal and an oscillator configured to generate an output signal. The feedback signal may be based on the output signal. The circuit may also include a determination unit configured to measure a phase of the feedback signal based on the phase error signal when an output of the phase detector and an input of the oscillator are communicatively decoupled. The circuit may also include an adjustment unit configured to subtract the measured phase of the feedback signal from an intermediate signal upon which the output signal is based when the output of the phase detector and the input of the oscillator are communicatively coupled.