Abstract: An apparatus configured to: receive a digital input signal; receive a processing-direction-signal that can have a forward-value or a backward-value; and provide a digital output signal. The apparatus comprising a processor configured to apply an involutional cryptographic function to the digital input signal by: for a first operation: apply a first step of the involutional cryptographic function to the digital input signal in order to implement a forward calculation to move to the next step in the sequence; and perform a plurality of further operations until the forward calculation of a last step is performed. Each further operation comprises: if the processing-direction-signal has a forward-value: then perform the forward calculation for the current step; or if the processing-direction-signal has a backward-value: then perform a backward calculation for the current step.

Abstract: Techniques for scanning physical media on physical items and providing information about those physical items are provided. In one technique, based on a printed medium of a physical item, a mobile device generates digital scan data that reflects multiple individual items that are referenced on the printed medium. The mobile device sends, over a computer network, to a remote server, the digital scan data or data that identifies individual items. The remote server determines a toxicity metric for each individual item. The remote server generates, based solely on each toxicity metric, a safeness rating of the physical item. Rating data is generated based on the safeness rating and presented on a screen of the mobile device in association with data that identifies the physical item.

Abstract: Techniques for scanning physical media on physical items and providing information about those physical items are provided. In one technique, based on a printed medium of a physical item, a mobile device generates digital scan data that reflects multiple individual items that are referenced on the printed medium. The mobile device sends, over a computer network, to a remote server, the digital scan data or data that identifies individual items. The remote server determines a toxicity metric for each individual item. The remote server generates, based solely on each toxicity metric, a safeness rating of the physical item. Rating data is generated based on the safeness rating and presented on a screen of the mobile device in association with data that identifies the physical item.

Abstract: A disclosed gate driver includes a plurality of stages, a kth stage comprising: a first output node connected to an emission line; a second output node; a Q node connected to a first controller and a pull-down circuit; the pull-down circuit and a pull-up circuit respectively controlled by the Q node and the second output node; the first controller configured to receive a voltage of a first output node of a (k?1)th stage or a first start signal; a second controller configured to receive a voltage of a second output node of the (k?1)th stage or a second start signal; a third controller configured to control the voltage of the second output node; and a fourth controller configured to be controlled by the second output node and to control the voltage of the first output node, wherein ‘k’ is a natural number ?1.

Abstract: Provided are a gate drive unit, a gate drive circuit, a drive method and a display apparatus. The gate drive unit includes an input control module, an input module, a potential pull-down module, a first output module, a second output module, an isolation module, a first node and a second node, wherein the input control module controls operation of the input module under action of a second input signal and a first clock signal; the input module transmits a second clock signal to the second node under control of the input control module; the potential pull-down module pulls down a potential of the second node under action of a potential of the first node; the first output module outputs a first output signal under action of the potential of the first node, the potential of the second node and the first clock signal.

Abstract: A binary logic circuit for manipulating an input binary string includes a first stage of a first group of multiplexers arranged to select respective portions of an input binary string and configured to receive a respective first control. A second stage is included in which a plurality of a second group of multiplexers is arranged to select respective portions of the input binary string and configured to receive a respective second control signal. The control signals are provided such that each multiplexer of a second group is configured to select a respective second portion of the first binary string. Control circuitry is configured to generate the first and second control signals such that two or more of the first groups and/or two or more of the second groups of multiplexers are independently controllable.

Abstract: Provided are a display panel and display device. The display panel includes a display area and a non-display area. The display panel further includes multiple cascaded shift registers disposed in the non-display area and multiple scanning lines disposed in the display area. Each shift register is connected to a corresponding scanning line. The shift registers include multiple first shift registers and multiple second shift registers. The first shift registers are capable of unidirectional scanning, and the second shift registers are capable of bidirectional scanning. The display area includes a first display area and a second display area. Each of scanning lines in the first display area are connected to a respective one of the plurality of first shift registers, and each of the at least part of the scanning lines in the second display area are connected to the second shift registers.

Abstract: A shift register unit, a gate driving circuit and a display apparatus including the shift register unit and an abnormal situation processing method adaptable to the shift register unit. The shift register unit includes a pull-up node control circuit, an output circuit, a pull-down node control circuit and an anomaly control circuit. The anomaly control circuit is coupled to an anomaly indication signal terminal, an output terminal, a pull-up node and a pull-down node, and configured to allow the output terminal to output a high level and simultaneously to reset the pull-up node and the pull-down node under a control of an anomaly indication signal inputted by the anomaly indication signal terminal at an instant when an abnormal situation occurs.

Abstract: A scan driver includes a plurality of clock lines which receive clock signals in different phases, a plurality of stages connected with at least one of the plurality of clock lines, an initialization line which receives an initialization pulse, a first control transistor, which is connected between the initialization line and each of the plurality of clock lines, and which is turned on when the initialization pulse is supplied, and a second control transistor, which is connected between the initialization line and each of the plurality of stages, and which is turned on when the initialization pulse is supplied.

Abstract: The invention provides a GOA circuit for LTPS-TFT, by adding the twelfth and thirteenth TFTs (T12, T13) controlled by output ends (G(n?1), G(n+1)) of (n?1)-th and (n+1)-th GOA units, the drain of twelfth TFT T12 connected through the fourth node (W1(n)) to source of first TFT (T1), the drain of first TFT (T1) connected to output end of (n?1)-th GOA unit, the drain of thirteenth TFT (T13) connected through the fifth node W2(n) to source of third TFT (T3), the drain of third TFT (T3) connected to output end of (n+1)-th GOA unit; the first and third TFTs (T1, T3) controlled respectively by the forward and backward scan DC control signals (U2D, D2U) to reduce leakage of twelfth TFT (T12) in forward scanning and leakage of thirteenth TFT (T13) in backward scanning. As such, the leakage in key TFTs is reduced and GOA circuit stability is improved.

Abstract: The present application provides a shift register unit as well as a gate drive circuit and a display device using it. The shift register unit comprises an input module, an NAND gate module, an inverter module, a pull-up module and a pull-down module. The input module receives an input signal and a first clock signal, and transfers the input signal to a first input end of the NAND gate module and the pull-down module under the control of the first clock signal. A second input end of the NAND gate module receives a second clock signal input, and an output end thereof connects the inverter module. An output end of the inverter module connects the pull-up module. The pull-up module pulls up the output signal to a high level based on the output of the inverter module. The pull-down module pulls down the output signal to a low level under the control of the received input signal and the second clock signal.

Abstract: There is provided a method, apparatus and integrated circuit for measuring a signal, the apparatus comprising a plurality of sample stages arranged in series, each sample stage comprising a delay element, and a sample element, wherein an input of the sample element is coupled to an output of the delay element, and a strobe line for controlling a sample time of the sample elements, the strobe line comprising a plurality of strobe delay elements arranged in series, wherein an output of each strobe delay element is coupled to one or more sample elements.

Abstract: Provided are a shift register, a gate driver and a display device capable of eliminating voltage coupled noise at an output terminal. The shift register comprises a pulling-up unit, a clock control unit, a resetting unit, an inverting unit and a pulling-down unit; the pulling-up unit is connected with a shift trigging signal terminal, a high level signal terminal and the resetting unit; the clock control unit is connected with the pulling-up node, a clock signal terminal and the pulling-down unit; the resetting unit is connected with a reset signal terminal, a low level signal terminal, the pulling-up node and the output terminal; the inverting unit is connected with the high and low level signal terminals, the pulling-up node and the pulling-down unit; the pulling-down unit is connected with the pulling-up node, the pulling-down node, the low level signal terminal, the shift trigging signal terminal and the output terminal.

Abstract: A stage circuit and a scan driver, the stage circuit including a switch unit configured to selectively electrically couple a first node to one of a first input terminal and a second input terminal, a first driver coupled to the first node, to a second node, to a third node, to a first clock terminal, and to a second clock terminal, and a second driver coupled to the second node, to the third node, to a third clock terminal, and to a common terminal, and configured to output a scan signal to an output terminal.

Abstract: Disclosed herein is a bidirectional shift register which is capable of preventing multi-outputs from both end stages. The shift register includes a plurality of stages for outputting scan pulses forward or reversely based on a start pulse and a plurality of clock pulses with a phase difference. A last one of the stages includes a forward scan controller for making a set node active and a reset node inactive based on any one of the clock pulses and a scan pulse from an upstream stage, a reverse scan controller for making the set node active and the reset node inactive based on any one of the clock pulses and the start pulse, and an output unit for outputting any one of a corresponding scan pulse and a deactivation voltage based on a voltage at the set node, a voltage at the reset node and any one of the clock pulses.

Abstract: A gate driving circuit includes a first input terminal, a second input terminal, a third input terminal, an output terminal, a first transistor, a second transistor, a third transistor, and a capacitor. The first terminal of the first transistor is coupled to the first input terminal. The control terminal of the first transistor is coupled to the second input terminal. The first terminal of the second transistor is coupled to the third input terminal. The control terminal of the second transistor is coupled to the second terminal of the first transistor. The second terminal of the second transistor is coupled to the output terminal. The first terminal of the third transistor is coupled to the output terminal. The second terminal of the third transistor is coupled to ground terminal. The capacitor is coupled between the control terminal of the second transistor and the output terminal.

Abstract: Embodiments of the invention include a semiconductor structure containing a back end of line randomly patterned interconnect structure for implementing a physical unclonable function (PUF), a method for forming the semiconductor device, and a circuit for enabling the interconnect structure to implement the physical unclonable function. The method includes forming a semiconductor substrate and a dielectric layer on the substrate. The randomly patterned interconnect structure is formed in the dielectric layer. The random pattern of the interconnect structure is used to implement the physical unclonable function and is a result of defect occurrences during the manufacturing of the semiconductor structure. The circuit includes n-channel and p-channel metal oxide semiconductor field effect transistors (MOSFETs) and the randomly patterned interconnect structure, which acts as electrical connections between the MOSFETs.

Abstract: An LCD and a bidirectional shift register device thereof are provided. The bidirectional shift register device of the invention is disposed on the substrate of the panel and includes multi-stages shift registers in series connection. Each stage shift register includes a pre-charging unit, a pull-up unit and a pull-down unit, in which the pre-charging unit receives a first preset clock signal and the output from a (i?1)th stage shift register or a (i+1)th stage shift register so as to thereby output a charging signal. The pull-up unit receives the charging signal and a second preset clock signal so as to thereby output a scan signal. The pull-down unit receives the second preset clock signal, a third preset clock signal and the output from the (i+2)th stage shift register or the (i?2)th stage shift register so as to decide whether or not pulling down the scan signal to a reference level.

Abstract: A semiconductor device which shifts a low-level signal is provided. In an example, a first transistor including a first terminal electrically connected to a first wiring and a second terminal electrically connected to a second wiring, a second transistor including a first terminal electrically connected to a third wiring and a second terminal electrically connected to the second wiring, a third transistor including a first terminal electrically connected to a fourth wiring and a second terminal electrically connected to a gate of the second transistor, a fourth transistor including a first terminal electrically connected to a fifth wiring, a second terminal electrically connected to a gate of the third transistor, and a gate electrically connected to a sixth wiring, and a first switch including a first terminal electrically connected to the third wiring and a second terminal electrically connected to a gate of the first transistor are included.

Abstract: A display device including various portions, circuits and other arrangements for outputting various pulses and triggers, for controlling forward shift and backward shift operations.

Abstract: A display device includes a first-stage output circuit adapted to perform output to a first-stage output signal line as an endmost output signal line out of a plurality of output signal lines disposed in parallel to each other, and the first-stage output circuit includes a start signal line to which a start signal for applying a conducting potential sequentially to the plurality of output signal lines is applied, a first clock signal line to which a first clock signal is applied, a second clock signal line to which a second clock signal is applied, a first transistor having a source to which the first-stage output signal line is connected, and a drain to which the first clock signal line is connected, and a second transistor having a gate to which the start signal line is connected.

Abstract: Disclosed herein is a shift register in which leakage of charges from a voltage at a set node is prevented to stabilize an output from a stage. The shift register includes a plurality of stages for sequentially outputting scan pulses. Each stage includes a node controller for controlling signal states of a set node and a reset node, and an output unit supplied with any one of a plurality of clock pulses having different phases. The output unit outputs the supplied clock pulse as a scan pulse through an output terminal thereof according to the signal states of the set node and reset node. The node controller includes a first discharging switching device which is turned on or off in response to a scan pulse from a downstream stage. The first discharging switching device is connected between any one of a plurality of clock transfer lines and the set node.

Abstract: A shift register and driving method thereof, a gate driving apparatus and a display apparatus, the shift register comprises a pulling-up unit(21), a precharging and resetting unit(22), an output signal terminal at present stage(OUTPUT), a pulling-down unit(23), an input terminal connected to an output signal terminal of a shift register at previous stage(OUTF), an input terminal connected to an output signal terminal of a shift register at next stage(OUTL), and a scan control signal input terminal(INPUT), wherein: the precharging and resetting unit(22) precharges a gate of a first thin film transistor(T1) included in the pulling-up unit(21) and resets its potential; the pulling-down unit(23) pulls down a potential at the gate of the first thin film transistor(T1) and the output signal at present stage after the precharging and resetting unit(22) resets the potential at the gate of the first thin film transistor(T1), so that the pulling-up unit(21) is turned off and the output signal at present stage is at a l

Abstract: A shift register is disclosed, which can prevent malfunctioning of device by decreasing the load on a discharging voltage source line, and can decrease a size of stage. The shift register comprises a plurality of stages to sequentially output scan pulses through respective output terminals, wherein each of the stages comprises a pull-up switching unit controlled based on a signal state of node, and connected between the output terminal and any one among a plurality of clock transmission lines to transmit the clock pulses provided with sequential phase differences; and a node controller to control the signal state of node, and to discharge the node by using the clock pulse from any one among the plurality of clock transmission line.

Abstract: An object is to enhance the driving capability and improve the operating speed of a unit shift register applicable to a scanning line driving circuit having a partial display function. A unit shift register forming a gate line driving circuit includes a first transistor that supplies a first clock signal to a first output terminal, a second transistor that supplies a second clock signal to a second output terminal, a third transistor that charges the gate of the first transistor in response to activation of a shift signal of the previous stage, and a fourth transistor connected between the gate of the first transistor and the gate of the second transistor. The first clock signal and the second clock signal have the same phase, and only the second clock signal is activated in a particular period (a display ineffective period).

Abstract: A shift register is provided in which leakage of charges from a voltage at a set node is prevented to stabilize an output from a stage. The shift register includes stages for sequentially outputting scan pulses. An nth one of the stages includes a node controller for controlling voltages at nodes, and an output unit for outputting any one of a corresponding one of the scan pulses and a first discharging voltage according to the voltages at the nodes. The nodes include set and reset nodes. The node controller of the nth stage includes a first switching device controlled by a voltage supplied to the reset node for supplying a second discharging voltage to the set node, and an inverter circuit controlled by a voltage supplied to the set node for supplying any one of a charging voltage and a third discharging voltage to the reset node.

Abstract: Disclosed herein is a shift register which is capable of preventing leakage of charges at a set node which occurs when the duty ratio of a scan pulse is small, so as to normally output a scan pulse. The shift register includes a plurality of stages for sequentially generating outputs thereof. Each of the stages includes a carry output unit for outputting a carry pulse to drive at least one of a downstream stage and an upstream stage, and a scan output unit for outputting a scan pulse to drive a gate line. Each of the outputs generated from the stages includes the carry pulse and the scan pulse. The carry pulse and the scan pulse are paired to correspond to each other. The paired carry pulse and scan pulse have different durations.

Abstract: A touch device includes gate lines, pixels, sense control lines and sense units. Each pixel is connected to one of the gate lines and is decided whether to receive data according to a voltage on the gate line. Each the sense unit is connected to one of the sense control lines and is decided whether to perform a touch sense operation according to a voltage on the sense control line. The touch device further includes a shift register string including cascade-connected shift registers. Each shift register has first and second output terminals. The first output terminal provides an output to one of the gate lines according to a first clock signal to control the voltage on the gate line. The second output terminal provides an output to one of the sense control lines according to a second clock signal to control the voltage on the detection control line.

Abstract: A shift register, a bidirectional shift register apparatus and a liquid crystal display panel using the same are provided. The shift register includes a precharge unit, a pull up unit, and a pull down unit. The precharge unit receives outputs of a previous two-stage of shift register and a next two-stage of shift register both corresponding to the shift register to thereby generate a precharge signal. The pull up unit is coupled to the precharge unit, and receives the precharge signal and a first input clock signal to thereby output a scan signal. The pull down unit is coupled to the precharge unit and the pull up unit, and receives the precharge signal, the first input clock signal and a second input clock signal to control a voltage level of the scan signal, where the first input clock signal and the second input clock signal are inverted in phase.

Abstract: A shift register for providing a plurality of gate signals includes an Nth stage shift register unit and an (N+1)th stage shift register unit. The Nth stage shift register unit includes a first pull up unit, a first driving unit, a first control unit and a first auxiliary pull down unit. The (N+1)th stage shift register unit includes a second pull up unit, a second driving unit, a first pull down unit and a second auxiliary pull down unit. The first and second pull up units are both coupled to the first and second driving units for controlling the first and second driving units to generate gate signals. The first and second auxiliary pull down units are both coupled to the first control unit for pulling down the gate signals.

Abstract: A bidirectional shift register outputs pulses from a plurality of cascaded unit register circuits in a shift order which is one of a forward direction and a reverse direction. A ?th stage of unit register circuit (38) has two set terminals connected to respective outputs of (??1)th and (?+1)th stages and two reset terminals connected to respective outputs of (?+2)th and (??2)th stages. The unit register circuit (38) sets, when a pulse is input to any one of the set terminals, a reference point N1 to an H level, and, when a pulse is input to any one of the reset terminals, N1 to an L level. The order of phase change of clock signals is reversed according to the direction of a shift, and whether a start trigger signal is applied to a top stage or a bottom stage is switched.

Abstract: A gate driver is provided with an odd-numbered stage shift register, an even-numbered stage shift register, and main lines including clock signal main lines. In at least one example embodiment, each stage of one of the shift registers receives the first clock and the second clock from the clock signal main lines, and the third clock and the fourth clock from an adjacently provided stage of the other shift register. Each stage of the shift register can receive the second clock from a different stage of the same shift register. With this, it is possible to reduce a picture-frame area of a panel in a display device provided with a scanning signal line drive circuit having the plurality of shift registers.

Abstract: A plurality of cascaded unit register circuits which comprises a bidirectional shift register include main stages and dummy stages at the top before the main stages and dummy stages at the bottom after the main stages. A k-th stage outputs a pulse Pk in synchronization with a clock signal with a reference point N1 being at H level. The main stages include terminals NSF and NSB for setting N1 to H to which Pk?1 and Pk+1 are input, respectively, and terminals NRB and NRF for setting N1 to L level to which Pk?2 and Pk+2 are input, respectively. The order of generation of clock signals is reversed according to the direction of a shift, and whether a start trigger signal is applied to a top stage or a bottom stage is switched. Top dummy stages do not have NRB. Bottom dummy stages do not have NRF.

Abstract: Disclosed herein is a bidirectional shift register which is capable of preventing multi-outputs from both end stages. The shift register includes a plurality of stages for outputting scan pulses forward or reversely based on a start pulse and a plurality of clock pulses with a phase difference. A last one of the stages includes a forward scan controller for making a set node active and a reset node inactive based on any one of the clock pulses and a scan pulse from an upstream stage, a reverse scan controller for making the set node active and the reset node inactive based on any one of the clock pulses and the start pulse, and an output unit for outputting any one of a corresponding scan pulse and a deactivation voltage based on a voltage at the set node, a voltage at the reset node and any one of the clock pulses.

Abstract: Disclosed are a shift register that shows excellent operation reliability with elements less than those of the conventional structure and a gate driving circuit using the shift register. The gate driving circuit comprises each of a plurality of shift registers sequentially connected and respectively supplying scan signals to a plurality of gate lines of a display device.

Abstract: Disclosed herein is a shift register in which leakage of charges from a voltage at a set node is prevented to stabilize an output from a stage. The shift register includes a plurality of stages for sequentially outputting scan pulses. Each stage includes a node controller for controlling signal states of a set node and a reset node, and an output unit supplied with any one of a plurality of clock pulses having different phases. The output unit outputs the supplied clock pulse as a scan pulse through an output terminal thereof according to the signal states of the set node and reset node. The node controller includes a first discharging switching device which is turned on or off in response to a scan pulse from a downstream stage. The first discharging switching device is connected between any one of a plurality of clock transfer lines and the set node.

Abstract: An object is to provide a semiconductor device which can suppress characteristic deterioration in each transistor without destabilizing operation. In a non-selection period, a transistor is turned on at regular intervals, so that a power supply potential is supplied to an output terminal of a shift register circuit. A power supply potential is supplied to the output terminal of the shift register circuit through the transistor. Since the transistor is not always on in a non-selection period, a shift of the threshold voltage of the transistor is suppressed. In addition, a power supply potential is supplied to the output terminal of the shift register circuit through the transistor at regular intervals. Therefore, the shift register circuit can suppress noise which is generated in the output terminal.

Abstract: The present invention provides a shift register unit, a gate driving device and a liquid crystal display, wherein the shift register unit includes a first thin film transistor, a second thin film transistor, a third thin film transistor and a fourth thin film transistor, and further includes a pull-down unit and a driving unit. Since the shift register unit includes the pull-down unit and the driving unit, it is possible to assure that the output gate driving signal keeps at a low level stably when the shift register unit needs to output a low level, and the pull-down unit operates under the driving of an alternating current signal, which can prevent the threshold voltage of the thin film transistor of the pull-down unit from offsetting largely.

Abstract: A driving circuit includes a plurality of stages driven in response to a start signal. Each normal stage outputs a gate signal and a carry signal, increases an electric potential of a node in response to a previous carry signal of a previous stage, and decreases the gate signal to a first voltage in response to a carry signal from a next stage. Each stage applies a second voltage lower than the first voltage to the node in response to receipt of a carry signal from a second next stage. A first dummy stage outputs a first dummy carry signal to the last two normal stages in response to a last carry signal from the last normal stage and the start signal, and a second dummy stage outputs a second dummy carry signal to the last normal stage in response to the first dummy carry signal and the start signal.

Abstract: Disclosed is a gate shift register, which can perform a bi-directional shift operation with a reduced number of switching devices. The gate shift register includes a plurality of stages to receive a plurality of gate shift clocks and sequentially output a scan pulse. A kth stage includes a scan direction controller including first and second forward TFTs and first and second reverse TFTs to convert a scan direction in response to carry signals of previous stages input through first and second input terminals and carry signals of next stages input through third and fourth input terminals, a node controller including first to eighteenth TFTs to control charging and discharge operations of Q1, Q2, QB1 and QB2 nodes, and an output unit including first and second pull-up TFTs and first to fourth pull-down TFTs to output two scan pulses based on voltage levels of the Q1, Q2, QB1 and QB2 nodes.

Abstract: Disclosed herein is a bidirectional shift register which is capable of preventing multi-outputs from both end stages. The shift register includes a plurality of stages for outputting scan pulses forward or reversely based on a start pulse and a plurality of clock pulses with a phase difference. A last one of the stages includes a forward scan controller for making a set node active and a reset node inactive based on any one of the clock pulses and a scan pulse from an upstream stage, a reverse scan controller for making the set node active and the reset node inactive based on any one of the clock pulses and the start pulse, and an output unit for outputting any one of a corresponding scan pulse and a deactivation voltage based on a voltage at the set node, a voltage at the reset node and any one of the clock pulses.

Abstract: A circuit is constituted by a plurality of n-channel-type transistors, the circuit including: among the plurality of transistors, a transistor including a drain terminal for receiving a voltage of VDD, a source terminal, and a gate terminal for receiving an input signal; among the plurality of transistors, a transistor including a drain terminal for receiving the voltage of VDD, a source terminal connected to an output terminal, and a gate terminal connected to the source terminal of the transistor; and a capacitor provided between a node and a clock terminal for receiving a clock signal. In at least one embodiment, the clock signal inputted into the clock terminal has a frequency higher than that of an output signal outputted from the output terminal.

Abstract: An object is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. A pulse signal output circuit according to one embodiment of the disclosed invention includes first to tenth transistors. The ratio W/L of the channel width W to the channel length L of the first transistor and W/L of the third transistor are each larger than W/L of the sixth transistor. W/L of the fifth transistor is larger than W/L of the sixth transistor. W/L of the fifth transistor is equal to W/L of the seventh transistor. W/L of the third transistor is larger than W/L of the fourth transistor. With such a structure, a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit can be provided.

Abstract: A circuit which is constituted by a plurality of n-channel transistors includes, in at least one embodiment, a transistor (T1) which has a drain terminal to which an input signal is supplied and a source terminal from which a output signal is supplied; and a transistor (T2) which has a drain terminal to which a control signal is supplied and a source terminal connected to a gate terminal of the transistor (T1). A gate terminal of the transistor (T2) is connected to the source terminal of the transistor (T2). With the arrangement, it is possible to provide (i) a semiconductor device which is constituted by transistors having an identical conductivity type and which is capable of reducing an influence of noise, and (ii) a display device including the semiconductor device.

Abstract: A shift register is used for solving the problem that the shift register in the prior art can only perform a forward scanning driving but can not perform a bi-directional scanning driving. The shift register includes: a first TFT(T1), a second TFT(T2), a reset unit and a pulling-up unit. The present disclosure further provides a display including the shift register. The shift register and the display can achieve a bi-directional scanning driving.

Abstract: A bi-directional driving circuit of a liquid crystal display (LCD) panel is disclosed, in which forward scanning and backward scanning are available. In a bi-directional driving circuit of an LCD panel having a plurality of blocks, each block includes a first start pulse input terminal to which a start pulse or an output signal of a previous block is input and a second start pulse input terminal to which the start pulse or an output signal of a next block is input. Also, each block includes a first switching portion switching a start pulse signal applied to an input terminal of a first block among the blocks and switching an output signal of a previous block, which is applied to input terminals of the other blocks and a second switching portion switching a start pulse signal applied to an input terminal of the last block and switching an output signal of a previous block, which is applied to input terminals of the other blocks.

Abstract: An LCD and a bidirectional shift register device thereof are provided. The bidirectional shift register device of the invention is disposed on the substrate of the panel and includes multi-stages shift registers in series connection. Each stage shift register includes a pre-charging unit, a pull-up unit and a pull-down unit, in which the pre-charging unit receives a first preset clock signal and the output from a (i?1)th stage shift register or a (i+1)th stage shift register so as to thereby output a charging signal. The pull-up unit receives the charging signal and a second preset clock signal so as to thereby output a scan signal. The pull-down unit receives the second preset clock signal, a third preset clock signal and the output from the (i+2)th stage shift register or the (i?2)th stage shift register so as to decide whether or not pulling down the scan signal to a reference level.

Abstract: Disclosed is a display apparatus including two scanning circuits of the same configuration and layout, arranged on either sides of the display part. As long as one of the scanning circuits is in operation, the other scanning circuit is in a state in which no output signal is output.

Abstract: An n-th stage (wherein, n is an integer) of the stages of a gate driving circuit includes a pull-up part, a first variable mode part and a second variable mode part. At least one of the first and second variable mode parts includes a variable element. The variable element comprises a first thin-film transistor (TFT) turned on in response to a first level voltage of the first or second direction signal, a second TFT applying the first or second direction signal to a control part of the pull-up part in response to an output signal of a previous stage or an output signal of a next stage, and a third TFT connected to the second TFT through the first TFT.

Abstract: An object is to provide a semiconductor device which can suppress characteristic deterioration in each transistor without destabilizing operation. In a non-selection period, a transistor is turned on at regular intervals, so that a power supply potential is supplied to an output terminal of a shift register circuit. A power supply potential is supplied to the output terminal of the shift register circuit through the transistor. Since the transistor is not always on in a non-selection period, a shift of the threshold voltage of the transistor is suppressed. In addition, a power supply potential is supplied to the output terminal of the shift register circuit through the transistor at regular intervals. Therefore, the shift register circuit can suppress noise which is generated in the output terminal.