Abstract: A bi-directional shift register circuit comprising, a plurality of shift register stages, each having an input and an output terminal, and a bi-directional shift controller circuit associated with each of said shift register stages is disclosed. The bi-directional shift controller circuit comprises a first input connected to a output terminal of a first shift register stage and a second input connected to a output terminal of a second shift register stage. Means to apply a first and a second control voltage, wherein said first and second control voltage are different, and a combinatorial circuit responsive to said first and second control voltages to apply an indication of an input received from either said first shift register or said second shift register to said corresponding shift register input terminal. The combinatorial circuit configuration is that of a NOR gate or a NAND gate.

Abstract: A shift register includes bidirectional register units, a direction switching section, a register unit selecting section, and a shift clock supply section. The bidirectional register units are cascaded through first input/output terminals for data shifting and perform data shifting operation. The bidirectional register units have second input/output terminals which separately and directly input/output data. The direction switching section switches the shifting directions of the bidirectional register units. The register unit selecting section selects one of the bidirectional register units and inputs/outputs data through the second input/output terminal. The shift clock supply section supplies shift clocks to the bidirectional register units ranging from the bidirectional register unit selected by the register unit selecting section to the last-stage bidirectional register unit.

Abstract: A shift register device includes transistor pass gates and latches connected in series and disposed along a data bit line, each latch connected to a corresponding transistor pass gate. Each transistor pass gate is controlled by a separate control signal input line that a provides a signal to the transistor pass gate connected to it. The signals are provided in a staggered time pattern beginning with a latch disposed last in succession, shifting data from one position to the next succeeding position. Each latch is capable of storing one bit of data. The shift register utilizes less silicon space while reducing the amount of power consumed during operation.

Abstract: Systems and techniques are disclosed relating to shifting a plurality of input data bits to the left or right by a number of bit positions as a function of a binary value of a plurality of shift control bits. A first shifter element may be configured to perform one of two shifting operations on the input data bits to produce a plurality of first output bits, a first one of the shift control bits being used to select the shifting operation performed by the first shifter element. A second shifter element may be configured to perform at least one shifting operation on the first output bits to produce a plurality of second output bits, each of said at least one shifting operation being selectable from two shifting operations, a different one of the shift control bits being used to select each of said at least one shifting operation performed by the second shifter element.

Abstract: Delay lock loop (DLL) circuits, systems, and methods providing glitch-free output clock signals. Glitches are eliminated from an output clock signal by using shift registers including a single token bit to select one of many delayed clock signals. A DLL clock multiplexer includes a series of shift registers, each of which selects only one of the many input clock signals at each stage. Thus, only one clock signal is selected at any given time. Delay is added or subtracted from the loop by shifting the token bit within each shift register. The token bit is shifted by a single position at a time. Therefore, no glitching occurs.

Abstract: A shift-register circuit comprises an inverter and first to fourth transistors. The first transistor includes a gate coupled to an inverse clock signal, and a first source/drain coupled to a signal output from a previous-stage shift-register unit. The inverter includes a first input terminal coupled to the first source/drain of the first transistor. The second transistor includes a gate coupled to a second source/drain of the first transistor, a first source/drain coupled to a clock signal, and a second source/drain coupled to an output terminal. The third transistor includes a gate coupled to a first output terminal of the inverter, a first source/drain coupled to the output terminal, and a second source/drain coupled to a first voltage. The fourth transistor includes a gate coupled to a signal output from a next-stage shift-register unit, a first source/drain coupled to the output terminal, and a second source/drain coupled to the first voltage.

Abstract: A bi-directional shift-register circuit for outputting data in different turns and reducing the power loss according to a low-voltage clock signal, a first directional signal, and a second directional signal.

Abstract: A drive circuit, for example a gate line drive circuit for a TFT liquid-crystal display, having a circuit size smaller than in the past. A TFT drive circuit has the shifting direction of drive data sequentially shifted through shift registers (SR116-R60) and is further inverted by a control signal (SEL_SFT), and the data are shifted in the opposite direction, from the first shift register (SR61) to the second shift register (SR116). At this time, the upper group of switching circuits (SW1-SW56) or the lower group of switching circuits (SW116-SW61) is enabled and the other group is disabled by control signals (SEL_UP, SEL_LO). Once the drive data are shifted to the bits of the shift registers, a voltage selection signal generated by a decoder (DEn) is inputted to an output circuit via an effective switching circuit, and a drive signal for a TFT gate is outputted. The number of circuits is reduced because the shift registers (SR61-SR116) and decoders (DE61-DE116) are shared by two outputs.

Abstract: A bi-directional shift-register circuit for outputting data in different sequence. A first shift-register unit includes a first-stage control terminal and a first-stage output terminal outputs a first output signal. A second shift-register unit includes a second-stage input terminal coupled to the first-stage output terminal and a third-stage output terminal, a second-stage control terminal and a second-stage output terminal outputs a second output signal. The second-stage control terminal is selectively coupled to the first-stage output terminal and the third-stage output terminal and disables the second shift-register unit according to the first output signal or a third output signal. A third shift-register unit includes a third-stage control terminal and the third-stage output terminal outputs the third output signal.

Abstract: A bi-directional shift-register circuit for outputting data in different turns according to a switching signal. Each shift-register unit includes a first input terminal, a second input terminal, an output terminal and a clock input terminal for receiving the clock signal.

Abstract: A shift register with low power consumption has memory circuits 151-15N connected in series, gate circuits in memory circuits 152n−1 in the odd-numbered locations become conductive when clock signal CK is high, and gate circuits in memory circuits 152n in the even-numbered locations become conductive when clock signal CK is low, wherein data signals S input are latched for output when the gate circuits are shut off. The circuit configuration is simplified. The Shift register operates every one half of the cycle of clock signal CK, allowing the frequency of clock signal to be reduced by half, resulting in reduced power consumption.

Abstract: A code phase setting method in a PN coder which includes a shift register is provided. According to the method, an initial value is set in the shift register and a direction is selected among two directions in which direction a value in the shift register is shifted. Then, a code phase is set by shifting the initial value in the direction a necessary number of times.

Abstract: In a shift register having stages each formed from three to six NMOS transistors, a transistor, which outputs an output signal when an ON voltage is applied to the gate, outputs an output signal from the source. Simultaneously, the gate voltage is increased by the parasitic capacitance between the gate and source. For this reason, the voltage of the output signal rises, and the output signal output from each stage does not attenuate.

Abstract: An on-chip parallel/load, serial-shift shift register stores information bits for one or more chip parameters. The bits are represented by fuses that are connected to respective input terminals of the shift register. When the chip is not in test mode (TM), the fuses are electrically connected to respective cells of the shift register, and the output of the shift register is electrically isolated from an output buffer. When the chip is put into test mode, the electrical connections between the fuses and the shift register bits are broken, leaving the fuse information isolated in the shift register. The test mode also connects the output of the shift register to the output buffer and the output of the first shift register bit is seen on the output pin. The rest of the shift register information bits are serially shifted out of the shift register by toggling the CEB pin.

Abstract: Disclosed is a method and apparatus for shifting data from registers. Bits from N registers are shifted as input to a first set of M multiplexors. Control signals are sent into each of the first set of M multiplexors to select bits inputted from one of the registers. The selected bits are outputted to each of a second set of M multiplexors. Control signals are then sent into each of the second set of M multiplexors to select bits inputted from each of the first set of multiplexors.

Abstract: A bi-directional shift register comprises flip-flops connected to first switches and second switches. Third switches are connected in sequence and between the respective flip-flops. The third switches are on-off controlled in accordance with a CLK signal in order to periodically transition from low to high or from high to low. The shift register opens the second switches during the low duration of the REV signal and opens and closes the first switches in accordance with clocking of the CLK signal to shift data in the forward direction. The shift register opens the first switches during the high duration of the REV signal and opens and closes the second switches in accordance with the clocking of the CLK signal to shift data in the reverse direction.

Abstract: An apparatus for controlling audio signals having pulse code modulation (PCM) data and methods of operating the same result in efficient modulation of the audio signals. The apparatus for controlling audio signals comprises a PCM data input register configured to store the PCM data. A shift register is coupled to the PCM data input register configured to serially shift the PCM data. A PCM data output register is coupled to the shift register configured to store modified PCM data. An audio magnitude controller is coupled to the shift register configured to control serial shifting of the shift register to provide the modified PCM data.

Abstract: An apparatus that performs a left shift operation includes a shifter unit that contains the value to be shifted, a flag having an input coupled to the left-most bit of the shifter unit for receiving sign bit information for the value to be shifted, an overflow detector having inputs coupled to the shifter unit and the flag for determining the existence of an overflow condition, and a shift counter having outputs coupled to the shifter unit and the overflow detector.

Abstract: An active matrix drive type liquid crystal device is equipped with a data line driving circuit (101) composed of a bidirectional shift register which has an odd number of output stages and a scanning line driving circuit (104). composed of a bidirectional shift register which has an odd number of output stages so as to make it possible to horizontally and vertically invert the horizontal scanning direction and the vertical scanning direction easily by using a relatively simple constitution.

Abstract: A shift register that is suitable for reducing the required number of clock signals as well as simplifying the configuration of an external control circuit uses a plurality of stages connected, in series, to a start pulse input line. In each stage, an output circuit responds to a first control signal to apply any one of first and second clock signals to a row line of a liquid crystal cell array and thus to charge the low line of the liquid crystal cell array, and responds to a second control signal to discharge a voltage at the row line. An output circuit responds to a clock signal different from any one of the start pulse and an output signal of the previous stage to generate the first control signal, and responds to a clock signal different from the first control signal to generate the second control signal.

Abstract: A simplified bi-directional shift register and a single-latch circuit for implementing the bi-directional shift register thereof which obviates the use of a conventional dual-latch (i.e., master/slave) configuration in the bi-directional shift register design is described. The single-latch circuit includes an input circuit portion and a latching circuit portion. The input circuit portion receives input signals including the output data from previous and next single-latch circuits in the shift register and right shift and left shift control signals. Dependent on the input signals, the input circuit portion drives an input node coupled to the latching circuit portion with a data value to be shifted which corresponds to data from one of the previous and next single-latch circuits.

Abstract: The present invention provides for a circuit comprising: an input operable to receive a bit pattern; a shifter configured to selectively shift the bit pattern; a data output operable to output the bit pattern; and a sign extension operator coupled with the data output and operable to provide a sign extension signal thereto. The present invention additionally discloses a barrel shifter and a method for manipulating a bit pattern.

Abstract: A space-efficient, multi-cycle barrel shifter circuit for shifting data inputted into the circuit by a shift value over multiple clock cycles which circuit includes: (a) a load module adapted to receive a load signal and the data, the load module coupled to the shift module and configured to load the data into the shift module upon receipt of a load signal; (b) a register module coupled to the shift module and to the load module, where the register module is a register adapted to receive a clock signal and configured to pass the data through the shift module with each clock cycle; (c) a constant shift module coupled to the register module and the shift module and configured to shift the data by a constant amount with each clock cycle; and (d) a control module coupled to the shift module and the load module, the control module capable of generating a command signal for each elementary shifter in the shift module for each clock cycle based upon the shift value, the command signal determining the amount of shift

Abstract: The present invention provides an overflow detector for a FIFO. The FIFO includes a plurality of registers each having an input and an output, a plurality of write signals each respectively coupled to a clock, one of the plurality of registers, and a plurality of read switches each respectively coupled to an output of one of the plurality of registers, each of the plurality of read switches being controlled by a respective read signal. The overflow detector includes a plurality of clocked registers each of which is coupled to receive a write signal and its corresponding read signal, wherein each clocked register records a read signal and is clocked by the corresponding write signal.

Abstract: A circuit, which shifts an M-sequence code with an arbitrary number of bits, is realized by a small circuit scale. D-type flip-flops 1-6 form a shift register for generating an M-sequence and having outputs d0-d5 of respective stages, to which 25 bit shift inserting circuit 10 is connected in the manner of receiving the outputs d0-d5 as respective inputs and of outputting outputs O0-O5, to which 24 bit shift inserting circuit 11 is connected in the manner of receiving the outputs O0-O5 as respective inputs. In the same manner, a 23 bit shift inserting circuit 12, a 22 bit shift inserting circuit 13, a 21 bit shift inserting circuit 14, and a 20 bit shift inserting circuit 15 are sequentially connected with one another. Each of bit shift inserting circuits 10-15 respectively shifts a predetermined bit when control signals b5-b0 are “1”, and does not shift a bit when “0” so as to output an input as it is. Therefore, it is possible to obtain an arbitrary bit shift.

Abstract: A device for shifting data in a cascade multiplexer shifter allows the shifter to be used in a full-length mode or in a split mode where the shifter is divided into two equal halves with upper and lower half fields thereof respectively receiving individual data numbers. Each data number is thereafter simultaneously shifted right or shifted left a given shift amount to effect a dual right or dual left shift function.

Abstract: A programmable shift register in which the length (e.g., number of bits), number and location of taps, operating mode (i.e., counting up/down) and number of skip states are configured by programming selected memory cells. The programmable shift register includes a plurality of flip-flops, a programmable interconnect circuit, a next-state control circuit and a mode control circuit. The output terminal of each flip-flop drives a different bus line in the programmable interconnect circuit. Each bus line is programmably connected to a plurality of I/O lines via programmable interconnect points (PIPs). At least two of the second lines are connected to the input terminal of each flip-flop via portions (e.g., multiplexers) of the mode control circuit. Programming the PIPs to link selected flip-flop input and output terminals forms one or more shift registers of a selected length.

Abstract: The present invention provides for a circuit comprising: an input operable to receive a bit pattern; a bit-operator configured to selectively transpose the bit pattern; a shifter configured to shift the bit pattern following the transposition of the bit pattern; and the bit-operator being configured to transpose the bit pattern following the shift of the bit pattern. The present invention additionally provides a barrel shifter and a method for manipulating a bit pattern.

Abstract: In a milking parlor having a plurality of stalls for simultaneously milking a plurality of cows, and an identification station for identifying cows passing serially therethrough, an identification correction method compares produced milk weight values and expected milk weight values in a given milking, and performs a correction by shifting at least one or more of the expected milk weight values relative to the produced milk weight values by at least one stall number, to provide accurate cow identification when there is a misidentified or nonidentified cow, such as a cow having a missing identification tag.

Abstract: A system clock signal monitor that monitors a system clock signal by comparing a pulse width of a logic high pulse and a pulse width of a logic low pulse of each system clock duty cycle of the system clock signal to one or more reference clock duty cycles in order to detect any pulse width violations. For each system clock duty cycle, a pulse width violation is detected if the pulse width of a logic high pulse and/or the pulse width of a logic low pulse is equal to or greater than a maximum time interval for the logic high pulse and the logic low pulse. A pulse width violation may also occur if the pulse width of a logic high pulse and/or the pulse width of a logic low pulse is within a risk range (as defined by the system designer) of the maximum time interval for the logic high pulse and the logic low pulse. The system clock signal monitor can be further designed to warn/reset a processor or a user of the processor upon the detection of one or more detected occurrences of a pulse width violation.

Abstract: A bi-directional shift register for scanning a liquid crystal display includes cascaded stages. A given stage includes an output transistor having a clock signal coupled thereto. A first input section is responsive to an output pulse of a second stage for generating a control signal that is coupled to the transistor to condition the output transistor periodically for operation in a conduction state when shifting in a first direction is selected. The input section is responsive to an output pulse of a third stage for periodically conditioning the output transistor to operate in the conduction state, when shifting in the opposite direction is selected. When the clock signal occurs and the transistor is conditioned for the operation in the conduction state, an output pulse is generated at an output of the given stage.

Abstract: A high speed barrel shifter in which fill input data is especially added.

Abstract: A communications unit configured to be implemented in an ASIC environment utilizes only a small amount of chip surface area and requires a minimum number of pins. The unit operates asynchronously with respect to the ASIC internal clock so that communications can occur independent of such internal clock. In one embodiment the communications unit includes a controller coupled to a shift register via a data bus. Pin connections to the controller include a request line REQ, an input/output control line I/O (or INOUT), an acknowledgement line ACK, an external clock line EXTCLK, and a data line DATA. The shift register also is coupled, via a data bus, to a memory module, e.g., a RAM. An ASIC processor is coupled to the controller, shift register and memory module via control lines.

Abstract: A unified bi-directional LFSR is fabricated from latches having dual (Forward and Reverse) inputs. Each such latch accepts its inputs upon receipt of a clock signal that is respectively associated with the forward or reverse direction. The appropriate collection of XOR gates exists between latch outputs and the inputs associated with a forward clock signal, so as to produce the forward sequence. Likewise, another appropriate collection of XOR gates exists between the latch outputs and the inputs associated with the reverse clock signal. To produce a "reverse" LFSR corresponding to the polynomial that is the reciprocal of the polynomial for the "forward" LFSR, the latches of the reciprocal (reverse direction) LFSR are construed as being numbered in the opposite order. That is, a single set of latches (register) has both a forward linear feedback network and a reverse linear feedback network.

Abstract: A shift register has four systems of shift registers for bidirectional scans and normal/redundant lines. The respective systems of shift registers are divided into blocks, so that transmission circuits are provided therebetween. The transmission circuits form switching circuits through transfer gates. The transmission circuits receive output signals from both of the shift registers for the normal/redundant lines, and output only normal output signals to next stage shift registers in accordance with control signals.

Abstract: A high-speed rotator array for shifting input data a specified amount. The rotator array includes a plurality of straight shift control lines extending across the array for receiving shift data representative of shift values, and a plurality of input terminals for receiving input data to be shifted. The rotator array also includes a plurality of data lines coupled to the plurality of input terminals that extend both diagonally and horizontally across the array. In response to the rotator array receiving the shift data and the input data, a plurality of output terminals transmit the shifted output data.

Abstract: A shifting circuit operates on a plurality of input sub-words, that collectively constitute an input data word, to generate a plurality of result sub-words that collectively represent the input data word, shifted. The shifting circuit receives, during each cycle, a separate one of the plurality of input sub-words. A combiner/selector performs a shift on each sub-word provided on the I-bus, taking carry-in bits from a carry-in register. Before a shifting operation is executed, the carry-in register is initialized to zero. (Alternately, the carry-in register may be reset to zero after a shifting operation is executed.) The carry-in register is also connected to receive the sub-words provided by the data source circuit onto the I-bus.

Abstract: A data shift control circuit for a shift register in response to a logic operation command code is disclosed. The shift register includes a first register and a second register and the logic operation command code includes a first portion and a second portion. The circuit includes a first decoder for decoding the first portion to transmit a move signal; a second decoder for decoding the second portion to transmit a control signal; a control signal channel, electrically connected to the first register and the second register, for allowing the first register and the second register to receive the control signal and for allowing the shift register to execute a first action; and a move signal channel, electrically connected to all registers of the shift register for allowing the all registers to receive the move signal and for allowing the move register to execute a second action.

Abstract: The scale of a pseudo-random number generating circuit that can select normal or reverse order in which pseudo-random numbers are generated is reduced. The outputs of first and second NOR circuits are selected by a selecting circuit and sent to a parity check circuit. The output of the parity check circuit is directly sent to the right and left shift input terminals of a bidirectional shift register.

Abstract: A start signal is given to an SP.sub.-- I/O buffer through a terminal SP1, and its pulse width is controlled by an SP control circuit. A selection signal SEL is given to a selector circuit so that the data shift direction of a bidirectional shift register is switched. When the shift direction is directed to the other side, the start signal is supplied from a terminal SP2 through an SP.sub.-- I/O buffer. When the shift operation is to be done from the terminal SP1 to the terminal SP2, the output of the 38th stage which precedes the final stage, namely, the 40th stage, by two stages is derived from the terminal SP2 as an input start signal for the succeeding driver, during a time period which is longer than one cycle of a clock signal CLK. According to this configuration, a cascade connection can be realized easily and surely even when a clock signal of a higher frequency is used.

Abstract: A shift register is clocked by propagating two clock networks in opposite directions: one from input towards the output, the other from the output towards the input. The parasitic delays at the end of these networks are picked to be approximately equal. An extra latch is added to the shift register where the two clock networks meet to prevent a race condition. Both clock networks consist of non-overlapping clocks. Non-overlapping clock generator circuits are used to restore the non-overlap of the clocks when parasitic effects start to cause clock overlap as the clocks are propagated over long distances. An extra latch in the shift register at the non-overlapping clock generators prevents the delay of the non-overlapping clock generator from causing a race condition.

Abstract: An instruction flow control circuit controls the selection and execution of instruction signals in a microprocessor having multiple execution units that can execute plural instructions at one time. The instruction flow control circuit compares a number of signals indicating how many execution units are available with a number of signals indicating how many execution units are required. The circuit is a matrix of transmission gates which propagate signals through, or shift signals between, various signal paths for available resources, depending on the signals requesting the executing units. A number of output gates suppress the execution of instruction signals where an execution unit is requested but none are available.

Abstract: The present invention describes a circuit (10) and associated method of operation for implementing bit reversals and shifts of an input data. The circuit (10) includes a plurality of input lines (12), a plurality of output lines (14), a plurality of shifting transistors (16), a plurality of bit reversal transistors (20), control lines (18) and (22) for each, and a controller (24). The plurality of shifting transistors (16) operably couple the input lines (12) to the output lines (14) such that the controller (24) may selectively operate the shifting transistors (22) to produce shifted outputs of the input data D.sub.0 through D.sub.3 on the output lines (14). The controller (24) selectively operates the bit reversal transistors (20) to produce a bit reversed representation of the input data on the output lines (14). Precharge circuit (30) precharges the output lines (14) so that they may be statically driven. The circuit (10) may include multiplexors (25), (26), and (27) to enable arithmetic shifts.

Abstract: A method of eliminating signal contention during reconfiguration of a programmable logic device includes the steps of: arranging a plurality of memory cells in sets and selectively programing the memory cells one set at a time, either in a first direction or a second direction. A structure for providing that selective programming includes a plurality of synchronous flip-flops, and a plurality of associated two-input multiplexers. A control signal in a first logic state provided to the multiplexers provides a first signal propagation direction through the flip-flops, whereas the control signal in a second logic state provides a second signal propagation direction through the flip-flops.

Abstract: An array processing system has a plurality of processing elements, each of which includes a processor and an associated memory module, and a router network over which each processing element can transfer messages to other random processing elements. The system further includes a shift register which can shift data either toward a shift-in terminal, or toward a shift-out terminal, either one bit at a time or four bits at a time, thus improving processing system speed for floating point arithmetic operations.

Abstract: A driver circuit comprising an output level selection circuit and a shift register is disclosed. The output level selection circuit has driving terminals, potential level input terminals and data input terminals, and an output signal having one of the different potential levels from the driving terminals in response to the data signals. The shift register includes an input terminal, an output terminal, a control terminal, a control circuit, a first shift circuit, and a second shift circuit. The first shift circuit has an input coupled to the input terminal of the shift register and the control circuit, and an output coupled to the control circuit. The second shift circuit has an input coupled to the control circuit and an output coupled to the output terminal of the shift register.

Abstract: A bi-directional shift register capable of transferring bit data in either a forward or reverse direction. The shift register includes multiple transfer elements (e.g., flip-flop circuits) cascaded together which provide synchronous transfer of the bit data from one stage to an adjacent stage in either direction. The shift register further includes two switching circuits for electrically connecting an input terminal of one transfer element to an output terminal of the adjacent transfer element. The first switching circuit is enabled to cause the transfer of the bit data in the forward direction, and the second switching circuit is enabled to cause the transfer of the bit data in the reverse direction.

Abstract: A bit sequence reversing device for reversing a sequence of data having a plurality of blocks, each block having a predetermined number of bits. The bit sequence reversing device includes a block reversing unit for reversing a sequence of at least two of the blocks; and a plurality of bit reversing units, each corresponding to one of the blocks, each of the bit reversing units reversing a sequence of the bits in the corresponding block. The block reversing unit includes a barrel shift unit.

Abstract: A data link controller receiver is disclosed that includes a series of shift registers and a bit counter that counts the number of received bits. When an end of frame character is received, the value in the bit counter which represents the bit residue is supplied to a bit adjustment counter. The bit adjustment counter is employed to control the operation of the shift register containing the bit residue during a byte adjust operation, in a manner which enables the shift register containing the bit residue to be clocked until the value in the bit adjustment counter is indicative of the number of bits in a defined byte. Accordingly, the bit residue is serially shifted until the least significant bit of the shift register is filled. In addition, a mechanism is provided for loading zeros into the shift register during the byte adjust operation.

Abstract: A method of operating a timer mechanism in a digital data processing system is described in which the contents of at least one timer register is updated by a predetermined time increment during each of successive periodic update cycles. Each update cycle includes a predetermined number of operating cycles of the data processing system. During each update cycle, the contents of an adjustment register is circularly shifted by one bit position and if the bit value at a particular position in this adjustment register has a predetermined binary value during an update cycle, then actual updating of the timer register is omitted during a related update cycle.