Shift Direction Control Patents (Class 377/69)
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Patent number: 8614700Abstract: A voltage level shifter formed by single-typed transistors comprises two input terminals, two power supply terminals, a plurality of thin-film transistors, and an output terminal. Another voltage level shifter formed by single-typed transistors comprises two input terminals, an output terminal, two power supply terminals, two input units, a first thin-film transistor, a disable unit, a feedback unit, and a second thin-film transistor. The voltage level shifters are formed by single-typed TFTs. When integrating the voltage level shifters into a substrate of a TFT display, the manufacturing processes are simplified. Besides, power is saved.Type: GrantFiled: May 3, 2011Date of Patent: December 24, 2013Assignee: AU Optronics Corp.Inventor: Jian-Shen Yu
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Patent number: 8615066Abstract: An object is to enhance the driving capability and improve the operating speed of a unit shift register applicable to a scanning line driving circuit having a partial display function. A unit shift register forming a gate line driving circuit includes a first transistor that supplies a first clock signal to a first output terminal, a second transistor that supplies a second clock signal to a second output terminal, a third transistor that charges the gate of the first transistor in response to activation of a shift signal of the previous stage, and a fourth transistor connected between the gate of the first transistor and the gate of the second transistor. The first clock signal and the second clock signal have the same phase, and only the second clock signal is activated in a particular period (a display ineffective period).Type: GrantFiled: July 16, 2013Date of Patent: December 24, 2013Assignee: Mitsubishi Electric CorporationInventor: Youichi Tobita
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Patent number: 8594270Abstract: A display panel drive device includes: a ring counter circuit that includes a first ring counter having a plurality of flipflops connected in cascade, configured to operate in synchronization with a first clock signal with a first-stage one of the plurality of flipflops being set by an initial signal, and outputs signals using outputs of the plurality of flipflops; a shift register having a plurality of flipflops connected in cascade, configured to operate in synchronization with a second clock signal lower in frequency than the first clock signal with a first-stage one of the plurality of flipflops being set by the initial signal; and an output section configured to perform a logical operation between one of outputs of the ring counter circuit and one of outputs of the shift register, to generate a scanning line drive signal for a display panel.Type: GrantFiled: January 3, 2013Date of Patent: November 26, 2013Assignee: Panasonic CorporationInventors: Tetsu Nagano, Daijiro Arisawa, Kenichi Ishibashi, Yoshiteru Fujimoto
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Patent number: 8571169Abstract: Provided are a bi-directional scanning type gate line driving circuit that does not require a dummy unit shift register and a method of driving the same. In a gate line driving circuit including a multi-stage shift register capable of bi-directional shifting, a start pulse is input to a unit shift register at a first stage and a unit shift register at the last stage of the multi-stage shift register. In forward shifting, a clock signal supplied to the unit shift register at the last stage is kept at a deactivation level during a period from a time at which an activation period of an output signal of the unit shift register at the last stage ends to a time at which the start pulse is activated during a subsequent frame period.Type: GrantFiled: February 8, 2011Date of Patent: October 29, 2013Assignee: Mitsubishi Electric CorporationInventor: Youichi Tobita
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Patent number: 8571170Abstract: An object is to enhance the driving capability and improve the operating speed of a unit shift register applicable to a scanning line driving circuit having a partial display function. A unit shift register forming a gate line driving circuit includes a first transistor that supplies a first clock signal to a first output terminal, a second transistor that supplies a second clock signal to a second output terminal, a third transistor that charges the gate of the first transistor in response to activation of a shift signal of the previous stage, and a fourth transistor connected between the gate of the first transistor and the gate of the second transistor. The first clock signal and the second clock signal have the same phase, and only the second clock signal is activated in a particular period (a display ineffective period).Type: GrantFiled: December 18, 2012Date of Patent: October 29, 2013Assignee: Mitsubishi Electric CorporationInventor: Youichi Tobita
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Patent number: 8565370Abstract: A pull-up driving part maintains a signal of a first node at a high level by receiving a turn-on voltage in response to one of a previous stage or a vertical start signal. A pull-up part outputs a clock signal through an output terminal in response to the signal of the first node. A first holding part maintains a signal of a second node at a high level or a low level when the signal of the first node is respectively low or high. A second holding part maintains the signal of the first node and a signal of the output terminal at a ground voltage in response to the signal of the second node or a delayed and inverted clock signal.Type: GrantFiled: September 12, 2012Date of Patent: October 22, 2013Assignee: Samsung Display Co., Ltd.Inventors: Hong-Woo Lee, Sung-Man Kim, Jong-Hyuk Lee, Jong-Hwan Lee, Hyeon-Hwan Kim, Sang-Moon Moh, Jeong-Il Kim, Yeon-Kyu Moon
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Patent number: 8553830Abstract: A shift register is disclosed, which can prevent malfunctioning of device by decreasing the load on a discharging voltage source line, and can decrease a size of stage. The shift register comprises a plurality of stages to sequentially output scan pulses through respective output terminals, wherein each of the stages comprises a pull-up switching unit controlled based on a signal state of node, and connected between the output terminal and any one among a plurality of clock transmission lines to transmit the clock pulses provided with sequential phase differences; and a node controller to control the signal state of node, and to discharge the node by using the clock pulse from any one among the plurality of clock transmission line.Type: GrantFiled: August 21, 2012Date of Patent: October 8, 2013Assignee: LG Display Co., Ltd.Inventor: Yong Ho Jang
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Patent number: 8552961Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a driving unit, an input unit, a driving adjustment unit and a pull-down unit. The driving unit is utilized for outputting a gate signal according to a system clock and a driving control voltage. The input unit is put in use for outputting the driving control voltage according to an input control signal and a first input signal. The driving adjustment unit is employed for adjusting the driving control voltage according to a second input signal and a third input signal. The pull-down unit is used for pulling down the gate signal and the driving control voltage according to a fourth input signal.Type: GrantFiled: May 13, 2011Date of Patent: October 8, 2013Assignee: AU Optronics Corp.Inventors: Yu-Chung Yang, Yung-Chih Chen
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Patent number: 8526569Abstract: Discussed herein is a shift register which is capable of stabilizing an output thereof. The shift register includes a plurality of stages for sequentially outputting scan pulses in such a manner that high durations of the scan pulses partially overlap with each other. Each of the stages includes a node controller for controlling a charging duration of a set node, and an output unit for outputting a corresponding one of the scan pulses through an output terminal for the charging duration of the set node.Type: GrantFiled: December 27, 2011Date of Patent: September 3, 2013Assignee: LG Display Co., Ltd.Inventors: Yong-Ho Jang, Seung-Chan Choi
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Patent number: 8519935Abstract: A display device having bi-directional shift registers is disclosed. The display device includes a display panel, a first dummy shift register set, a second dummy shift register set, a third dummy shift register sets, a fourth dummy shift register sets, a first valid shift register set coupled between the first dummy shift register set and the second dummy shift register set, a second valid shift register set coupled between the third dummy shift register set and the fourth dummy shift register set, and a first directional circuit coupled to a first valid register in the first valid register set and the third dummy shift register set.Type: GrantFiled: March 17, 2011Date of Patent: August 27, 2013Assignee: AU Optronics Corp.Inventors: Yung-Chih Chen, Kuo-Chang Su, Chih-Ying Lin, Yu-Chung Yang
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Patent number: 8483350Abstract: A shift register includes a plurality of shift register units coupled in series. Each shift register unit, receiving an input voltage at an input end and an output voltage at an output end, includes a node, a pull-up driving circuit, a pull-up circuit and first through third pull-down circuits. The pull-up driving circuit can transmit the input voltage to the node, and the pull-up circuit can provide the output voltage based on a high-frequency clock signal and the input signal. The first pull-down circuit can provide a bias voltage at the node or at the output end based on a first low-frequency clock signal. The second pull-down circuit can provide a bias voltage at the node or at the output end based on a second low-frequency clock signal. The third pull-down circuit can provide a bias voltage at the node or at the output end based on a feedback voltage.Type: GrantFiled: November 15, 2012Date of Patent: July 9, 2013Assignee: AU Optronics Corp.Inventors: Tsung-Ting Tsai, Ming-Sheng Lai, Min-Feng Chiang, Chun-Hsin Liu
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Publication number: 20130148775Abstract: Disclosed is a gate shift register, which can perform a bi-directional shift operation with a reduced number of switching devices. The gate shift register includes a plurality of stages to receive a plurality of gate shift clocks and sequentially output a scan pulse. A kth stage includes a scan direction controller including first and second forward TFTs and first and second reverse TFTs to convert a scan direction in response to carry signals of previous stages input through first and second input terminals and carry signals of next stages input through third and fourth input terminals, a node controller including first to eighteenth TFTs to control charging and discharge operations of Q1, Q2, QB1 and QB2 nodes, and an output unit including first and second pull-up TFTs and first to fourth pull-down TFTs to output two scan pulses based on voltage levels of the Q1, Q2, QB1 and QB2 nodes.Type: ApplicationFiled: August 16, 2012Publication date: June 13, 2013Inventors: Hong-Jae Shin, Chung-Ah Lee
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Patent number: 8442183Abstract: An object is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. A pulse signal output circuit according to one embodiment of the disclosed invention includes first to tenth transistors. The ratio W/L of the channel width W to the channel length L of the first transistor and W/L of the third transistor are each larger than W/L of the sixth transistor. W/L of the fifth transistor is larger than W/L of the sixth transistor. W/L of the fifth transistor is equal to W/L of the seventh transistor. W/L of the third transistor is larger than W/L of the fourth transistor. With such a structure, a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit can be provided.Type: GrantFiled: February 28, 2011Date of Patent: May 14, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Seiko Amano, Kouhei Toyotaka, Hiroyuki Miyake, Aya Miyazaki, Hideaki Shishido, Koji Kusunoki
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Patent number: 8422621Abstract: A shift register is provided in which leakage of charges from a voltage at a set node is prevented to stabilize an output from a stage. The shift register includes stages for sequentially outputting scan pulses. An nth one of the stages includes a node controller for controlling voltages at nodes, and an output unit for outputting any one of a corresponding one of the scan pulses and a first discharging voltage according to the voltages at the nodes. The nodes include set and reset nodes. The node controller of the nth stage includes a first switching device controlled by a voltage supplied to the reset node for supplying a second discharging voltage to the set node, and an inverter circuit controlled by a voltage supplied to the set node for supplying any one of a charging voltage and a third discharging voltage to the reset node.Type: GrantFiled: December 28, 2011Date of Patent: April 16, 2013Assignee: LG Display Co., Ltd.Inventors: Yong-Ho Jang, Seung-Chan Choi, Jae-Yong You, Woo-Seok Choi
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Patent number: 8422622Abstract: To provide a shift register and a display device each capable of satisfactorily preventing noises of individual stage outputs without increasing circuit complexity, each stage of the shift register includes: a first output transistor; a first capacitor; an input gate; a first switching element; a second switching element; a third switching element; a fourth switching element; and a fifth switching element.Type: GrantFiled: February 24, 2010Date of Patent: April 16, 2013Assignee: Sharp Kabushiki KaishaInventors: Masahiko Nakamizo, Masashi Yonemaru, Yasuaki Iwase, Kenichi Ishii
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Publication number: 20130083885Abstract: Disclosed herein is a bidirectional shift register which is capable of preventing multi-outputs from both end stages. The shift register includes a plurality of stages for outputting scan pulses forward or reversely based on a start pulse and a plurality of clock pulses with a phase difference. A last one of the stages includes a forward scan controller for making a set node active and a reset node inactive based on any one of the clock pulses and a scan pulse from an upstream stage, a reverse scan controller for making the set node active and the reset node inactive based on any one of the clock pulses and the start pulse, and an output unit for outputting any one of a corresponding scan pulse and a deactivation voltage based on a voltage at the set node, a voltage at the reset node and any one of the clock pulses.Type: ApplicationFiled: September 28, 2012Publication date: April 4, 2013Applicant: LG DISPLAY CO., LTD.Inventor: LG Display Co., Ltd.
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Publication number: 20130077736Abstract: Disclosed are a shift register that shows excellent operation reliability with elements less than those of the conventional structure and a gate driving circuit using the shift register. The gate driving circuit comprises each of a plurality of shift registers sequentially connected and respectively supplying scan signals to a plurality of gate lines of a display device.Type: ApplicationFiled: August 29, 2012Publication date: March 28, 2013Applicant: HYDIS TECHNOLOGIES CO., LTD.Inventor: Ki Min Son
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Patent number: 8406372Abstract: A shift register of an LCD device includes a plurality of shift register units coupled in series. Each shift register unit includes an input circuit and a pull-down circuit having symmetric structures which enable the LCD device to function in a forward-scan mode and a reverse-scan mode.Type: GrantFiled: May 28, 2012Date of Patent: March 26, 2013Assignee: AU Optronics Corp.Inventors: Kuo-Hua Hsu, Kun-Yueh Lin, Yu-Chung Yang, Kuo-Chang Su
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Publication number: 20130069920Abstract: A signal output circuit of the present invention is provided in a unit stage of a shift register. The signal output circuit includes a set-reset flip-flop, and a signal generation circuit for generating an output signal by loading or blocking a clock signal in accordance with a signal inputted thereto. The signal output circuit is arranged such that: the signal generation circuit receives a signal outputted from the flip-flop and the output signal fed back to the signal generating circuit; and the output signal is fed back to a reset input of the flip-flop. This makes it possible to achieve a reduction in the area of the circuit and a simplification of the circuit.Type: ApplicationFiled: November 12, 2012Publication date: March 21, 2013Inventors: Etsuo Yamamoto, Yuhichiroh Murakami, Eiji Matsuda
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Patent number: 8379790Abstract: An object is to enhance the driving capability and improve the operating speed of a unit shift register applicable to a scanning line driving circuit having a partial display function. A unit shift register forming a gate line driving circuit includes a first transistor that supplies a first clock signal to a first output terminal, a second transistor that supplies a second clock signal to a second output terminal, a third transistor that charges the gate of the first transistor in response to activation of a shift signal of the previous stage, and a fourth transistor connected between the gate of the first transistor and the gate of the second transistor. The first clock signal and the second clock signal have the same phase, and only the second clock signal is activated in a particular period (a display ineffective period).Type: GrantFiled: February 3, 2011Date of Patent: February 19, 2013Assignee: Mitsubishi Electric CorporationInventor: Youichi Tobita
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Patent number: 8369479Abstract: The present invention relates to a shift register having a plurality of stages electrically coupled to each other in series. Each stage includes a first and second TFT transistor. The first TFT transistor has a get electrically coupled to the output of the immediately prior stage, a drain electrically coupled to the boost point of the stage, and a source configured to receive one of the first and second control signals. The second TFT transistor has a get electrically coupled to the output of the immediately next stage, a drain and a source electrically coupled the drain and the source of the first transistor, respectively.Type: GrantFiled: August 2, 2011Date of Patent: February 5, 2013Assignee: Au Optronics CorporationInventors: Ching-Huan Lin, Sheng-Chao Liu, Kuan-Chun Huang, Chih-Hung Shih
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Patent number: 8345028Abstract: A driving circuit applied in an electronic display apparatus is provided. The driving circuit includes a first exchange circuit and a first buffer. The first buffer includes first and second input stages, a second exchange circuit and first and second output stages. The first exchange circuit selectively couples a first input signal and a first output signal outputted from the first output stage to one of the first and the second input stages; and selectively couples a second input signal and a second output signal outputted from the second output stage to the other of the first and the second input stages. The second exchange circuit selectively couples the first input stage to one of the first and the second output stages and selectively couples the second input stage to the other of the first and the second output stages.Type: GrantFiled: August 5, 2010Date of Patent: January 1, 2013Assignee: Raydium Semiconductor CorporationInventors: Chih-Chuan Huang, Yu-Lung Lo, Hsin-Yeh Wu
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Patent number: 8340240Abstract: A shift register includes a plurality of shift register units coupled in series. Each shift register unit, receiving an input voltage at an input end and an output voltage at an output end, includes a node, a pull-up driving circuit, a pull-up circuit and first through third pull-down circuits. The pull-up driving circuit can transmit the input voltage to the node, and the pull-up circuit can provide the output voltage based on a high-frequency clock signal and the input signal. The first pull-down circuit can provide a bias voltage at the node or at the output end based on a first low-frequency clock signal. The second pull-down circuit can provide a bias voltage at the node or at the output end based on a second low-frequency clock signal. The third pull-down circuit can provide a bias voltage at the node or at the output end based on a feedback voltage.Type: GrantFiled: June 10, 2012Date of Patent: December 25, 2012Assignee: AU Optronics Corp.Inventors: Tsung-Ting Tsai, Ming-Sheng Lai, Min-Feng Chiang, Chun-Hsin Liu
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Publication number: 20120306829Abstract: A shift register includes a plurality of stages of unit circuits each including a flip-flop. Each of the unit circuits generates, by obtaining a sync signal in accordance with an output from the flip-flop, an output signal. The flip-flop includes a first switch and a second switch and a latch circuit for latching a signal supplied thereto and outputting the signal as the output from the flip-flop. A first shift direction signal is supplied to the latch circuit via the first switch, and the second shift direction signal is supplied to the latch circuit via the second switch. In each unit circuit other than those of the first and last stages, an output signal from a previous stage is supplied to a control terminal of the first switch, and an output signal from a subsequent stage is supplied to a control terminal of the second switch.Type: ApplicationFiled: February 10, 2011Publication date: December 6, 2012Applicant: SHARP KABUSHIKI KAISHAInventors: Shige Furuta, Yuhichiroh Murakami, Yasushi Sasaki, Takahiro Yamaguchi, Seijirou Gyouten
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Patent number: 8320516Abstract: An object of the present invention is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. In an embodiment of the pulse signal output circuit, a transistor has a source terminal or a drain terminal connected to a gate electrode of another transistor having a source terminal or a drain terminal forming an output terminal of the pulse signal output circuit, the channel length of the transistor being longer than the channel length of the other transistor. Thereby, the amount of a leakage current modifying the gate potential of the other transistor can be reduced, and a malfunction of the pulse signal output circuit can be prevented.Type: GrantFiled: February 22, 2011Date of Patent: November 27, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Kouhei Toyotaka
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Publication number: 20120293467Abstract: A gate driving circuit includes a shift register and a vertical start line. The shift register includes first to N-th circuit stages sequentially providing first to N-th gate-on signals to first to N-th gate lines, respectively, at least one reverse dummy stage adjacent to the first circuit stage and at least one forward dummy stage adjacent to the N-th circuit stage (N is a natural number). The vertical start line is electrically connected to the first circuit stage or the N-th circuit stage according to a scan direction and transfers a vertical start signal to the first or N-th circuit stage.Type: ApplicationFiled: November 21, 2011Publication date: November 22, 2012Inventors: Jae-Hoon Lee, Bon-Yong Koo, Seung-Hwan Moon, Won-Hee Lee
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Patent number: 8306177Abstract: A pull-up driving part maintains a signal of a first node at a high level by receiving a turn-on voltage in response to one of a previous stage or a vertical start signal. A pull-up part outputs a clock signal through an output terminal in response to the signal of the first node. A first holding part maintains a signal of a second node at a high level or a low level when the signal of the first node is respectively low or high. A second holding part maintains the signal of the first node and a signal of the output terminal at a ground voltage in response to the signal of the second node or a delayed and inverted clock signal.Type: GrantFiled: October 8, 2009Date of Patent: November 6, 2012Assignee: Samsung Display Co., Ltd.Inventors: Hong-Woo Lee, Sung-Man Kim, Jong-Hyuk Lee, Jong-Hwan Lee, Hyeon-Hwan Kim, Sang-Moon Moh, Jeong-Il Kim, Yeon-Kyu Moon
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Patent number: 8284890Abstract: A shift register includes individually connected shift register units. Each shift register unit includes a switching unit, a pre-charging unit, a pulse signal output unit, a low level voltage signal control unit, a first clock pulse signal input, a second clock pulse signal input, and an output. The first and the second clock pulse signal inputs respectively receive a first clock signal and a second clock signal, the first clock signal and the second clock signal having reverse clock pulses during each clock cycle. The switching unit receives at least one external starting signal and a high level signal, when the at least one external starting signal is high level, the switching unit is turned on and outputs the high level signal to the pre-charging unit. When the second clock signal is high level, the pre-charging unit receives the high level signal and charges, and when the first clock signal is high level, the pre-charging unit discharges.Type: GrantFiled: November 30, 2010Date of Patent: October 9, 2012Assignee: Chimei Innolux CorporationInventor: Chien-Hsueh Chiang
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Patent number: 8270558Abstract: An electronic device is provided which comprises a barrel shifter unit (BS) for performing a rotation of an input. The barrel shifter unit comprises a first and second barrel shifter (BS1, BS2). The electronic device furthermore comprises a selection unit for selecting a first set of elements (a) for the second barrel shifter (BS2) and a second set of elements for the first barrel shifter (BS1). The electronic device furthermore comprises a plurality of second multiplexers (M1 M8) for receiving the input of the second barrel shifter as first input and the output of the first barrel shifter as second input.Type: GrantFiled: September 9, 2008Date of Patent: September 18, 2012Assignee: ST-Ericsson SAInventor: John Dielissen
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Patent number: 8265222Abstract: A shift register is disclosed, which can prevent malfunctioning of device by decreasing the load on a discharging voltage source line, and can decrease a size of stage. The shift register comprises a plurality of stages to sequentially output scan pulses through respective output terminals, wherein each of the stages comprises a pull-up switching unit controlled based on a signal state of node, and connected between the output terminal and any one among a plurality of clock transmission lines to transmit the clock pulses provided with sequential phase differences; and a node controller to control the signal state of node, and to discharge the node by using the clock pulse from any one among the plurality of clock transmission line.Type: GrantFiled: July 21, 2011Date of Patent: September 11, 2012Assignee: LG Display Co., Ltd.Inventor: Yong Ho Jang
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Patent number: 8259895Abstract: A bidirectional shift register includes first, second, third and fourth control signal bus lines for providing first, second, third and fourth control signals, Bi1, Bi2, Bi3 and Bi4, respectively, and a plurality of shift register stages electrically coupled in serial, each shift register stage having first and second input nodes, where the shift register stages are grouped into a first section and a second section, where the first and second input nodes of each shift register stage in the first section are electrically coupled to the first and second control signal bus lines for receiving the first and second control signals Bi1 and Bi2, respectively, and the first and second input nodes of each shift register stage in the second section are electrically coupled to the third and fourth control signal bus lines for receiving the third and fourth control signals Bi3 and Bi4, respectively.Type: GrantFiled: December 19, 2011Date of Patent: September 4, 2012Assignee: Au Optronics CorporationInventors: Sheng-Chao Liu, Kuang-Hsiang Liu, Chien-Chang Tseng, Tsang-Hong Wang
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Patent number: 8238512Abstract: Disclosed is a dual shift register that includes a first shift register configured to include a plurality of stages which sequentially output scan pulses using at least two clock signals with sequential and circular phases, and a second shift register configured to a plurality of stages which form pair with the respective stages of the first shift register and sequentially output the scan pulses using at least two clock signals. Each stage includes: a scan direction controller configured to respond to the scan pulses from previous and next stages and to selectively output forward and reverse direction voltages with opposite electric potentials to each other; and an output portion configured to respond to the output signal of the scan direction controller, to generate two sequential scan pulses using two of the at least two clock signals, and to distribute the sequential scan pulses to the previous and next stages.Type: GrantFiled: January 19, 2012Date of Patent: August 7, 2012Assignee: LG Display Co., Ltd.Inventor: Hong Jae Kim
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Patent number: 8229058Abstract: A shift register includes a plurality of shift register units coupled in series. Each shift register unit, receiving an input voltage at an input end and an output voltage at an output end, includes a node, a pull-up driving circuit, a pull-up circuit and first through third pull-down circuits. The pull-up driving circuit can transmit the input voltage to the node, and the pull-up circuit can provide the output voltage based on a high-frequency clock signal and the input signal. The first pull-down circuit can provide a bias voltage at the node or at the output end based on a first low-frequency clock signal. The second pull-down circuit can provide a bias voltage at the node or at the output end based on a second low-frequency clock signal. The third pull-down circuit can provide a bias voltage at the node or at the output end based on a feedback voltage.Type: GrantFiled: October 27, 2009Date of Patent: July 24, 2012Assignee: AU Optronics Corp.Inventors: Tsung-Ting Tsai, Ming-Sheng Lai, Min-Feng Chiang, Chun-Hsin Liu
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Publication number: 20120162170Abstract: A bidirectional shift register capable of performing a stable shift operation in both directions and an image display device using the same are provided. In forward shift operation, when reference point N1 is at H level, (n+4)-th unit register circuit as a rear stage of the bidirectional shift register outputs pulse G(n+4) in synchronization with clock pulse V (n+4) inputted to (n+4)-th unit register circuit. A backward direction trigger signal VSTB is generated not only at the time of start of backward shift, but also, for example, in period (time t4 to t5) of one-phase clock immediately after G(n+4) is outputted in vertical blanking interval of the forward shift. The backward direction trigger signal VSTB is inputted to gate of a transistor provided to set reference point N1 of (n+4)-th unit register circuit to H level at the time of start of the backward shift.Type: ApplicationFiled: December 22, 2011Publication date: June 28, 2012Inventors: Takahiro OCHIAI, Mitsuru GOTO, Hiroyuki HIGASHIJIMA, Yoshihiro KOTANI, Shuuichirou MATSUMOTO
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Publication number: 20120114092Abstract: Disclosed is a dual shift register that includes a first shift register configured to include a plurality of stages which sequentially output scan pulses using at least two clock signals with sequential and circular phases, and a second shift register configured to a plurality of stages which form pair with the respective stages of the first shift register and sequentially output the scan pulses using at least two clock signals. Each stage includes: a scan direction controller configured to respond to the scan pulses from previous and next stages and to selectively output forward and reverse direction voltages with opposite electric potentials to each other; and an output portion configured to respond to the output signal of the scan direction controller, to generate two sequential scan pulses using two of the at least two clock signals, and to distribute the sequential scan pulses to the previous and next stages.Type: ApplicationFiled: January 19, 2012Publication date: May 10, 2012Inventor: Hong Jae KIM
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Publication number: 20120112992Abstract: Disclosed is a display apparatus including two scanning circuits of the same configuration and layout, arranged on either sides of the display part. As long as one of the scanning circuits is in operation, the other scanning circuit is in a state in which no output signal is output.Type: ApplicationFiled: December 29, 2011Publication date: May 10, 2012Applicant: NLT TECHNOLOGIES, LTDInventors: TOMOHIKO OTOSE, MASAMICHI SHIMODA
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Publication number: 20120087461Abstract: A bidirectional shift register includes first, second, third and fourth control signal bus lines for providing first, second, third and fourth control signals, Bi1, Bi2, Bi3 and Bi4, respectively, and a plurality of shift register stages electrically coupled in serial, each shift register stage having first and second input nodes, where the shift register stages are grouped into a first section and a second section, where the first and second input nodes of each shift register stage in the first section are electrically coupled to the first and second control signal bus lines for receiving the first and second control signals Bi1 and Bi2, respectively, and the first and second input nodes of each shift register stage in the second section are electrically coupled to the third and fourth control signal bus lines for receiving the third and fourth control signals Bi3 and Bi4, respectively.Type: ApplicationFiled: December 19, 2011Publication date: April 12, 2012Applicant: AU OPTRONICS CORPORATIONInventors: Sheng-Chao Liu, Kuang-Hsiang Liu, Chien-Chang Tseng, Tsang-Hong Wang
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Patent number: 8155261Abstract: The present invention relates to a shift register and a gate driver therefor.Type: GrantFiled: June 9, 2009Date of Patent: April 10, 2012Assignee: Beijing Boe Optoelectronics Technology Co., Ltd.Inventor: Ming Hu
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Patent number: 8121244Abstract: Disclosed is a dual shift register that includes a first shift register configured to include a plurality of stages which sequentially output scan pulses using at least two clock signals with sequential and circular phases, and a second shift register configured to a plurality of stages which form pair with the respective stages of the first shift register and sequentially output the scan pulses using at least two clock signals. Each stage includes: a scan direction controller configured to respond to the scan pulses from previous and next stages and to selectively output forward and reverse direction voltages with opposite electric potentials to each other; and an output portion configured to respond to the output signal of the scan direction controller, to generate two sequential scan pulses using two of the at least two clock signals, and to distribute the sequential scan pulses to the previous and next stages.Type: GrantFiled: July 1, 2010Date of Patent: February 21, 2012Assignee: LG Display Co., Ltd.Inventor: Hong Jae Kim
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Patent number: 8107586Abstract: A shift register comprises stages connected to each other, in which each stage generates an output signal in response to any one of clock signals and an output from each of two different stages. Each clock signal has a duty ratio of less than 50% and a different phase from each of the other clock signals. A display device includes pixels, signal lines, and first and second shift registers each having stages connected to each other and generating output signals to signal lines. Each stage includes a set terminal, a reset terminal, a clock terminal, and first and second output terminals.Type: GrantFiled: March 11, 2005Date of Patent: January 31, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Kyong-Ju Shin, Chong-Chul Chae, Mun-Pyo Hong, Cheol-Woo Park, Nam-Seok Roh
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Patent number: 8102962Abstract: A bidirectional shift register includes first, second, third and four control signal bus lines for providing first, second, third and fourth control signals, Bi1, Bi2, Bi3 and Bi4, respectively, and a plurality of shift register stages electrically coupled in serial, each shift register stage having a first input node and a second input node, where the plurality of shift register stages is grouped into a first section and a second section, wherein the first and second input nodes of each shift register stage in the first section are electrically coupled to the first and second control signal bus lines for receiving the first and second control signals Bi1 and Bi2, respectively, and the first and second input nodes of each shift register stage in the second section are electrically coupled to the third and fourth control signal bus lines for receiving the third and fourth control signals Bi3 and Bi4, respectively.Type: GrantFiled: January 11, 2010Date of Patent: January 24, 2012Assignee: AU Optronics CorporationInventors: Sheng-Chao Liu, Kuang-Hsiang Liu, Chien-Chang Tseng, Tsang-Hong Wang
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Patent number: 8089448Abstract: A data driver for time-division multiplexing includes a first memory cell set having first memory cells, a second memory cell set having second memory cells, and a plurality of output lines. Each first memory cell is used for generating a first data signal in response to a first sampling control signal, and for outputting the first data signal in response to a first transmitting control signal. Each second memory cell is used for generating a second data signal in response to a second sampling control signal, and for outputting the second data signal in response to a second transmitting control signal. During a first line time period, the first sampling control signal is triggered while the second transmitting control signal is triggered. During a second line time period, the first transmitting control signal is triggered while the second sampling control signal is triggered.Type: GrantFiled: February 9, 2009Date of Patent: January 3, 2012Assignee: AU Optronics Corp.Inventor: Chung-chun Chen
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Publication number: 20110316831Abstract: A plurality of cascaded unit register circuits which comprises a bidirectional shift register include main stages and dummy stages at the top before the main stages and dummy stages at the bottom after the main stages. A k-th stage outputs a pulse Pk in synchronization with a clock signal with a reference point N1 being at H level. The main stages include terminals NSF and NSB for setting N1 to H to which Pk?1 and Pk+1 are input, respectively, and terminals NRB and NRF for setting N1 to L level to which Pk?2 and Pk+2 are input, respectively. The order of generation of clock signals is reversed according to the direction of a shift, and whether a start trigger signal is applied to a top stage or a bottom stage is switched. Top dummy stages do not have NRB. Bottom dummy stages do not have NRF.Type: ApplicationFiled: June 21, 2011Publication date: December 29, 2011Inventors: Takahiro OCHIAI, Mitsuru Goto, Hiroko Sehata, Hiroyuki Higashijima
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Publication number: 20110310074Abstract: A bidirectional shift register outputs pulses from a plurality of cascaded unit register circuits in a shift order which is one of a forward direction and a reverse direction. A ?th stage of unit register circuit (38) has two set terminals connected to respective outputs of (??1)th and (?+1)th stages and two reset terminals connected to respective outputs of (?+2)th and (??2)th stages. The unit register circuit (38) sets, when a pulse is input to any one of the set terminals, a reference point N1 to an H level, and, when a pulse is input to any one of the reset terminals, N1 to an L level. The order of phase change of clock signals is reversed according to the direction of a shift, and whether a start trigger signal is applied to a top stage or a bottom stage is switched.Type: ApplicationFiled: June 21, 2011Publication date: December 22, 2011Inventors: Takahiro OCHIAI, Mitsuru GOTO, Hiroko SEHATA, Hiroyuki HIGASHIJIMA
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Patent number: 8059780Abstract: An exemplary shift register circuit includes a shift register, a first switching circuit and a second switching circuit. The shift register has a start pulse signal input terminal and a start pulse signal output terminal. The first switching circuit includes a first input switch unit and a second output switch unit respectively electrically coupled to the start pulse signal input terminal and the start pulse signal output terminal. The second switching circuit includes a second input switch unit and a first output switch unit respectively electrically coupled to the start pulse signal input terminal and the start pulse signal output terminal. Moreover, on-off states of the first input and first output switch units are opposite to on-off states of the second input and second output switch units. Moreover, a gate driving circuit using the above-mentioned shift register and switching circuits also is provided.Type: GrantFiled: August 2, 2010Date of Patent: November 15, 2011Assignee: Au Optronics Corp.Inventors: Po-Kai Wang, Chun-Hao Huang, Chung-Hung Peng
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Patent number: 8050379Abstract: An exemplary shift register (20) includes a plurality of shift register units (200) connected one by one. Each of the shift register units includes a clock signal input terminal (TS), a high level signal input terminal (VH), a low level signal input terminal (VL), an input terminal (VIN), a first output terminal (VOUT1), a second output terminal (VOUT2), a first common node (P1), a second common node (P2), a first switch circuit (31), a second switch circuit (32), a third switch circuit (33), a fourth switch circuit (34), a fifth switch circuit (35), a six switch circuit (36), a nor gate, an inverter, and an and gate.Type: GrantFiled: February 6, 2008Date of Patent: November 1, 2011Assignee: Chimei Innolux CorporationInventors: Chien-Hsueh Chiang, Sz-Hsiao Chen
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Patent number: 8045675Abstract: A bi-directional shift register includes N stages, wherein the mth stage among the N stages includes a node, an output end, first input circuit, second input circuit, and a shift register unit. N is a natural number greater than 1 and m is a natural number smaller than or equal to N. First control signal is measured on the node. The output end outputs an mth output signal. The first input circuit receives an m?1th output signal as a control signal and a power signal to accordingly generate an enabled first driving signal to the node in first period. The second input circuit receives an m+1th output signal as a control signal and a power signal to accordingly generate an enabled second driving signal to the node in second period. Controlled by the first control signal, the shift register unit generates an mth output signal in third period.Type: GrantFiled: July 20, 2010Date of Patent: October 25, 2011Assignees: Dongguan Masstop Liquid Crystal Display Co., Ltd., Wintek CorporationInventors: Chien-Ting Chan, Hsi-Rong Han, Wen-Chun Wang
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Patent number: 8044894Abstract: After a sampling transistor is turned ON at a first timing when a control signal has risen, during a sampling period from a second timing when a video signal has risen from a reference potential to a signal potential to a third timing when the control signal has fallen and is turned OFF, the sampling transistor samples and writes the signal potential in a holding capacitance, and negatively feeds back a current flowing into a drive transistor during the sampling period to the holding capacitance and applies mobility correction of the drive transistor on the written signal potential. A signal driver adjusts the second timing for the video signal supplied to respective signal lines to correct a backward shift of the third timing due to a transmission delay along a scanning line of the control signal output from the control scanner.Type: GrantFiled: March 12, 2008Date of Patent: October 25, 2011Assignee: Sony CorporationInventors: Katsuhide Uchino, Tetsuro Yamamoto
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Patent number: 8023611Abstract: The present invention relates to a shift register having a plurality of stages electrically coupled to each other in series. Each stage includes a first and second TFT transistor. The first TFT transistor has a get electrically coupled to the output of the immediately prior stage, a drain electrically coupled to the boost point of the stage, and a source configured to receive one of the first and second control signals. The second TFT transistor has a get electrically coupled to the output of the immediately next stage, a drain and a source electrically coupled the drain and the source of the first transistor, respectively.Type: GrantFiled: May 11, 2010Date of Patent: September 20, 2011Assignee: Au Optronics CorporationInventors: Ching-Huan Lin, Sheng-Chao Liu, Kuan-Chun Huang, Chih-Hung Shih
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Patent number: 8018423Abstract: A shift register is for generating scan signals. Each stage of the shift register comprises a first level lifting unit and at least a second level lifting unit, a first level lowering unit and at least a second level lowering unit, first and second driving units. The first level lowering and lifting units are for controlling the levels of signals at the first output terminal to output a first scan signal. The second level lowering unit and second level lifting unit are for controlling the levels of signals at the second output terminal to output at least a second scan signal. The first and second driving units are for turning on and off the first and the second level lifting units and the first and the second level lowering unit to control the first and second scan signals.Type: GrantFiled: April 24, 2008Date of Patent: September 13, 2011Assignee: Wintek CorporationInventors: Yi-Cheng Tsai, Chien-Ting Chan, Hsi-Rong Han, Wen-Chun Wang, Kuo-Chang Su