Abstract: A serial data receiving circuit comprising a most significant bit input detecting circuit (20) for providing a given control signal in synchronism with input of the most significant bit of a serial data represented by twos complement and a data converter circuit (30B) for subjecting the serial data to a sign extension data when the control signal is active and providing the resultant sign extended data as a parallel data and shifting the serial data from a low order bit to a high order bit when the control signal is inactive and providing the shifted data as a parallel data.

Abstract: Digital ratiometer and amplitude analyzer using such a ratiometer.It is possible to solve the problems of the calculation and display of the ratio of two or more quantities, provided that the latter are converted into frequencies. Counting registers are used for evaluating these quantities. The filling of these counting registers (6,13) is prevented by bringing about a shift to the right (10,19) of all the registers as soon as (15) one of them is filled.

Abstract: An integrated memory circuit in which memory cells are arranged in rows and columns, each column having a separate sense amplifier. The memory columns can be coupled to neighboring memory columns by additional transistors and the gain of the sense amplifiers in the even and the odd columns is adjustable. Consequently, information can also be serially shifted from one column to another, so that the information can be written and read not only in parallel but also serially.

Abstract: A universal shift register (200) utilizes a matrix (236-251) of high speed transmission gates to effect the various modes of register data manipulation in place of conventional operating mode selection logic gate elements. The shift register additionally includes apparatus allowing for the cascading of the register with units of similar design.

Abstract: A data processing circuit having a bit reverse function and including a bit reverse circuit which reverses a bit string of data and a shifting circuit which shifts the data with the reversed bit string such that a part of the bit string or arbitrary bits of the data may be selectively reversed according to an information representing bits to be reversed.

Abstract: There is disclosed a barrel shifter for providing efficient wiring therein and a compact composition as compared with conventional ones, in which a low-level-input resistor and a high-level-input resistor are arranged in parallel to each other, and low-level-input-bit lines and high-level-input-bit lines are alternately arranged corresponding to both resistors respectively, the width of both the input and output sides of a barrel-shifter main unit are so arranged as to be substantially the same as the width of the respective resistors substantially defined by wiring width of the respective input-bit lines, and a wiring area from the high-level-input resistor is incorporated in the barrel-shifter main unit as well as a wiring area from the low-level-input resistor.

Abstract: A dual storage cell memory includes an array of dual storage cells, each of the dual storage cells containing a first memory cell and a second memory cell. The first and second memory cells are well known six-transistor static memory cells with the addition of transfer circuitry for transferring data directly from the internal data nodes of each of the memory cells to its corresponding complementary memory cell without requiring the use of the enable transistors or the bit lines associated with each of the dual storage cells.

Abstract: In the present invention, a reprogrammable control circuit is disclosed. The reprogrammable control circuit comprises a single-bit register for serially receiving an input bit signal and providing a control signal. The control signal represents the state of the bit stored in the register. A transmission gate means receives the control signal from the single-bit shift register and an input signal and provides an output signal therefrom. The control signal of the bit shift register is used to control the transmission of the input signal to the output signal. A plurality of reprogrammable control circuit which comprises a plurality of bit shift registers, each having a transmission gate means associated therewith is also disclosed. The reprogrammable control circuit can be used in an improved PLA, improved RAM, improved RCIM, improved ALU, improved counter, improved CAM, PCN to improve the reliability of routing signals and power, and to preserve the states of flip-flops.

Abstract: A pipeline binary updown counter is comprised of simple stages that may be readily replicated. Each stage is defined by the Boolean logic equationA.sub.n (t)=A.sub.n (t-1).sym.[(U.multidot.P.sub.n)+(D.multidot.Q.sub.n)]where A.sub.n (t) denotes the value of the nth bit at time t. The input to the counter has three values represented by two binary signals U and D such that if both are zero, the input is zero, if U=0 and D=1, the input is -1 and if U=1 and D=0, the input is +1. P.sub.n represents a product of A.sub.k 's for 1.ltoreq.k.ltoreq.-1, while Q.sub.n represents the product of A's for 1.ltoreq.k.ltoreq.n-1, where A.sub.k is the complement of A.sub.k and P.sub.n and Q.sub.n are expressed as the following two equationsP.sub.n =A.sub.n-1 A.sub.n-2 . . . A.sub.1Q.sub.n =A.sub.n-1 A.sub.n-2 . . . A.sub.1which can be written in recursion form asP.sub.n =P.sub.n-1 .multidot.A.sub.n-1Q.sub.n =Q.sub.n-1 .multidot.A.sub.n-1with the initial values P.sub.1 =1 and Q.sub.1 =1.

Abstract: A barrel shifter including a first bit reverse unit which reverses the bit position of all bits of input data or passes the bit positions to leave them as they are; a bit shift unit which shifts output bits from the first bit reverse unit in one fixed direction by exactly the number of bits to be shifted; and a second bit reverse unit which reverses the bit position of all bits of input data or passes the bit positions to leave them as they are, to produce the desired output data. Thus, even if there is an increase of the number of bits of the input data, the hardware structure and control do not become complicated and the use of integrated circuits (ICs) is made easy.

Abstract: In a semiconductor integrated circuit device having at least one shift register, a plurality of 5 stages of the shift register are electrically connected in series, the 1st stage of said shift register is located in the closest position to the data input terminal, and other succeeding stages are sequentially and straightly located at intervals; the chain of the stages is folded at a particular stage, and further succeeding stages are sequentially and straightly located at intervals so as to fill in the spaces between the other stages, thus, the unbalance of the load capacitance between said stages and the functional unbalance between the shift registers can be minimized.

Abstract: Apparatus is disclosed for reversing the bit order of a portion of a digital word. The apparatus contains a shifter, connected to the input through a bit reversing means, and selector means which forms an output word by selecting appropriate bits either directly from the input word or from the output of the shifter.

Abstract: A queue form of asynchronous register is disclosed with signal paths commonly carrying elements of both data and control. Binaries are intercoupled in two sequences and are individually cross coupled to register "one" bits in one sequence and "zero" bits in the other. Bits are manifest by signal level changes. Individual binaries are driven by logic to accomplish an operational rule based on the states of neighboring binaries in both sequences. Each binary in each sequence is controlled by the states of the predecessor and successor in its sequence and the predecessor and successor of its associated binary in the other sequence. Specifically, if predecessor and successor binaries in a sequence are in different states, and predecessor and successor binaries of an associated binary in the other sequence are in the same state, the state of the predecessor is to be taken.

Abstract: A bidirectional barrel shift circuit includes an input switching circuit having a plurality of parallel input lines and the corresponding number of first and second signal line pairs associated to the respective input lines. This input switching circuit is operative to selectively connect each of the input lines to one line of the associated first and second signal line pair. There is also provided an output switching circuit connected to all the first and second singal lines and having output lines of the number corresponding to that of the input lines. This output switching circuit is operative to connect either the first signal lines or the second signal lines to the corresponding output lines. A barrel shift matrix is connected to the first and second signal lines and is controlled by a shift number controller so as to produce between the first and second signal lines a connection pattern sufficient for realizing a given shift number.

Abstract: A shift register which, including a plurality of cells each comprising a data latch section and a shift control section, operates without external clocks, wherein the shift control section includes a terminal for receiving a shift start control signal; a terminal for receiving a shift inhibition control signal; a shift allowance control circuit which receives signals indicating as to whether each of the particular cell and the cells adjacent thereto is in a shift operation and signals indicating as to whether each of the adjacent cells is in a state which allows the shift of the particular cell, and generates a shift allowance signal to be given to the particular cell and the adjacent cells on the basis of the states of these cells and the shift inhibition control signal; a shift control circuit which receives the shift start control signal, the output of the shift allowance control circuit, the state signals of the particular cell and the adjacent cell, and makes the data latch section to conduct a shift ope

Abstract: A bidirectional shift register includes a plurality of serially connected cells with each cell having a first circuit portion and a second circuit portion. Each circuit portion includes at least two parallel inverters connected in opposite directions. The relative transconductance of the oppositely connected inverters in each circuit portion of a cell can be varied thereby determining the direction of data flow through the circuit portion and through the bidirectional shift register.

Abstract: A plurality of cascaded RS flip-flops are enabled by gating circuitry coupled between the output of the last RS flip-flop of the cascaded RS flip-flops and the set and reset inputs of the RS flip-flops to enable digital data stored in a preceding or following RS flip-flop to be shifted into an adjacent following or preceding RS flip-flop upon successive occurrences of complementary clocking pulses applied to the gating circuitry.

Abstract: A linear array of bistable data latches and logic gates arranged to count the binary transitions, both low to high and high to low, of a clock signal and provide a threshold style output code, characterized along the array by high logic states on one side of the threshold point and low logic states on the opposite side. Each latch in the array is permitted to set when a clock transition occurs after the preceding latch has set or to reset when a clock transition occurs after the succeeding latch has reset. Clock phasing and count enable/disable logic may be included along with direct set/reset inputs in order to accomplish parallel and/or ripple preset/clear functions or other output code modifications.

Abstract: A drop-out detector for detecting the absence of a pulse in either of first and second pulse trains, especially for use with the spindle servo error generator of a videodisc mastering machine. Prior attempts at providing a drop-out detector function for the spindle servo error generator rely on the use of RC based timing circuits to create time windows within which to look for the presence or absence of a reference or tach pulse, as the case may be. Such arrangements provide satisfactory performance in connection with constant angular velocity type discs, since reference and tach frequencies remain constant throughout the mastering process. However, problems arise in utilizing such RC based circuits in connection with constant linear velocity type discs. The present invention overcomes these problems by operating on a pulse width modulation technique for controlling the spindle motor speed.

Abstract: A general purpose retiming circuit comprising a timing signal source for generating timing signals, a plurality of N registers arranged in a row in a given order with each register having an input terminal, an output terminal, and clock input terminal and responsive to timing signals supplied thereto to transfer the signal supplied to said input terminal means to said output terminal. There is provided a serial input terminal for supplying a serial input signal thereto. Also provided are N switches arranged in the given order and each having first and second input terminals and an output terminal which is connected to the input terminal of a corresponding register of said row of N registers, and with the first input terminal of a first of the N switches being connected to the serial input terminal and the first input terminal of each of the remainder of the N switches being connected to the output terminal of the register preceding the corresponding register in the row of registers.