Semiconductor Component Patents (Class 428/620)
  • Patent number: 9960092
    Abstract: To provide an interlayer filler composition which, in 3D lamination of semiconductor device chips, forms a highly thermally conductive filling interlayer simultaneously with the bonding of solder bumps or the like and lands between semiconductor device chips, a coating fluid and a process for producing a three-dimensional integrated circuit. An interlayer filler composition for a three-dimensional integrated circuit, which comprises a resin (A) having a melt viscosity at 120° C. of at most 100 Pa·s and a flux (B), the content of the flux (B) being at least 0.1 part by weight and at most 10 parts by weight per 100 parts by weight of the resin (A).
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: May 1, 2018
    Assignee: Mitsubishi Chemical Corporation
    Inventors: Makoto Ikemoto, Yasuhiro Kawase, Tomohide Murase, Makoto Takahashi, Takayoshi Hirai, Iho Kamimura
  • Patent number: 9954297
    Abstract: A terminal fitting having a smaller terminal insertion force than before. The terminal fitting includes a backing material made of a metal material and a plating coating covering a surface of the backing material. The plating coating contains a Sn parent phase and Sn—Pd based particles dispersed in the Sn parent phase and includes an outermost layer having an outer surface in which the Sn parent phase and the Sn—Pd based particles are present. Further, the number of the Sn—Pd based particles present in the outer surface of the plating coating in a state where only the Sn parent phase is removed is 10 to 400 Sn—Pd based particles per 500 ?m2.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: April 24, 2018
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Hajime Watanabe, Yoshifumi Saka, Shigeru Sawada
  • Patent number: 9799526
    Abstract: An etching method includes etching a silicon substrate with a liquid composition containing an alkaline organic compound, water, and a boron compound with a content in the range of 1% by mass to 14% by mass. The boron compound is at least one of boron sesquioxide, sodium tetraborate, metaboric acid, sodium perborate, sodium borohydride, zinc borate, and ammonium borate.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: October 24, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Hirohisa Fujita, Taichi Yonemoto, Shuji Koyama
  • Patent number: 9732196
    Abstract: One embodiment relates to an, article and a method for producing an article including a plurality of substrates, and an adhesive bonded between at least two of the plurality of substrates. The adhesive can include a polycarbonate copolymer that includes reacted resorcinol, siloxane, and bisphenol-A. Another embodiment relates to an article having a first polyimide substrate, a second polyimide substrate, and an adhesive bonded between the first substrate and the second substrate. The article can have a 2 minute integrated heat release rate of less than or equal to 65 kilowatt-minutes per square meter (kW?min/m2) and a peak heat release rate of less than 65 kilowatts per square meter (kW/m2) as measured using the method of FAR F25.4, in accordance with Federal Aviation Regulation FAR 25.853(d).
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: August 15, 2017
    Assignee: SABIC GLOBAL TECHNOLOGIES B.V.
    Inventors: Erich Otto Teutsch, Craig Milne
  • Patent number: 9673547
    Abstract: The present invention aims to provide a plated terminal for connector which requires a smaller insertion force by reducing a friction coefficient and a terminal pair formed using such a plated terminal for connector. An alloy containing layer (1) made of tin and palladium and containing a tin-palladium alloy is formed on a surface of a terminal base material (2) made of copper or copper alloy. Here, the alloy containing layer (1) is preferably such that domain structures of a first metal phase (11) made of an alloy of tin and palladium are formed in a second metal phase (12) made of pure tin or an alloy having a higher ratio of tin to palladium than in the first metal phase (11).
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: June 6, 2017
    Assignees: AUTONETWORKS TECHNOLOGIES, LTD., SUMITOMO WIRING SYSTEMS, LTD., SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Yoshifumi Saka, Hajime Watanabe, Mikio Satou, Masayuki Ookubo
  • Patent number: 9651539
    Abstract: Methods for fabricating materials useful for optical detection in microfluidic and nanofluidic devices, such as those used in nanopore-based nucleic acid sequencing are described herein. In certain variations, a method of reducing background fluorescence in a MEMS material may include the step of treating a surface of the MEMS material with a low energy ion beam.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: May 16, 2017
    Assignee: Quantapore, Inc.
    Inventors: Martin Huber, Bason E. Clancy, Adam R. Hall
  • Patent number: 9508648
    Abstract: To provide a three-dimensional integrated circuit laminate filled in with an interlayer filler composition having both high thermal conductivity and low linear expansion property, a three-dimensional integrated circuit laminate, which comprises a semiconductor substrate laminate having at least two semiconductor substrates each having a semiconductor device layer formed thereon laminated, and has a first interlayer filler layer containing a resin (A) and an organic filler (B) and having a thermal conductivity of at least 0.8 W/(rrrK) between the semiconductor substrate.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: November 29, 2016
    Assignee: Mitsubishi Chemical Corporation
    Inventors: Yasuhiro Kawase, Makoto Ikemoto, Hideki Kiritani
  • Patent number: 9466767
    Abstract: An optoelectronic device comprises a semiconductor stack, a first metal layer formed above the semiconductor stack, wherein the first metal layer comprises a first major plane and a first boundary with a gradually reduced thickness, and a second metal layer formed above the first metal layer, wherein the second metal layer comprise a second major plane paralleling to the first major plane and a second boundary with a gradually reduced thickness, and the second boundary of the second metal layer exceeds the first boundary of the first metal layer.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: October 11, 2016
    Assignee: EPISTAR CORPORATION
    Inventors: Jia-Kuen Wang, Chien-Fu Shen, Hung-Che Chen, Chao-Hsing Chen
  • Patent number: 9443814
    Abstract: A multi-chip package includes a substrate having a plurality of first bump structures. A pitch between first bump structures of the plurality of first bump structures is uniform across a surface of the substrate. The multi-chip package includes a first chip bonded to the substrate and a second chip bonded to the substrate. The first chip includes a plurality of second bump structures, and the plurality of second bump structures are bonded to a first set of first bump structures of the plurality of first bump structures. The second chip includes a plurality of third bump structures, and the plurality of third bump structures are bonded to a second set of first bump structures of the plurality of first bump structures. A pitch between second bump structures of the plurality of second bump structures is different from a pitch between third bump structures of the plurality of third bump structures.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: September 13, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Jing-Cheng Lin
  • Patent number: 9425120
    Abstract: A manufacturing method for a semiconductor device in which connection portions of a semiconductor chip are electrically connected to connection portions of a wiring circuit substrate or a semiconductor device in which connection portions of a plurality of semiconductor chips are electrically connected to each other, the method comprising a step of sealing at least part of the connection portions with an adhesive for a semiconductor comprising a compound having a group represented by the following formula (1): wherein R1 represents an electron-donating group.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: August 23, 2016
    Assignee: HITACHI CHEMICAL COMPANY, LTD
    Inventors: Kazutaka Honda, Akira Nagai, Makoto Satou
  • Patent number: 9312049
    Abstract: The invention relates to an electrical contact element, an electrical contact arrangement and methods for manufacturing an electrical contact element and for reducing oxidization of a contact section of an electrical contact element. In order to avoid that the durability of the contact element and therefore of the contact arrangement is negatively influenced by growing oxide layers on contact surfaces, the contact element is provided with a cover layer with a chemical reducing agent that can be activated by frictional forces.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: April 12, 2016
    Assignees: TE Connectivity Germany GmbH, Tyco Electronics Corporation
    Inventors: Helge Schmidt, Josh Golden
  • Patent number: 9287110
    Abstract: A semiconductor wafer electroless plating apparatus includes a platen and a fluid bowl. The platen has a top surface defined to support a wafer, and an outer surface extending downward from a periphery of the top surface to a lower surface of the platen. The fluid bowl has an inner volume defined by an interior surface so as to receive the platen, and wafer to be supported thereon, within the inner volume. A seal is disposed around the interior surface of the fluid bowl so as to form a liquid tight barrier when engaged between the interior surface of the fluid bowl and the outer surface of the platen. A number of fluid dispense nozzles are positioned to dispense electroplating solution within the fluid bowl above the seal so as to rise up and flow over the platen, thereby flowing over the wafer when present on the platen.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: March 15, 2016
    Assignee: Lam Research Corporation
    Inventors: William Thie, John M. Boyd, Fritz C. Redeker, Yezdi Dordi, John Parks, Tiruchirapalli Arunagiri, Aleksander Owczarz, Todd Balisky, Clint Thomas, Jacob Wylie, Alan M. Schoepp
  • Patent number: 9263565
    Abstract: A semiconductor structure comprises a first layer. The first layer comprises a first III-V semiconductor material. The semiconductor structure also comprises a second layer over the first layer. The second layer comprises a second III-V semiconductor material different from the first III-V semiconductor material. The semiconductor structure further comprises an insulating layer over the second layer. The insulating layer is patterned to expose a portion of the first layer. The exposed portion of the first layer comprises electrons of the second layer. The semiconductor structure additionally comprises an intermetallic compound over the exposed portion of the first layer.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: February 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Chih Chen, Jiun-Lei Jerry Yu, Fu-Wei Yao, Chun-Wei Hsu, Fu-Chih Yang, Chun Lin Tsai
  • Patent number: 9236278
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a dummy-die paddle having a first inactive side facing up, a second inactive side facing down; forming an insulator in a single continuous structure around and in direct contact with the first inactive side; and mounting an integrated circuit over the dummy-die paddle and the insulator, the integrated circuit and the dummy-die paddle having the same coefficient of thermal expansion as the dummy-die paddle.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: January 12, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: Rui Huang, Xusheng Bao, Kang Chen, Yung Kuan Hsiao, Hin Hwa Goh
  • Patent number: 9136194
    Abstract: The present invention provides a resin composition for encapsulating electronic components that contains a phenol resin curing agent and an epoxy resin, in which either the phenol resin curing agent or the epoxy resin has a biphenyl structure; a resin composition for encapsulating electronic components that contains a phenol resin curing agent and an epoxy resin, in which a glass transition temperature of a cured material is equal to or higher than 200° C., and a weight reduction rate of the cured material is equal to or lower than 0.3%; and an electronic device that includes an electronic component encapsulated with the resin composition.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: September 15, 2015
    Assignee: SUMITOMO BAKELITE CO., LTD.
    Inventors: Kenji Yoshida, Ken Ukawa, Yusuke Tanaka
  • Patent number: 9123607
    Abstract: An apparatus for infrared imaging may include a hybrid infrared focal plane array including a front-end (FE) portion and a back-end (BE) portion. The FE portion may be coupled to the BE portion via multiple electrically conductive bump bonds. The FE portion may include nano-electronic circuits integrated with an array of infrared imaging pixels. The CNT electronic circuits may be configured to generate multiplexed output signals. The BE portion may include electronic circuits implemented on a substrate and configured to generate readout output signals. A count of the multiple electrically conductive bump bonds may be substantially less than a count of the infrared imaging pixels of the array.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: September 1, 2015
    Assignee: LOCKHEED MARTIN CORPORATION
    Inventors: Ryan Michael Hatcher, Brent M. Segal, Robert Chris Bowen, Jonathan Wesley Ward
  • Patent number: 9117861
    Abstract: Embodiments in accordance with the present invention provide for materials, methods for using such materials and structures that both incorporate such materials and are made using such methods that can be smoothly debonded at or near room temperature while providing a fixable bond that allows for wafer processing such as wafer thinning, anisotropic dry etching and chemical resistance during plating and etching.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: August 25, 2015
    Inventors: Venkat Dukkipati, Kei Kawasaki, Larry Rhodes, Toshihiro Sato
  • Patent number: 9111901
    Abstract: Embodiments of methods for forming a semiconductor device that includes a die and a substrate include pressing together the die and the substrate such that a first gold layer and one or more additional material layers are between the die and the substrate, and performing a bonding operation to form a die attach layer between the die and the substrate. The die attach layer includes a gold interface layer that includes gold and a plurality of first precipitates in the gold. Each of the first precipitates includes a combination of nickel, cobalt, palladium, gold, and silicon.
    Type: Grant
    Filed: May 26, 2014
    Date of Patent: August 18, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jin-Wook Jang, Lalgudi M. Mahalingam, Audel A. Sanchez, Lakshminarayan Viswanathan
  • Patent number: 9105599
    Abstract: Embodiments of a semiconductor device include a primary portion of a substrate, a die, and a die attach layer between the die and the primary portion of the substrate. The die attach layer includes a gold interface layer that includes gold and a plurality of first precipitates in the gold. Each of the first precipitates includes a combination of nickel, cobalt, palladium, gold, and silicon.
    Type: Grant
    Filed: May 26, 2014
    Date of Patent: August 11, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jin-Wook Jang, Lalgudi M. Mahalingam, Audel A. Sanchez, Lakshminarayan Viswanathan
  • Patent number: 9087832
    Abstract: Various embodiments of mechanisms for forming a die package and a package on package (PoP) structure using one or more compressive dielectric layers to reduce warpage are provided. The compressive dielectric layer(s) is part of a redistribution structure of the die package and its compressive stress reduces or eliminates bowing of the die package. In addition, the one or more compressive dielectric layers improve the adhesion between redistribution structure and the materials surrounding the semiconductor die. As a result, the yield and reliability of the die package and PoP structure using the die package are improved.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: July 21, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chih Huang, Yen-Chang Hu, Ching-Wen Hsiao, Chen-Shien Chen
  • Patent number: 9082840
    Abstract: A method for preparing a semiconductor wafer into individual semiconductor dies uses both a dicing before grinding step and/or via hole micro-fabrication step, and an adhesive coating step.
    Type: Grant
    Filed: May 6, 2014
    Date of Patent: July 14, 2015
    Assignee: Henkel IP & Holding GmbH
    Inventors: Hwang Kyu Yun, Jeffrey Leon, Raj Peddi, YounSang Kim
  • Patent number: 9070566
    Abstract: A composite focal plane assembly with an expandable architecture has a multi-layer, double-sided aluminum nitride (AlN) substrate and vertical architecture to achieve the dual function of focal plane and electronics backplane. Imaging dice and other electrical components are mounted and wire bonded to one surface and then direct backplane connectivity is provided on the opposing surface through a matrix of electrical contacts. In one embodiment, a flexible connector is sandwiched between the AlN focal plane and a FR-4 backplane is used to compensate for differences in coefficient of thermal expansion (CTE) between the AlN and commercially available high density circuit card connectors that are commonly manufactured from materials with CTE properties more closely approximating FR-4. In an alternate embodiment, the FR-4 and flexible connectors are eliminated by using high density circuit card connectors that are fabricated out of materials more closely matching the CTE of AlN.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: June 30, 2015
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Raymond J. Silva, Dennis P. Bowler, Gene A. Robillard
  • Publication number: 20140374834
    Abstract: A germanium (Ge) structure includes a substrate, a Ge layer and at least a Ge spatial structure. The Ge layer is formed on the substrate, and a surface of the Ge layer is a Ge {110} lattice plane. The Ge spatial structure is formed in the Ge layer and includes a top surface and a sidewall surface, wherein the top surface is a Ge {110} lattice plane and the sidewall surface is perpendicular to the top surface. An axis is formed at a junction of the sidewall surface and the top surface, and an extensive direction of the axis is parallel to a Ge [112] lattice vector on the surface of the Ge layer, therefore the sidewall surface is a Ge {111} lattice plane. Because Ge {111} surface channels have very high electron mobility, this Ge spatial structure may be applied for fabricating high-performance Ge semiconductor devices.
    Type: Application
    Filed: June 20, 2013
    Publication date: December 25, 2014
    Inventors: Guang-Li Luo, Chee-Wee Liu, Shu-Han Hsu, Chun-Lin Chu, Chih-Hung Lo
  • Patent number: 8916675
    Abstract: A method for forming a polymer comprising the polymerization of a plurality of monomers, wherein at least one of the plurality of monomers is one or both of: a charge transporting unit and a hydrocarbon monomer in which at least one carbon atom has been substituted by an atom or group with a greater quantity of unshared valence electrons than the carbon atom it has been substituted for, and wherein at least one of the plurality of monomers comprises an end-capping compound at one end of said monomer, the end-capping compound preventing polymerization at the end, wherein the end-capping compound is not charge transporting and comprises at least two rings. The end capping compound preferably consists of or includes a structural unit having the formula: (Ar)n—X, wherein Ar in each occurrence independently represents an aryl or heteroaryl group; X represents a leaving group comprising a boron derivative group or halogen; and n is 2 or more.
    Type: Grant
    Filed: April 15, 2010
    Date of Patent: December 23, 2014
    Assignees: Cambridge Display Technology Limited, Sumitomo Chemical Company Limited
    Inventors: Mary McKiernan, Thomas Pounds
  • Patent number: 8822045
    Abstract: The present invention provides methods of protecting a surface of an aluminum nitride substrate. The substrate with the protected surface can be stored for a period of time and easily activated to be in a condition ready for thin film growth or other processing. In certain embodiments, the method of protecting the substrate surface comprises forming a passivating layer on at least a portion of the substrate surface by performing a wet etch, which can comprise the use of one or more organic compounds and one or more acids. The invention also provides aluminum nitride substrates having passivated surfaces.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: September 2, 2014
    Assignee: North Carolina State University
    Inventors: Ramon R. Collazo, Zlatko Sitar, Rafael Dalmau
  • Patent number: 8766107
    Abstract: Example multi-layer printed circuit boards (‘PCBs’) are described as well as methods of making and using such PCBs that include layers of laminate; at least one via hole traversing the layers of laminate, and a via conductor contained within the via hole, the via conductor comprising a used portion and an unused portion, the via conductor comprising copper coated with a metal having a conductivity lower than the conductivity of copper.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: July 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Moises Cases, Tae Hong Kim, Rohan U. Mandrekar, Nusrat I. Sherali
  • Publication number: 20140134454
    Abstract: A multi-layer composite precursor is provided comprising a substrate, wherein the substrate comprises a light emitting organic compound, a first surface, and a second surface, wherein the second surface is superimposed by a transparent electrically conducting layer, a liquid phase superimposing at least a part of the first surface comprising a metal-organic compound, wherein the metal-organic compound comprises an organic moiety, wherein the organic moiety comprises a C?O group; and wherein the liquid phase further comprises a first silicon compound, wherein the first silicon compound comprises at least one carbon atom and at least one nitrogen atom.
    Type: Application
    Filed: November 15, 2013
    Publication date: May 15, 2014
    Applicants: KOREA ELECTRONICS TECHNOLOGY INSTITUTE, HERAEUS PRECIOUS METALS GMBH & CO. KG
    Inventors: Herbert FUCHS, Hyung Seok HA, Kerstin TIMTER, Jeongno LEE, Bumjoo LEE, Chul Jong HAN, Seunghyun LEE
  • Patent number: 8658911
    Abstract: Example multi-layer printed circuit boards (‘PCBs’) are described as well as methods of making and using such PCBs that include layers of laminate; at least one via hole traversing the layers of laminate, and a via conductor contained within the via hole, the via conductor comprising a used portion and an unused portion, the via conductor comprising copper coated with a metal having a conductivity lower than the conductivity of copper.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: February 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Moises Cases, Tae Hong Kim, Rohan U. Mandrekar, Nusrat I. Sherali
  • Patent number: 8647485
    Abstract: Apparatus for processing substrates is disclosed herein. In some embodiments, an apparatus includes a first shield having a first end, a second end, and one or more first sidewalls disposed between the first and second ends, wherein the first end is configured to interface with a first support member of a process chamber to support the first shield in a position such that the one or more first sidewalls surround a first volume of the process chamber; and a second shield having a first end, a second end, and one or more second sidewalls disposed between the first and second ends of the second shield and about the first shield, wherein the first end of the second shield is configured to interface with a second support member of the process chamber to support the second shield such that the second shield contacts the first shield to form a seal therebetween.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: February 11, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Muhammad Rasheed, Donny Young, Kirankumar Savandaiah, Uday Pai
  • Patent number: 8618795
    Abstract: A sensor assembly is provided for use in tracking a medical device. The sensor assembly comprises a magnetoresistance sensor capable of providing position and orientation information. In certain implementations, the magnetoresistance position and orientation sensor is originally configured for connection to a substrate using one type of interconnect approach but is modified to be connected using a different interconnect approach.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: December 31, 2013
    Assignee: General Electric Company
    Inventors: Kaustubh Ravindra Nagarkar, William Hullinger Huber, Daniel Eduardo Groszmann
  • Patent number: 8614007
    Abstract: The present invention generally comprises a semiconductor film and the reactive sputtering process used to deposit the semiconductor film. The sputtering target may comprise pure zinc (i.e., 99.995 atomic percent or greater), which may be doped with aluminum (about 1 atomic percent to about 20 atomic percent) or other doping metals. The zinc target may be reactively sputtered by introducing nitrogen and oxygen to the chamber. The amount of nitrogen may be significantly greater than the amount of oxygen and argon gas. The amount of oxygen may be based upon a turning point of the film structure, the film transmittance, a DC voltage change, or the film conductivity based upon measurements obtained from deposition without the nitrogen containing gas. The reactive sputtering may occur at temperatures from about room temperature up to several hundred degrees Celsius. After deposition, the semiconductor film may be annealed to further improve the film mobility.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: December 24, 2013
    Assignee: Applied Materials, Inc.
    Inventor: Yan Ye
  • Patent number: 8580092
    Abstract: Embodiments of the invention generally provide a process kit for use in a physical deposition chamber (PVD) chamber. In one embodiment, the process kit provides adjustable process spacing, centering between the cover ring and the shield, and controlled gas flow between the cover ring and the shield contributing to uniform gas distribution, which promotes greater process uniformity and repeatability along with longer chamber component service life.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: November 12, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Lara Hawrylchak, Kirankumar Savandaiah
  • Patent number: 8518561
    Abstract: Nanoporous polymers with gyroid nanochannels can be fabricated from the self-assembly of degradable block copolymer, polystyrene-b-poly(L-lactide) (PS-PLLA), followed by the hydrolysis of PLLA blocks. A well-defined nanohybrid material with SiO2 gyroid nanostructure in a PS matrix can be obtained using the nanoporous PS as a template for the sol-gel reaction. After subsequent UV degradation of the PS matrix, a highly porous inorganic gyroid network remains, yielding a single-component material with an exceptionally low refractive index (as low as 1.1).
    Type: Grant
    Filed: January 13, 2011
    Date of Patent: August 27, 2013
    Assignee: National Tsing Hua University
    Inventors: Rong-Ming Ho, Han-Yu Hsueh, Ming-Shiuan She, Hung-Ying Chen, Shangjr Gwo
  • Publication number: 20130118775
    Abstract: The present invention relates to a method of forming copper nanowires with a metallic coating. In a preferred embodiment, the metallic coating is copper. Due to the metal coating, the nanowires become magnetically guidable and chemically stable. As such, the nanowires can be used to form nanomesh. Further, the nanowire and nanomesh of the present invention can be used as transparent electrodes that are used in TV, PC, touch-control, and solar industries.
    Type: Application
    Filed: July 19, 2011
    Publication date: May 16, 2013
    Applicant: NATIONAL UNIVERSITY OF SINGAPORE
    Inventors: Hua Chun Zeng, Shengmao Zhang, Yu Chang, Mei Ling Lye
  • Patent number: 8404359
    Abstract: A solder layer and an electronic device bonding substrate using the layer are provided which avoid deteriorating qualities of the electronic device to be bonded. In a solder layer 14 free from lead and formed on a substrate 11 or an electronic device bonding substrate 10 having such a solder layer, the solder layer 14 has a specific resistance of not more than 0.4 ?·?m. The electronic device bonding substrate 10 can have a thermal resistance of not more than 0.5 K/W and a thickness of not more than 10 ?m. Then, voids contained in the solder layer 14 have a maximum diameter of not more than 0.5 ?m and the substrate can be a submount substrate.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: March 26, 2013
    Assignee: Dowa Electronics Materials Co., Ltd.
    Inventors: Yoshikazu Oshika, Masayuki Nakano
  • Patent number: 8241421
    Abstract: The epitaxial layer defects generated from voids of a silicon substrate wafer containing added hydrogen are suppressed by a method for producing an epitaxial wafer by: growing a silicon crystal by the Czochralski method comprising adding hydrogen and nitrogen to a silicon melt and growing from the silicon melt a silicon crystal having a nitrogen concentration of from 3×1013 cm?3 to 3×1014 cm?3, preparing a silicon substrate by machining the silicon crystal, and forming an epitaxial layer at the surface of the silicon substrate.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: August 14, 2012
    Assignee: Siltronic AG
    Inventors: Katsuhiko Nakai, Timo Mueller, Atsushi Ikari, Wilfried von Ammon, Martin Weber
  • Patent number: 8222171
    Abstract: A method for the production of a ceramic substrate for a semiconductor component, includes the steps of producing paper containing at least cellulose fibers, as well as a filler to be carbonized and/or SiC, pyrolizing the produced paper, and siliconizing the pyrolyzed paper.
    Type: Grant
    Filed: July 13, 2007
    Date of Patent: July 17, 2012
    Assignee: Schunk Kohlenstofftechnik GmbH
    Inventors: Marco Ebert, Martin Henrich, Andreas Lauer, Gotthard Nauditt, Thorsten Scheibel, Roland Weiss
  • Patent number: 8182929
    Abstract: The present invention provides a solar absorptive material for a solar selective surface of an absorber of solar radiation. The solar absorptive material comprises a dispersed metallic material and a receiving boundary through which the solar radiation is received. Further, the solar absorptive material comprises a first region and a second region. The first region being located at a position closer to the receiving boundary than the second region and the first region has an average volume fraction of the dispersed metallic material that is larger than that of the second region.
    Type: Grant
    Filed: March 3, 2006
    Date of Patent: May 22, 2012
    Assignee: The University of Sydney
    Inventors: Yongbai Yin, Lingxia Hang, David Mills
  • Publication number: 20120107639
    Abstract: An electrical component is provided by a method comprising forming a middle plated layer made of palladium or a palladium alloy on a substrate and forming a surface plated layer made of tin or a tin alloy containing a metal other than palladium on the middle plated layer. Thus, there can be provided an electrical component having a surface layer consisting primarily of tin in which whisker formation can be prevented for a long period under stress.
    Type: Application
    Filed: April 30, 2010
    Publication date: May 3, 2012
    Applicant: OM SANGYO CO., LTD.
    Inventors: Masao Takamizawa, Toshihide Naka, Hitoshi Kemmotsu, Yoshiyuki Nishimura
  • Patent number: 8143164
    Abstract: Embodiments of the current invention describe methods of processing a semiconductor substrate that include applying a zincating solution to the semiconductor substrate to form a zinc passivation layer on the titanium-containing layer, the zincating solution comprising a zinc salt, FeCl3, and a pH adjuster.
    Type: Grant
    Filed: February 9, 2009
    Date of Patent: March 27, 2012
    Assignee: Intermolecular, Inc.
    Inventors: Bob Kong, Zhi-Wen Sun, Chi-I Lang, Jinhong Tong, Tony Chiang
  • Patent number: 8138303
    Abstract: The present invention relates to novel polymers comprising a repeating unit of the formula (I) and their use in electronic devices. The polymers according to the invention have excellent solubility in organic solvents and excellent film-forming properties. In addition, high charge carrier mobilities and high stability of the emission color can be observed, if the polymers according to the invention are used in organic light emitting diodes (OLEDs).
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: March 20, 2012
    Assignee: BASF SE
    Inventors: Natalia Chebotareva, Roger Prétôt, Paul Adriaan Van der Schaaf, Thomas Schäfer, Beat Schmidhalter, Peter Murer
  • Publication number: 20110171137
    Abstract: A process of preparing a plurality of nanostructures, each being composed of at least one target material is disclosed. The process comprises sequentially electrodepositing a first material and the at least one target material into pores of a porous membrane having a nanometric pore diameter, to thereby obtain within the pores nanometric rods, each of the nanometric rods having a plurality of segments where any two adjacent segments are made of different materials. The process further comprises and etching the membrane and the first material, thereby obtaining the nanostructures.
    Type: Application
    Filed: September 10, 2009
    Publication date: July 14, 2011
    Applicant: RAMOT AT TEL-AVIV UNIVERSITY LTD.
    Inventors: Fernando Patolsky, Roey Elnathan, Raisa Kantaev
  • Patent number: 7972683
    Abstract: A material for bonding a first wafer to a second wafer, which includes an insulating adhesive with conductive particles embedded in the adhesive substance. When the adhesive is applied and melted or fused, and pressure is applied between the first wafer and the second wafer, the first wafer approaches the second wafer until a minimum separation is reached, defined by a dimension of the conductive particles. Each of the first wafer and the second wafer may have circuitry formed thereon, and the conductive particles may form a conductive path between the circuitry on one wafer and the circuitry on the other wafer. Advantageously, the high fusing temperature required by the insulating adhesive may also serve to activate a getter material, formed in the device cavity between the first wafer and the second wafer.
    Type: Grant
    Filed: September 5, 2007
    Date of Patent: July 5, 2011
    Assignee: Innovative Micro Technology
    Inventors: Christopher S. Gudeman, Steven H. Hovey, Ian R. Johnston
  • Patent number: 7935430
    Abstract: A bonding structure and method of manufacturing the same are provided. The bonding structure of a substrate and a component include an electrode formed of metal powder and a resin component on the substrate. A low melting point solder that bonds the component to the electrode. The metal powder contains at least spherical metal powder and flake metal powder. The low melting point solder is infiltrated from the surface of the electrode into the electrode.
    Type: Grant
    Filed: October 26, 2006
    Date of Patent: May 3, 2011
    Assignee: Alps Electric Co., Ltd.
    Inventors: Hiroki Suzuki, Masato Uehara
  • Patent number: 7927713
    Abstract: The present invention generally comprises a semiconductor film and the reactive sputtering process used to deposit the semiconductor film. The sputtering target may comprise pure zinc (i.e., 99.995 atomic percent or greater), which may be doped with aluminum (about 1 atomic percent to about 20 atomic percent) or other doping metals. The zinc target may be reactively sputtered by introducing nitrogen and oxygen to the chamber. The amount of nitrogen may be significantly greater than the amount of oxygen and argon gas. The amount of oxygen may be based upon a turning point of the film structure, the film transmittance, a DC voltage change, or the film conductivity based upon measurements obtained from deposition without the nitrogen containing gas. The reactive sputtering may occur at temperatures from about room temperature up to several hundred degrees Celsius. After deposition, the semiconductor film may be annealed to further improve the film mobility.
    Type: Grant
    Filed: July 26, 2007
    Date of Patent: April 19, 2011
    Assignee: Applied Materials, Inc.
    Inventor: Yan Ye
  • Patent number: 7879455
    Abstract: The present invention intends to provide a power semiconductor device using a high-temperature lead-free solder material, the high-temperature lead-free solder material having the heat resistant property at 280° C. or more, and the bondability at 400° C. or less, and excellent in the suppliabilty and wettability of solder, and in the high-temperature storage reliability and the temperature cycle reliability. In the power semiconductor device according to the present invention, a semiconductor element and a metal electrode member were bonded each other by a high-temperature solder material comprising Sn, Sb, Ag, and Cu as the main constitutive elements and the rest of other unavoidable impurity elements wherein the high-temperature solder material comprises 42 wt %?Sb/(Sn+Sb)?48 wt %, 5 wt %?Ag<20 wt %, 3 wt %?Cu<10 wt %, and Ag+Cu?25 wt %.
    Type: Grant
    Filed: December 5, 2006
    Date of Patent: February 1, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Ryoichi Kajiwara, Kazutoshi Itou
  • Patent number: 7776993
    Abstract: A reworkable thermoset epoxy-containing material that allows for a reworkable assembly such as a reworkable waferlevel underfilled microelectronic package. A method for using the reworkable thermoset material in the formation of a microelectronic package using this material.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: August 17, 2010
    Assignee: International Business Machines Corporation
    Inventors: Stephen Leslie Buchwalter, Claudius Feger, Gareth Hougham, Nancy LaBianca, Hosadurga Shobha
  • Publication number: 20100203350
    Abstract: Methods and apparatuses are provided for casting silicon for photovoltaic cells and other applications. With these methods, an ingot can be grown that is low in carbon and whose crystal growth is controlled to increase the cross-sectional area of seeded material during casting.
    Type: Application
    Filed: July 16, 2008
    Publication date: August 12, 2010
    Applicant: BP CORPORATION NOTH AMERICA INC.
    Inventors: Nathan G. Stoddard, Roger F. Clark, James A. Cliber
  • Patent number: 7722962
    Abstract: A solder foil formed from a material comprising particles of Cu, etc. as metal particles and Sn particles as solder particles by rolling is suitable for solder bonding at a high temperature side in temperature-hierarchical bonding, and semiconductor devices and electronic devices produced by use of such solder bonding have distinguished reliability of mechanical characteristics, etc.
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: May 25, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Tasao Soga, Hanae Hata, Toshiharu Ishida, Kanko Ishida, legal representative, Tetsuya Nakatsuka, Masahide Okamoto, Kazuma Miura
  • Patent number: 7648775
    Abstract: A ceramic substrate comprising a metallic layer on its surface, wherein said metallic layer includes: a silver layer containing silver; a gold layer containing gold; and a nickel layer containing nickel, in this order from an outermost layer of said metallic layer.
    Type: Grant
    Filed: December 2, 2005
    Date of Patent: January 19, 2010
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Hisashi Wakako, Makoto Nagai, Atsushi Uchida, Masahito Morita, Kazuo Kimura