Abstract: A coating material used in the fabrication of electronic components such as a metallized paste is provided comprising a material to be coated on the electronic component substrate and an identifying component which identifying component can be identified and which identifying component identifies the coating material. Optical dyes visible to the eye can be used as the identifying component with a preferred dye being a UV fluorescent dye which is colorless under visible light and visible under UV light. A process for making an electronic component using the coating materials of the invention and electronic components made using the coating material are also provided.

Abstract: An epoxy resin comprising (A) an epoxy resin, (B) a curing agent and (C) a filler, in which the epoxy resin (A) contains a bisphenol F-type epoxy compound (a), the filler (C) contains spherical silica and the filler (C) accounts for from 88 to 96% by weight of the resin composition, has good soldering heat resistance enough for high-temperature solder reflow and has good moldability. A semiconductor device encapsulated with the resin composition is useful for use in electronic appliances.

Abstract: A square substrate has a pair of opposed major surfaces and peripheral end faces therebetween, wherein a tapered edge portion is disposed between the peripheral end face and each major surface to define an inner boundary with the major surface, and has a width of 0.2-1 mm from the peripheral end face. Both or either one of the major surfaces of the substrate has a flatness of up to 0.5 &mgr;m in an outside region of the substrate that extends between a position spaced 3 mm inward from the peripheral end face and the inner boundary of the tapered edge portion.

Abstract: An epoxy resin composition comprising an epoxy resin, a first curing agent for polymerizing the epoxy resin into a linear polymer, and a second curing agent for crosslinking the linear polymer into a three-dimensional polymer. The use of two curing agents corresponding to straight chain growth reaction and crosslinking reaction of the epoxy resin optimizes the reaction conditions to B-stage, giving a semi-cured film having a minimized variation. A laminate includes a layer of the epoxy resin composition and a protective layer. By sealing a semiconductor chip with the film, there is obtained a semiconductor package having improved heat resistance, improved moisture resistance, low stress property.

Abstract: The instant invention provides a means and method for producing multi-laminar elements, said elements being suitable for operation in high temperature, atmospheric or vacuum environments such as those which may be required when processing materials such as substrates for semiconductors or for chemical vapor deposition.

Abstract: A one-pack type epoxy resin composition is desclosed. The composition comprises a low-viscosity epoxy resin and an acid anhydride hardener, and has a viscosity of 250 P or less at 25° C. The hardener is an imide oligomer comprising an imide unit and having an acid anhydride group at the terminal thereof. The imide unit is represented by formula I: wherein A represents an asymmetric aromatic tetracarboxylic dianhydride residue or alicyclic tetracarboxylic dianhydride residue; and B represents a diaminopolysiloxane residue.

Abstract: An epoxy resin composition comprising (A) a polyfunctional epoxy resin, (B) a phenolic resin, (C) an inorganic filler, and (D) curing catalyst-containing microcapsules having a mean particle size of 0.5-50 &mgr;m is suited for semiconductor package encapsulation since it minimizes the warpage of packages and has satisfactory catalyst latency, storage stability and cure.

Abstract: A printed circuit board of the present invention is formed of an electrical insulating base material with through holes that are formed in a thickness direction of the electrical insulating base material and are filled with an electrical conductor; the electrical insulating base material including a core layer formed by impregnating a holder with a resin and resin layers formed on both sides of the core layer; and wiring layers that are formed on both surfaces of the electrical insulating base material into a predetermined pattern and are electrically connected to each other by the electrical conductor. The wiring layer is embedded in at least one of the resin layers. The resin layers on the both sides have different thicknesses from each other, and a thinner layer out of the resin layers has a thickness equal to or smaller than a mean particle diameter of an electrically conductive filler contained in the electrical conductor.

Abstract: Nitrogen compounds represented by formula (XXIa) or (XXIb); an epoxy resin hardening accelerator and a resin composition each containing any of the compounds; and an electronic part device containing an element encapsulated with the composition. In the formulae, R1 and R2 each represents hydrogen or a C1-20 monovalent organic group; R3 and R4 each represents a C1-20 divalnt organic group; R5 represents hydrogen or a C1-6 monovalent organic group; k is an integer of 0 to 2; and p is 0 or 1.

Abstract: A gold wire, for semiconductor element connection, having 5-100 ppm by weight of Ca, 5-100 ppm by weight of Gd, and 1-100 ppm by weight of Y. The gold wire further preferably has 1-100 ppm by weight of at least one of Eu, La, Ce and Lu, as well as 1-100 ppm by weight of at least one of Mg and Ti. The total amount of the added elements being no greater than 200 ppm by weight. The balance being gold and unavoidable impurities. A semiconductor element connection method by ball bonding or bump connection using the gold wire.

Abstract: An electronic circuit device comprising at least one substrate having a photoimageable covercoat, comprising at least 95 weight percent of at least one epoxy-modified aromatic vinyl-conjugated diene block copolymer and a catalyst comprising an onium salt selected from a triarylsulfonium salt and a diaryliodonium salt, wherein the covercoat is formed by solvent coating or extrusion and then heat laminated onto at least a portion of the substrate.

Abstract: Copper can be pattern etched at acceptable rates and with selectivity over adjacent materials using an etch process which utilizes a solely physical process which we have termed “enhanced physical bombardment”. Enhanced physical bombardment requires an increase in ion density and/or an increase in ion energy of ionized species which strike the substrate surface. To assist in the removal of excited copper atoms from the surface being etched, the power to the ion generation source and/or the substrate offset bias source may be pulsed. In addition, when the bombarding ions are supplied from a remote source, the supply of these ions may be pulsed. Further, thermal phoresis may be used by maintaining a substrate temperature which is higher than the temperature of a surface in the etch chamber.

Abstract: A practically realizable semiconductor magnetic body having a flat-band structure is disclosed. The semiconductor magnetic body is formed by semiconductor quantum dots arranged on lattice points such that electrons can transfer between neighboring quantum dots and the electron energy band contains a flat-band structure, where each quantum dot is a structure in which electrons are confined inside a region which is surrounded by high energy potential regions, and the flat-band structure is a band structure in which energy dispersion of electrons has hardly any wave number dependency.

Abstract: An organic antireflection coating is formed on a semiconductor substrate. A resist film is formed on the semiconductor substrate through the organic antireflection coating. The resist film is patterned for forming a resist pattern having an opening. A part of the organic antireflection coating exposed on the bottom of the opening of the resist pattern is removed with atomic oxygen. Thus provided is a method of forming a resist pattern so improved as to increase the dimensional accuracy of the resist pattern.

Abstract: A sealing material for flip chip-type semiconductor devices comprises a liquid epoxy resin composition which includes (A) a liquid epoxy resin, (B) an optional curing agent, (C) an inorganic filler, and (D) 1 to 15 parts by weight of a microencapsulated catalyst per 100 parts by weight of components A and B combined. The excellent thin-film penetration and shelf stability of the sealing material confer a very high reliability to flip chip-type semiconductor devices made using the sealing material.

Abstract: Multi-layer assemblies of polysilicon thin films having predetermined stress characteristics and techniques for forming such assemblies are disclosed. In particular, a multi-layer assembly of polysilicon thin films may be produced that has a stress level of zero, or substantially so. The multi-layer assemblies comprise at least one constituent thin film having a tensile stress and at least one constituent thin film having a compressive stress. The thin films forming the multi-layer assemblies may be disposed immediately adjacent to one another without the use of intermediate layers between the thin films. Multi-layer assemblies exhibiting selectively determinable overall bending moments are also disclosed. Selective production of overall bending moments in microstructures enables manufacture of such structures with a wide array of geometrical configurations.

Abstract: It is the object of the present invention to provide not only a semiconductor wafer obtained by forming a semiconductor thin film with uniform resistivity and substantially no slip dislocation on a main surface of a semiconductor single crystal substrate having a relatively low dopant concentration, as large as 300 mm or more in diameter but also a vapor phase growth apparatus by means of which such a semiconductor wafer can be produced. A dopant gas is supplied into a reaction chamber 10 through all of the inlet ports 18a to 18f disposed in a width direction of the reaction chamber 10 from a common gas pipe 22a functioning as a main dopant gas pipe. Further, the dopant gas is additionally supplied through inner inlet ports 18a and 18b, and middle inlet ports 18c and 18d, as specific gas inlet ports, into the reaction chamber 10 from first and second auxiliary dopant gas pipes 22b and 22c.

Abstract: This invention relates to fluxing underfill compositions useful for fluxing metal surfaces in preparation for providing an electrical connection and sealing the space between semiconductor devices, such as chip size or chip scale packages (“CSPs”), ball grid arrays (“BGAs”), land grid arrays (“LGAs”), flip chip assemblies (“FCs”) and the like, each of which having a semiconductor chip, such as large scale integration (“LSI”), or semiconductor chips themselves and a circuit board to which the devices or chips, respectively, are electrically interconnected. The inventive fluxing underfill composition begins to cure at about the same temperature that solder used to establish the electrical interconnection melts.

Abstract: Method for controlling the morphology and impeding electromigration of sputtered copper films and semiconductor wafers produced thereby. Copper may be deposited onto a seed layer or wetting layer of a dopant metal by PVD at an elevated temperature relative to the temperature at which the seed layer is deposited. Copper may also be deposited in a two step PVD process whereby a first copper layer is deposited at a lower temperature relative to a second copper layer. The resulting film has a smooth surface and no voids.

Abstract: A shield for attenuating the strength and density of electromagnetic radiation emitted by electronic components includes two parallel conductors separated by an insulator. The shields are installed on the surface of electronic components by an adhesive.

Abstract: A surface treated metallic material according to the present invention comprises a metallic substrate and a metallic compound layer formed thereon, wherein the entire surface of the metallic compound layer is covered with minute, upright, scaly protrusions. The width in the major axial direction of the scaly protrusions is between 0.05˜0.5 &mgr;m and the thickness between 0.01˜0.1 &mgr;m, and the thickness of the metallic compound layer is between 0.1˜1.0 &mgr;m. The metallic compound layer incorporates one, or two or more of, the materials selected from the group consisting of chromium oxide, chromium hydroxide, niobium oxide, niobium hydroxide, rhodium oxide, rhodium hydroxide, vanadium oxide, vanadium hydroxide, palladium oxide, palladium hydroxide, nickel oxide, and nickel hydroxide. By using surface treated metallic materials of this type, bonding strength to a resin layer can be improved.

Abstract: A nitride-based semiconductor element enabling formation of a nitride-based semiconductor layer having low dislocation density, consisting of a material different from that of an underlayer, on the underlayer with a small thickness is obtained. This nitride-based semiconductor element comprises a plurality of mask layers formed at a prescribed interval to be in contact with the upper surface of the underlayer while partially exposing the underlayer and the nitride-based semiconductor layer, formed on the upper surface of the underlayer and the mask layers, consisting of the material different from that of the underlayer. The minimum distance between adjacent mask layers is smaller than the width of an exposed part of the underlayer located between the adjacent mask layers.

Abstract: An electronic circuit device comprising at least one substrate having a photoimageable covercoat, comprising at least 95 weight percent of at least one epoxy-modified aromatic vinyl-conjugated diene block copolymer and a catalyst comprising an onium salt selected from a triarylsulfonium salt and a diaryliodonium salt, wherein the covercoat is formed by solvent coating or extrusion and then heat laminated onto at least a portion of the substrate.

Abstract: A semiconductor ceramic device comprises a body composed of a semiconductor ceramic having a positive resistance-temperature coefficient primarily composed of barium titanate and electrodes provided on the body, in which the resistance-temperature coefficient is 9%/° C. or more, resistivity is 3.5 ∩·cm or less, and withstand voltage is 50 V/mm or more. As the semiconductor ceramic forming the body provided in a thermistor having positive resistance-temperature characteristics, a semiconductor ceramic having a positive resistance-temperature coefficient is used, in which the semiconductor ceramic has an average particle diameter of about 7 to 12 &mgr;m and comprises barium titanate as a major component and sodium in an amount of about 70 ppm or less on a weight basis.

Abstract: This invention provides a Group III-V compound semiconductor that is free from the limitation of the shape and the size, is economical, is excellent in photo-electric characteristics (photo-electric conductivity photo-electromotive current, photo-electromotive force, quantum efficiency), can freely select the optical gap over a broad range, has high performance as a photo-semiconductor, has limited change with time, and is excellent in response, environmental resistance characteristics and high temperature resistance. The Group III-V compound semiconductor contains a Group III element and a Group V element of the Periodic Table as principal components, and contains also 0.1 atom % to 40 atom % of hydrogen atoms and 100 ppm to 20 atom %, based on the sum of the atomic numbers of the Group III element and the Group V element, of at least one element selected from among Be, Mg, Ca, Zn and Sr.

Abstract: Semiconductor encapsulating epoxy resin compositions comprising an epoxy resin, a phenolic resin curing agent, a fire retardant comprising zinc molybdate carried on spherical silica having a mean particle diameter of 0.2-20 &mgr;m and a specific surface of 1-20 m2/g, and an inorganic filler are able to provide cured products having excellent fire retardance. The compositions have good flow and curing properties and excellent reliability and do not pose a hazard to human health or the environment.

Abstract: Provided is a method of manufacturing a semiconductor device with which it is able to individually adjust the effect of reducing the overlap capacity between a gate electrode and extensions. Specifically, a stacked structure made up of a polysilicon film (3, 9), tungsten silicide film (4, 10) and silicon nitride film (5, 11) is partially formed in first and second regions of a silicon substrate (1), respectively. Sidewall oxide films (20, 21) are formed on the side surfaces of the polysilicon films (3, 9) in the first and second regions, respectively. After removing the sidewall oxide film (20) in the first region, extensions (14) are formed in the first region. A sidewall oxide film (6) is formed on the side surface of the polysilicon film (3) in the first region, and the width of the sidewall oxide film (21) in the second region is increased to form a sidewall oxide film (12). Extensions (16) are formed in the second region.

Abstract: The present invention provides a ceramic circuit board comprising: a ceramic substrate and a metal circuit plate bonded to the ceramic substrate through a brazing material layer; wherein the brazing material layer is composed of Al—Si group brazing material and an amount of Si contained in the brazing material is 7 wt % or less. In addition, it is preferable to form a thinned portion, holes, or grooves to outer peripheral portion of the metal circuit plate. According to the above structure of the present invention, there can be provided a ceramic circuit board having both high bonding strength and high heat-cycle resistance, and capable of increasing an operating reliability as electronic device.

Abstract: A method of fabricating a semiconductor device having a Cu—Ca—O thin film formed on a Cu surface by immersing the Cu surface into a unique chemical (electroless plating) solution containing salts of calcium (Ca) and copper (Cu), their complexing agents, a reducing agent, a pH adjuster, and surfactants; and a semiconductor device thereby formed for improving Cu interconnect reliability, electromigration resistance, and corrosion resistance. The method controls the parameters of pH, temperature, and time in order to form a uniform conformal Cu-rich Cu—Ca—O thin film, possibly containing carbon (C) and/or sulphur (S), for reducing -electromigration in Cu interconnect lines by decreasing the drift velocity therein which decreases the Cu migration rate in addition to decreasing the void formation rate.

Abstract: A semiconductor-on-insulator (SOI) device includes a buried insulator layer and an overlying semiconductor layer. At least parts of the buried insulator layer include a nitrided semiconductor oxide. The nitrided semiconductor oxide may be formed by means of a nitride implant with sufficient energy to pass through a surface semiconductor layer and penetrate into a buried oxide layer. Following the nitride implant the device may be annealed to remove damage to the surface semiconductor layer, as well as to form a high quality nitrided oxide in the buried insulator layer. The nitrided semiconductor oxide material may reduce or prevent depletion of dopant material from portions of the surface semiconductor layer, such as from channel portions of NMOS transistors.

Abstract: A compliant substrate for the formation of semiconductor devices includes a crystalline base layer and a thin-film crystalline layer on and loosely bonded to the base layers. The thin-film layer has a high degree of lattice flexibility. A compliant substrate for formation of semiconductor devices may also include a crystalline base layer, and, on the base layer, a thin film layer having a lattice constant different from the lattice constant of the base layer. A method for formation of a compliant substrate for formation of semiconductor devices includes forming a thin film layer on a first substrate, bonding a first surface of the thin film layer to a surface of a second substrate having a lattice constant different from the lattice constant of the thin film layer either with or without twist bonding, and removing the first substrate to expose a second surface of the thin film layer.

Abstract: A method for forming an epitaxial layer involves depositing a buffer layer on a substrate by a first deposition process, followed by deposition of an epitaxial layer by a second deposition process. By using such a dual process, the first and second deposition processes can be optimized, with respect to performance, growth rate, and cost, for different materials of each layer. A semiconductor heterostructure prepared by a dual deposition process includes a buffer layer formed on a substrate by MOCVD, and an epitaxial layer formed on the buffer layer, the epitaxial layer deposited by hydride vapor-phase deposition.

Abstract: The present invention provides a multi-component multi-phase type polymeric shaped material in which a plurality of hole- or electron-conducting phases constitute a three-dimensional bicontinuous nano phase separation structure, and a functional device using the same. Such a functional device is quick in response and good in durability. The present invention also relates to a functional device comprising a laminated structure composed of a plurality of layers laminated, and at least one pair of electrodes that penetrate the interface between two layers laminated.

Abstract: A Cu plated ceramic substrate is used in a semiconductor. On a ceramic substrate layer, a thin-film Cr layer is put, and a thin-firm Au layer is put on the Cr layer. The Au layer is plated with Cu. By providing the Au and Cr layers between the ceramic plate and Cu layer, adhesibility is increased. A Pertier element which includes the Cu plated ceramic layer is employed in a semiconductor to absorb and generate heat efficiently.

Abstract: A semiconductor wafer having copper bondpads (17) that are free of voids (13) and a method for coating the copper bondpads (17) with solderable or wirebondable metals such that the copper bondpads (17) are free of the voids (13). The void free metal coatings are achieved using a dual activation process. In a first activation step (27), the copper bondpads (17) are activated by placing them in a palladium bath. In a second activation step (28), the bondpads are placed in a nickel—boron bath. After the dual activation, the copper bondpads (17) are coated with a layer of nickel—phosphorous or palladium. The nickel—phosphorous or palladium layer may be coated with a layer of gold for subsequent formation of solder balls or wirebonds thereon.

Abstract: A layer of a metal is electroplated onto an electrically conducting substrate having a generally smooth surface with a small recess therein, having a transverse dimension not greater than about 350 micrometers, typically from about 5 micrometers to about 350 micrometers, by immersing the substrate and a counterelectrode in an electroplating bath of the metal to be electroplated and passing a modulated reversing electric current between the electrodes. The current contains pulses that are cathodic with respect to said substrate and pulses that are anodic with respect to said substrate. The cathodic pulses typically have a duty cycle less than about 50% and the anodic pulses have a duty cycle greater than about 50%, the charge transfer ratio of the cathodic pulses to the anodic pulses is greater than one, and the frequency of the pulses ranges from about 10 Hertz to about 12000 Hertz. The on-time of the cathodic pulses may range from about 0.83 microseconds to about 50 milliseconds.

Abstract: The object of the present invention is to provide an epoxy resin compositions for encapsulating of semiconductors containing no bromine compounds and no antimony oxide and excellent in flame retardancy, moisture resistance, moldability, curability and electric characteristics. This composition is an epoxy resin composition containing (A) an epoxy resin, (B) a phenolic resin, (C) a curing accelerator, (D) an inorganic filler and (E) a red phosphorus-based flame retardant, wherein the improvement comprises the red phosphorus-based flame retardant (E) having a total content of phosphate ion and phosphite ion extracted from the retardant when subjected to extraction with water at 80° C. for 20 hours is not more than 2000 ppm, the amount of the red phosphorus in the red phosphorus-based retardant being 20-40% by weight and the red phosphorus-based retardant being contained in an amount of 0.5-5% by weight in the whole resin composition.

Abstract: The present invention provides an Al alloy thin film for a semiconductor device electrode having an electrical resistivity of as low as 6 &mgr;&OHgr;cm or less, high hillock resistance, high void resistance, and high corrosion resistance against an alkaline solution, which are required for an electrode thin film of large-screen liquid crystal display (LCD) or high-resolution LCD. The present invention also provides a sputtering target to deposit the Al alloy film by sputtering process for a semiconductor device electrode. The Al alloy thin film for a semiconductor device electrode satisfies the conditions of Y≧0.3 at %, IVa group metal element≧0.2 at %, and 0.3Cy+3CIVa≦2 (wherein Cy: Y content (at %), CIVa: content of IVa group metal element (at %)), and the sputtering target is made of an Al alloy satisfying the above conditions.

Abstract: An epoxy resin composition comprising an epoxy resin containing 0-10% by weight of a 2-nucleus compound and 50-100% by weight of 3 to 5-nucleus compounds combined and having a dispersity (Mw/Mn) of up to 1.7, an inorganic filler, a curing catalyst, a thermoplastic resin, and an optional phenolic resin and having a Tg of lower than 15° C. in an uncured state is effective in forming a flexible film which is easy to work at room temperature. Owing to the thermoplastic resin added, the composition avoids the problem that when a semiconductor chip is sealed with an uncured film of the composition, the film will lose its original shape or entrapped voids will be formed near the chip.

Abstract: An epoxy resin composition for encapsulating a semiconductor device comprising as essential components (A) an epoxy resin; (B) a phenolic resin; (C) a curing accelerator; and (D) a hollow inorganic filler having an average particle size of 4 to 100 &mgr;m and an average shell thickness of 1.5 &mgr;m or more, wherein the amounts of the component (A) and the component (B) are adjusted such that a total amount of X and Y (X+Y) is 350 or more, wherein X is an epoxy equivalent of the epoxy resin (A), and Y is a hydroxyl group equivalent of the phenolic resin (B); and a semiconductor device comprising a semiconductor element encapsulated by the epoxy resin composition.

Abstract: The present invention provides an epoxy resin composition having excellent moldability, flame retardancy and soldering resistance and low in water absorption. More specifically, it provides an epoxy resin composition for semiconductor encapsulation comprising (A) an epoxy resin in which the proportion of the carbon atoms of aromatic derivation to the whole carbon atoms in the epoxy resin is 70% or more, (B) a phenol resin in which the proportion of the carbon atoms of aromatic derivation to the whole carbon atoms in the phenol resin is 70% or more and whose phenolic hydroxy equivalent is 140 to 300, (C) a curing accelerator, and (D) an inorganic filler whose content W (wt %) in the whole epoxy resin composition satisfies 88≦W≦94, characterized in that the combustion starting temperature in thermogravimetric analysis of the cured epoxy resin composition in the air atmosphere is 280° C. or higher, or the retention A (wt %) of the cured product in said TG analysis satisfies W+[0.

Abstract: A composition comprising (A) 100 parts of a liquid epoxy resin, (B) 100-300 parts of a spherical inorganic filler having a maximum particle size of up to 50 &mgr;m and a mean particle size of 0.5-10 &mgr;m, (C) 0.1-6 parts of a reactive functional group-containing silicone compound, and (D) 0.01-10 parts of a curing accelerator is suitable as an underfill material for flip-chip type semiconductor devices. The composition has improved thin film infiltration and eliminates voids and other defects.

Abstract: In the present invention, provided are i) an encapsulant epoxy resin composition comprising an epoxy resin, a curing agent, a non-conductive carbon and an inorganic filler, and ii) an electronic device having an encapsulating member comprising a cured product of this composition.

Abstract: The invention concerns an electrochromic glazing system, with an electrochromic pane unit and at least one other pane, which are joined to one another in the edge area by means of a spacer frame, forming an interspace, and with a temperature sensor for detection of the temperature of the electrochromic pane unit. To optimize its location, according to the invention the temperature sensor is arranged in the region of the spacer frame, between the electrochromic pane unit and the other pane. The invention takes advantage of the fact that the spacer frame area represents a thermal bridge between the panes of a double-glazing unit which is especially suitable for the arrangement of a temperature sensor.

Abstract: A copper-plating electrolyte includes an aqueous copper salt solution, a water-soluble &bgr;-naphtholethoxylate compound having the formula 1

Abstract: A method is provided in which intermediate sized structures can be filled without forming voids during the fill process. The methods involve use of a sequence of CVD/PVD/CVD/PVD steps. The methods are especially effective for filling “intermediate” size features in damascene and dual damascene structures.

Abstract: A sealed semiconductor chip having a surface film of a sealed resin composition, wherein the resin composition has a linear expansion coefficient of 60×10−6/K or less at a temperature equal to or less than its glass transition point and 140×10−6/K or less at a temperature equal to or higher than its glass transition point; a semiconductor-sealing resin composition for sealing a semiconductor chip, which has a linear expansion coefficient of 60×10−6/K or less at a temperature equal to or less than its glass transition point and 140×10−6/K or less at a temperature equal to or higher than its glass transition point; the sealed semiconductor chip is chip size and has high reliability; the semiconductor-sealing resin composition creates a good seal on chip wafers and has high reliability; and the chip wafers sealed with a surface film of the resin composition warp little.

Abstract: The present invention provides a coating film, which is not likely to cause cracks on the coated surface and is also capable of improving the resistance of the coated surface, especially oxidation resistance, corrosion resistance, and gas permeation resistance, a member provided with the coating film, and a method for producing the coating film. In the coating film of the present invention, a dense layer containing silicon dioxide as a principal component, which is obtained by heat-treating a solution containing perhydropolysilazane and polyorganosilazane, a ratio of the content of perhydropolysilazane to the total amount of polysilazane including perhydropolysilazane and polyorganosilazane being from 0.65 to 0.95, in air or air containing water vapor, was formed on the surface of a stainless steel plate.

Abstract: There is provided a resin composition having high flame retardancy, which improves high temperature storage of an epoxy resin composition comprising an epoxy resin having biphenyl structure without a halogenated flame retardant and an antimony compound as a conventional flame retardant. High temperature storage was improved, a glass transition temperature (Tg) became not less than 150° C. and V-0 class in flame retardance standard (UL94) was accomplished by employing (1) an epoxy resin having biphenyl structure mainly as an epoxy resin, (2) a phenolic aralkyl resin mainly as a curing agent, (3) 0.5 to 30 parts by weight of a polyimide resin as an additive based on total 100 parts by weight of the epoxy resin and the curing agent, (4) a polysiloxane compound modified with polyether containing an amino group as a flame retardant, (5) not less than 87% by weight of a fused silica as an inorganic filler based on the total composition.

Abstract: A sol-gel catalyst composition for electroless plating includes a metal alkoxide in a polar organic solvent, an acid, a chloride salt or acid chloride, and a catalytic metallic salt. The sol-gel catalyst adheres to smooth surfaces without the preconditioning normally associated with other sol-gel smooth surface catalyst, as well as a method for coating a substrate with the sol-gel catalyst composition, and then a metallic platting solution.