Abstract: A bonding structure and method of manufacturing the same are provided. The bonding structure of a substrate and a component include an electrode formed of metal powder and a resin component on the substrate. A low melting point solder that bonds the component to the electrode. The metal powder contains at least spherical metal powder and flake metal powder. The low melting point solder is infiltrated from the surface of the electrode into the electrode.

Abstract: The present invention generally comprises a semiconductor film and the reactive sputtering process used to deposit the semiconductor film. The sputtering target may comprise pure zinc (i.e., 99.995 atomic percent or greater), which may be doped with aluminum (about 1 atomic percent to about 20 atomic percent) or other doping metals. The zinc target may be reactively sputtered by introducing nitrogen and oxygen to the chamber. The amount of nitrogen may be significantly greater than the amount of oxygen and argon gas. The amount of oxygen may be based upon a turning point of the film structure, the film transmittance, a DC voltage change, or the film conductivity based upon measurements obtained from deposition without the nitrogen containing gas. The reactive sputtering may occur at temperatures from about room temperature up to several hundred degrees Celsius. After deposition, the semiconductor film may be annealed to further improve the film mobility.

Abstract: The present invention intends to provide a power semiconductor device using a high-temperature lead-free solder material, the high-temperature lead-free solder material having the heat resistant property at 280° C. or more, and the bondability at 400° C. or less, and excellent in the suppliabilty and wettability of solder, and in the high-temperature storage reliability and the temperature cycle reliability. In the power semiconductor device according to the present invention, a semiconductor element and a metal electrode member were bonded each other by a high-temperature solder material comprising Sn, Sb, Ag, and Cu as the main constitutive elements and the rest of other unavoidable impurity elements wherein the high-temperature solder material comprises 42 wt %?Sb/(Sn+Sb)?48 wt %, 5 wt %?Ag<20 wt %, 3 wt %?Cu<10 wt %, and Ag+Cu?25 wt %.

Abstract: A reworkable thermoset epoxy-containing material that allows for a reworkable assembly such as a reworkable waferlevel underfilled microelectronic package. A method for using the reworkable thermoset material in the formation of a microelectronic package using this material.

Abstract: Methods and apparatuses are provided for casting silicon for photovoltaic cells and other applications. With these methods, an ingot can be grown that is low in carbon and whose crystal growth is controlled to increase the cross-sectional area of seeded material during casting.

Abstract: A solder foil formed from a material comprising particles of Cu, etc. as metal particles and Sn particles as solder particles by rolling is suitable for solder bonding at a high temperature side in temperature-hierarchical bonding, and semiconductor devices and electronic devices produced by use of such solder bonding have distinguished reliability of mechanical characteristics, etc.

Abstract: A ceramic substrate comprising a metallic layer on its surface, wherein said metallic layer includes: a silver layer containing silver; a gold layer containing gold; and a nickel layer containing nickel, in this order from an outermost layer of said metallic layer.

Abstract: Provided is a spin coating apparatus having a ring-shaped or polygonal auxiliary member for use in manufacture of a coated substrate via spin coating, wherein the auxiliary member is positioned adjacent to the side of a substrate for coating, within a range of a spaced distance of 0.03 to 0.8 mm and a range of a height deviation of less than 0.1 mm, upon mounting the substrate. When a surface of a substrate for coating is spin coated with a coating agent using the apparatus of the present invention, it is possible to eliminate or effectively reduce a ski-jump phenomenon at end portions of a coated substrate occurring when spin coating is performed, thereby resulting in uniform coating of a coating solution on the substrate, and it is also possible to effectively decrease contamination of the substrate for coating due to inflow or stay of the remaining coating agent.

Abstract: A process for growth of boron-based nanostructures, such as nanotubes and nanowires, with a controlled diameter and with controlled chemical (such as composition, doping) as well as physical (such as electrical and superconducting) properties is described. The boron nanostructures are grown on a metal-substituted MCM-41 template with pores having a uniform pore diameter of less than approximately 4 nm, and can be doped with a Group Ia or Group IIa electron donor element during or after growth of the nanostructure. Preliminary data based on magnetic susceptibility measurements suggest that Mg-doped boron nanotubes have a superconducting transition temperature on the order of 100 K.

Abstract: A method for dynamically varying a threshold voltage of a complimentary metal oxide semiconductor (CMOS) includes providing a substrate pickup formed a semiconductor material type which is complimentary to the semiconductor material type of a well thereof, so as to define a diode. The diode is at least partially turned on, so as to increase the potential of a substrate of the complimentary metal oxide semiconductor and thus reduce the turn-on threshold voltage thereof. The turn-off threshold voltage is approximately unchanged.

Abstract: A bonding pad structure for a semiconductor device includes a first lower metal layer beneath a second upper metal layer in a bonding region of the device. The lower metal layer is formed such that the metal of the lower metal layer is absent from the bonding region. As a result, if damage occurs to the structure during procedures such as probing or bonding at the bonding region, the lower metal is not exposed to the environment. Oxidation of the lower metal layer by exposure to the environment is prevented, thus improving reliability of the device.

Abstract: Provided is a flexible film which includes a dielectric film, a metal layer formed on the dielectric film, circuit patterns formed on the metal layer, and a tin-based bonding layer formed on the circuit patterns. Thus, it is possible to improve the reliability, thermal resistance, and dimension stability of a flexible film and enhance the adhesion between circuit patterns and an integrated circuit (IC) of a flexible film and between circuit patterns and circuit electrodes of a display device.

Abstract: A composite material is a Mo—Cu based composite material having a Cu content of 30 to 70 weight % and containing a copper pool phase and an Mo—Cu based composite phase. The copper pool phase is contained in an amount of 10-50 weight %. A heat-sink member uses the composite material.

Abstract: Disclosed herein is a graded core/shell semiconductor nanorod having at least a first segment of a core of a Group II-VI, Group III-V or a Group IV semiconductor, a graded shell overlying the core, wherein the graded shell comprises at least two monolayers, wherein the at least two monolayers each independently comprise a Group II-VI, Group III-V or a Group IV semiconductor.

Abstract: Disclosed herein is a gradient thin film, formed on a substrate by simultaneously depositing different materials on the substrate using a plurality of thin film deposition apparatuses provided in a vacuum chamber, wherein the gradient thin film is formed such that the composition thereof is continuously changed depending on the thickness thereof by deposition control plates provided in the path through which the different materials move to the substrate. The gradient thin film is advantageous in that the thin film is formed by simultaneously depositing different materials using various deposition apparatuses, so that the composition thereof is continuously changed depending on the thickness thereof, with the result that the physical properties of a thin film are easily controlled and the number of deposition processes is decreased, and thus processing time and manufacturing costs are decreased, thereby improving economic efficiency.

Abstract: A laminated sheet for adhering to a circuit side of a projected electrode-mounting wafer in a step of grinding a backside of the wafer, wherein the laminated sheet comprises at least a layer (layer A) contacting with the circuit side, made of a thermosetting resin, a layer (layer B) directly laminated on the layer A, made of a thermoplastic resin having a tensile modulus of from 1 to 300 MPa at 40° to 80° C., and an outermost layer (layer C) made of a thermoplastic resin which is non-plastic at a temperature of at least 25° C.; A method for manufacturing a semiconductor device, comprising the steps of grinding a backside of a projected electrode-mounting wafer wherein the laminated sheet is adhered to a circuit side of the wafer, removing other layers besides the layer A of the laminated sheet, and cutting the wafer into individual chips; and a semiconductor device obtainable by the method.

Abstract: A circuit system comprising: forming a lower electrode over a substrate; forming a resistive film over the lower electrode; forming a multi-layered insulating stack over a portion of the resistive film; and forming an upper electrode over a portion of the multi-layered insulating stack.

Abstract: A pretreatment composition of: (a) at least one compound having structure VI V1—Y—V2??VI in which each of Y, V1, and V2 is defined in the specification; (b) at least one organic solvent, and optionally, (c) at least one adhesion promoter; in which the amount of the compound of Structure VI present in the composition is effective to inhibit residue from forming when the photosensitive composition is coated on a substrate and the coated substrate is processed to form an image thereon.

Abstract: A method for depositing a solid film of ZnO onto a substrate from a reagent solution includes a reservoir of reagent solution maintained at a sufficiently low temperature to inhibit homogeneous reactions within the reagent solution. The reagent solution contains a source of Zn, a source of O, and multiple ligands to further control solution stability and shelf life. The chilled solution is dispensed through a showerhead onto a substrate. The substrate is positioned in a holder that has a raised structure peripheral to the substrate to retain or impound a controlled volume (or depth) of reagent solution over the exposed surface of the substrate. The reagent solution is periodically or continuously replenished from the showerhead so that only the part of the solution directly adjacent to the substrate is heated. A heater is disposed beneath the substrate and maintains the substrate at an elevated temperature at which the deposition of a desired solid phase from the reagent solution may be initiated.

Abstract: A BOAC/COA of a semiconductor device is manufactured by forming a conductive pad over a semiconductor device, forming a passivation oxide film over the semiconductor device including the conductive pad, forming an oxide film over the entire surface of the conductive pad and the passivation oxide film, forming an oxide film pattern defining a bond pad region on the conductive pad, sequentially forming a barrier film and a metal seed layer over the oxide film pattern, the passivation oxide film and the conductive pad, forming a metal layer over the metal seed layer, planarizing the metal layer exposing the oxide film pattern and portions of the barrier film and the metal seed layer, and removing the oxide film pattern by an etching process.

Abstract: A circuit assembly comprises two or more circuit laminates, each comprising a conductive metal layer disposed on a poly(arylene ether ketone) substrate layer, wherein at least one of the conductive metal layers has been patterned to form a circuit, and a bond ply layer comprising a thermoplastic or thermosetting material. The thermoplastic bond ply has a melting point between 250° C. and 370° C., a decomposition temperature greater than about 290° C. and a dissipation factor of less than 0.01 at 10 GHz. The thermoset bond ply has a dissipation factor less than 0.01 at 10 GHz and a decomposition temperature greater than about 290° C. after lamination. Methods of forming the above circuit assemblies are also disclosed.

Abstract: In a piezoelectric element having a substrate, a lower electrode layered on the substrate, a piezoelectric body made of ceramic layered on top of the lower electrode and an upper electrode layered on the piezoelectric body, wherein a first metal layer is provided between the substrate and the lower electrode, a second metal layer is provided between the lower electrode and the piezoelectric body, and the first metal layer and the second metal layer are made of a metal selected from among metals of which the ionization tendency is not less than that of Cu, oxides of metals of which the ionization tendency is not less than that of Cu, and alloys of metals of which the ionization tendency is not less than that of Cu.

Abstract: A method for forming a semiconductor device is provided including processing a wafer having a first layer and a second layer, the second layer is over the first layer, forming a vertical post from a sidewall spacer formed from the second layer, forming a filler over the first layer and surrounding the vertical post, and forming a device layer having a hole by removing the vertical post in the filler.

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include heating a substrate comprising a patterned metallic region to about 145 C or below in a reaction space, introducing an aluminum co-reactant into the reaction space, wherein an aluminum material is formed on the patterned metallic region, but not on non-metallic regions.

Abstract: A semiconductor device includes a semiconductor material having two crystal orientations. The semiconductor material forms an active area of the device. A device channel is formed on the two crystal orientations, which include a first region formed in a first crystal orientation surface of the semiconductor material, and a second region formed in a second crystal orientation surface of the semiconductor material wherein the first crystal orientation surface forms an angle with the second crystal orientation surface and the device channel covers at least an intersection of the angle.

Abstract: Methods of manufacturing a semiconductor device, a method of manufacturing a memory cell, a semiconductor device, a semiconductor processing device, and a memory cell, are provided. In one embodiment a method of manufacturing a semiconductor device is provided including forming a metal doped chalcogenide layer using light irradiation at least partially during provision of the metal.

Abstract: A layer sequence (400), comprising an aluminium layer (300), a nickel layer (301), and a nickel layer protection layer (302; 701). The aluminium layer (300) is formable on a substrate (200), the nickel layer (301) is formed on the aluminium layer (300), and the nickel layer protection layer (302; 701) is formed on the nickel layer (301).

Abstract: A substrate for semiconductor and integrated circuit components including: a core plate containing a Group VIB metal from the periodic table of the elements and/or an anisotropic material, having a first major surface and a second major surface and a plurality of openings extending, at least partially, from the first major surface to the second major surface; and a Group IB metal from the periodic table of the elements or other high thermally conductive material filling at least a portion of the space encompassed by at least some of the openings; and optionally, a layer containing a Group IB metal from the periodic table or other high thermally conductive material disposed over at least a portion of the first major surface and at least a portion of the second major surface. The substrate can be used in electronic devices, which can also include one or more semiconductor components.

Abstract: A metal structure (100) for a contact pad of a semiconductor, which has interconnecting traces of a first copper layer (102). The substrate is protected by an insulating overcoat (104). The first copper layer of first thickness and first crystallite size is selectively exposed by a window (110) in the insulating overcoat. A second copper layer (105) of second thickness covers conformably the exposed first copper layer. The second layer is deposited by an electroless process and consists of a transition zone, adjoining the first layer and having copper crystallites of a second size, and a main zone having crystallites of the first size. The distance a void can migrate from the second layer is smaller than the combined thicknesses of the first and second layers. A nickel layer (106) is on the second copper layer, and a noble metal layer (107) is on the nickel layer.

Abstract: A low temperature cofired ceramic material mainly includes that mixed evenly with high thermal conductivity ceramic materials (AlN) and Borosilicate powder glass materials.

Abstract: One embodiment of the present invention provides a method for fabricating a high-quality metal substrate. During operation, the method involves cleaning a polished single-crystal substrate. A metal structure of a predetermined thickness is then formed on a polished surface of the single-crystal substrate. The method further involves removing the single-crystal substrate from the metal structure without damaging the metal structure to obtain the high-quality metal substrate, wherein one surface of the metal substrate is a high-quality metal surface which preserves the smoothness and flatness of the polished surface of the single-crystal substrate.

Abstract: A chemical vapor deposition (CVD) method for selectively depositing GeSb materials onto a surface of a substrate is provided in which a metal that is capable of forming an eutectic alloy with germanium is used to catalyze the growth of the GeSb materials. A structure is also provided that includes a GeSb material located on preselected regions of a substrate. In accordance with the present invention, the GeSb material is sandwiched between a lower metal layer used to catalyze the growth of the GeSb and an upper surface metal layer that forms during the growth of the GeSb material.

Abstract: A semiconductor nanocrystal heterostructure has a core of a first semiconductor material surrounded by an overcoating of a second semiconductor material. Upon excitation, one carrier can be substantially confined to the core and the other carrier can be substantially confined to the overcoating.

Abstract: There is provided a method of manufacturing a thin film, in which not only high crystallinity and surface flatness can be realized but also dopant doping can be performed at high concentration. The method includes a low temperature highly doped layer growing step of performing dopant doping while growing the thin film at a given first temperature; an annealing step of interrupting the growth of the thin film and annealing the thin film at a given second temperature higher than the first temperature; and a high temperature lowly doped layer growing step of growing the thin film at the second temperature.

Abstract: A semiconductor chip (1) is provided having an adhesion-promoting-layer-free three-layer metallization (2). The three-layer metallization (2) has an aluminum layer (4) applied directly on the semiconductor chip (1), a diffusion barrier layer (5) applied directly on the aluminum layer (4), and a solder layer (6) applied directly on the diffusion barrier layer (5). Ti, Ni, Pt or Cr is provided as the diffusion barrier layer (5) and a diffusion solder layer is provided as the solder layer (6). All three layers are applied by sputtering in a process sequence.

Abstract: An optical film which enables desired optical properties to be obtained easily, and enables the durability to be improved. A metal film 32 is formed on an inner major surface 12a of a glass substrate 12. A plurality of first island structures 33 is formed scattered as islands on an inner major surface 32a of the metal film 32. A plurality of second island structures 31 is formed scattered as islands on the inner major surface 12a of the substrate 12. At least one set of the plurality of first island structures 33 and the plurality of second island structures 31 are made of at least one selected from the group consisting of metals and metal oxides having a different standard electrode potential to a metal of the metal film 32.

Abstract: The present invention provides an apparatus and method for use in processing semiconductor workpieces. The new apparatus and method allows for the production of thinner workpieces that at the same time remain strong. Particularly, a chuck is provided that includes a body, a retainer removeably attached to the body and a seal forming member. When a workpiece is placed on the chuck body and the retainer is engaged to the body, a peripheral portion of the back side of the workpiece is covered by the retainer while an interior region of the back side of the workpiece is exposed. The exposed back side of the workpiece is then subjected to a wet chemical etching process to thin the workpiece and form a relatively thick rim comprised of semiconductor material at the periphery of the workpiece. The thick rim or hoop imparts strength to the otherwise fragile, thinned semiconductor workpiece.

Abstract: A substrate for embodying multi-package comprises an underlying layer has a polymer material containing a conductive filler and provided with a step-like groove divided into step part and bottom part; a coating layer formed over the underlying layer, the coating layer is formed so that it may define a metal-wire forming area on the step part and the bottom part of the step-like groove and the conductive filler in the metal-wire forming area is exposed; and a metal wire formed via a plating process using the exposed conductive filler in the metal-wire forming area defined by the coating layer as a seed layer.

Abstract: The invention relates to polymerizable charge transport compounds, their use as semiconductors or charge transport materials, in optical, electrooptical or electronic devices like for example organic field effect transistors (FET or OFET) for thin film transistor liquid crystal displays and integrated circuit devices such as RFID tags, electroluminescent devices in flat panel displays, and in plotovoltaic and sensor devices, and to a field effect transistor, light emitting device or ID tag comprising the polymerisable charge transport compounds.

Abstract: The invention relates to a process for the multi-stage production of diffusion-soldered joints for power components with semiconductor chips, the melting points of diffusion-soldering alloys and diffusion-soldered joints being staggered in such a manner that a first melting point of the first diffusion-soldering alloy is lower than a second melting point of the second diffusion-soldering alloy, and the second melting point being lower than a third melting point of a first diffusion-soldered joint of the first diffusion-soldering alloy.

Abstract: A first metal is plated onto a substrate comprising a second metal by immersing the substrate into a bath comprising a compound of the first metal and an organic diluent. The second metal is more electropositive than the first metal. The organic diluent has a boiling point higher than a eutectic point in a phase diagram of the first and second metals. The bath is operated above the eutectic point but below the melting point of the second metal. For example, bismuth is immersion plated onto lead-free tin-based solder balls, and subsequently redistributed by fluxless reflow. Plated structures are also provided.

Abstract: An insulating substrate board for a semiconductor of the present invention comprises a ceramic substrate board (2) and a metal alloy layer (3) consisting of aluminum formed on one surface portion of the ceramic substrate board (2), wherein the Vickers hardness of the metal alloy layer (3) is not less than 25 and not more than 40. The metal alloy layer (3) includes silicon of not less than 0.2% by weight and not more than 5% by weight. The ceramic substrate board (2) is made of a material selected from a group consisting of alumina. aluminum nitride, and silicon nitride.

Abstract: A lead frame having a structure that can discharge hydrogen adsorbed during deposition and can reduce a galvanic potential difference between plating layers and a method of manufacturing the same are provided. The method includes forming a Ni plating layer formed of Ni or a Ni alloy on a base metal layer formed of a metal, forming a Pd plating layer formed of Pd or an Pd alloy on the Ni plating layer, heat-treating the Ni plating layer and the Pd plating layer, and forming a protective plating layer on the heat-treated Pd plating layer.

Abstract: A poly(arylene ether) polymer includes polymer repeat units of the following structure: —(O—Ar1—O—Ar2)m—(O—Ar3—O—Ar4)n— where Ar1, Ar2, Ar3, and Ar4 are identical or different aryl radicals, m is 0.05 to 0.95, n is 1-m, and at least one of the aryl radicals is grafted to at least one hydroxyalkyl group, such as 2-undecanol. The polymer is especially useful in electrically conductive adhesives.

Abstract: Compound preforms are provided having a first region, including a porous ceramic and a second region including a porous or solid ceramic in which the two regions differ in composition. The compound preform is infiltrated with a liquid metal which is then solidified to form a metal matrix composite.

Abstract: A semiconductor encapsulating epoxy resin composition is provided comprising (A) an epoxy resin, (B) a phenolic resin curing agent, (C) a molybdenum compound, (D-i) an organopolysiloxane, (D-ii) an organopolysiloxane cured product, or (D-iii) a block copolymer obtained by reacting an epoxy resin or alkenyl group-bearing epoxy resin with an organohydrogenpolysiloxane, and (E) an inorganic filler. The composition has improved moldability and solder crack resistance while exhibiting high flame retardance despite the absence of halogenated epoxy resins and antimony oxide.

Abstract: A low-expansion unit includes a plate member and an iron-nickel layer. Upper and lower surface layers of the plate member each have the iron-nickel layer thereon and/or therein. While the plate member has a relatively large thermal expansion coefficient, the iron-nickel layers, which are formed on and/or in the upper and lower surface layers of the plate member, have a relatively small thermal expansion coefficient. Therefore, thermal expansion coefficient of the low-expansion unit is as a whole restrained to a relatively small value. Also, the plate member includes pure iron whose thermal conductivity is relatively high. Meanwhile, the iron-nickel layers, which are formed on the plate member, are relatively thin. Therefore, the low-expansion unit has a relatively large thermal conductivity in a direction of thickness thereof.

Abstract: The thermal interface structure of the present invention is suited for use in a non-referenced die system between a heat source and heat sink spaced up to 300 mils apart and comprises a plurality of layers including a core body of high conductivity metal or metal alloy having opposite sides, a soft thermal interface layer disposed on one side of the core body for mounting against the heat sink and a thin layer of a phase change material disposed on the opposite side of the core body for mounting against the heat source wherein the surface area dimension (footprint) of the core body is substantially larger than the surface area of the heat source upon which the phase change material is mounted to minimize the thermal resistance between the heat source and the heat sink and wherein said soft thermal interface layer is of a thickness sufficient to accommodate a variable spacing between the heat source and the heat sink of up to 300 mils.

Abstract: A nanostructure is a porous body comprising a plurality of pillar-shaped pores and a region surrounding them, said region being an oxide amorphous region formed so as to contain C, Si, Ge or a material of a combination of them. Such a nanostructure can be used as functional material that can be used for light emitting devices, optical devices and microdevices. It can also be used as filter.

Abstract: A practically realizable semiconductor magnetic body having a flat-band structure is disclosed. The semiconductor magnetic body is formed by semiconductor quantum dots arranged on lattice points such that electrons can transfer between neighboring quantum dots and the electron energy band contains a flat-band structure, where each quantum dot is a structure in which electrons are confined inside a region which is surrounded by high energy potential regions, and the flat-band structure is a band structure in which energy dispersion of electrons has hardly any wave number dependency.