Abstract: A method of obtaining information related to a defect present in the irradiation of a substrate coated with a layer of radiation sensitive material using immersion lithography is disclosed. The method includes irradiating an area of the radiation sensitive material with a non-patterned radiation beam, the area being irradiated with a dose which is sufficient for the radiation sensitive material to be substantially removed during subsequent development of the radiation sensitive material if the radiation sensitive material is a positive radiation sensitive material, or with a dose which is sufficient for the radiation sensitive material to be substantially insoluble during subsequent development of the radiation sensitive material if the radiation sensitive material is a negative radiation sensitive material.

Abstract: A method includes providing a layout of an integrated circuit design, and generating a plurality of double patterning decompositions from the layout, with each of the plurality of double patterning decompositions including patterns separated to a first mask and a second mask of a double patterning mask set. A maximum shift between the first and the second masks is determined, wherein the maximum shift is a maximum expected mask shift in a manufacturing process for implementing the layout on a wafer. For each of the plurality of double patterning decompositions, a worst-case performance value is simulated using mask shifts within a range defined by the maximum shift.

Abstract: A target system for determining positioning error between lithographically produced integrated circuit fields on at least one lithographic level. The target system includes a first target pattern on a lithographic field containing an integrated circuit pattern, with the first target pattern comprising a plurality of sub-patterns symmetric about a first target pattern center and at a same first distance from the first target pattern center. The target system also includes a second target pattern on a different lithographic field, with the second target pattern comprising a plurality of sub-patterns symmetric about a second target pattern center and at a same second distance from the second target pattern center. The second target pattern center is intended to be at the same location as the first target pattern center. The centers of the first and second target patterns may be determined and compared to determine positioning error between the lithographic fields.

Abstract: A method of performing overlay error correction includes forming a photoresist layer over a substrate and exposing a first set of apertures to incident radiation. The method also includes determining an overlay error associated with the first set of apertures and determining an overlay correction as a function of the determined overlay error. The method further includes exposing a data area and a second set of apertures. The data area and the second set of apertures are exposed based, in part, on the determined overlay correction. Moreover, the method includes verifying the determined overlay correction.

Abstract: A lithographic apparatus, includes a support structure configured to hold a patterning device, the patterning device configured to impart a beam of radiation with a pattern in its cross-section; a substrate table configured to hold a substrate; a projection system configured to project the patterned beam onto a target portion of the substrate; a liquid supply system configured to provide liquid to a space between the projection system and the substrate table; a sensor configured to measure an exposure parameter using a measuring beam projected through the liquid; and a correction system configured to determine an offset based on a change of a physical property impacting a measurement made using the measuring beam to at least partly correct the measured exposure parameter.

Abstract: An alignment method is disclosed, in which a distance between a substrate and a photomask is set at a predetermined exposure gap. The photomask is rectangular, and includes a first side, and a second side opposite to the first side. A distance between a midpoint of the first side and the substrate is matched with the exposure gap. The photomask is rotated about, as an axis, a line that connects the midpoint of the first side and a midpoint of the second side to each other, whereby distances between both ends of the first side and the substrate are individually matched with the exposure gap.

Abstract: A position aligning apparatus performs position alignment of a pattern in a current process of a pattern exposure process by using a pattern formed before the current process. The position aligning apparatus includes: a correction calculating section configured to calculate a correction value set of a current lot about each of misalignments in scale and rotation of a pattern in a chip in the current process based on a correction value set in an immediately-preceding lot in the current process, a completeness value set in the immediately-preceding lot in the current process, a summation of completeness value sets in the immediately-preceding lot to a process immediately-preceding to the current process, and a summation of completeness value sets in the current lot to the immediately-preceding process; and a correction control unit configured to control correction of the scale and the rotation of the pattern in the chip by using the correction value sets.

Abstract: In an exposure aligning method, a first shift amount indicating a shift amount of a lower layer pattern of an exposure target substrate from an origin point position is determined and a second shift amount indicating a shift amount of the lower layer pattern in at lease one past lot which has been processed before said exposure target substrate is processed, from the origin point position is determined. A third shift amount indicating a difference between the first shift amount and the second shift amount is calculated and a first correction value is determined based on the third shift amount. An exposure position of an exposure target pattern is adjusted based on the first correction value.

Abstract: In an exposure process forming a predetermined circuit pattern of a semiconductor device on a wafer, a resist dimension of the resist pattern formed on a wafer and a focus position in the exposure process at a past time are measured. A resist dimension and a focus position of a wafer to which the exposure process is secondly performed are estimated by using measurement results of the measured resist dimension and focus position, and a focus offset value is calculated by using estimated values of the estimated resist dimension and focus position. Then, an exposure dose is calculated with considering this focus offset value, and a resist pattern is formed on the wafer to which the exposure process is performed by using the calculated exposure dose and focus offset value.

Abstract: A method for transferring an image of a mask pattern through a pitch range onto a substrate is presented. In an embodiment, the method includes illuminating the mask pattern of an attenuated phase shift mask using a multipole illumination that includes an on-axis component and an off-axis component, the mask pattern including non-printing assist features configured for a pitch larger than twice a minimum pitch of the mask pattern, and projecting an image of the illuminated mask pattern onto the substrate.

Abstract: By encoding process-related non-uniformities, such as different height levels, which may be caused by CMP or other processes during the fabrication of complex device levels, such as metallization structures, respective focus parameter settings may be efficiently evaluated on the basis of well-established CD measurement techniques.

Abstract: By taking into consideration the combination of the substrate holders in various lithography tools used during the imaging to two subsequent device layers, enhanced alignment accuracy may be accomplished. Furthermore, restrictive tool dedications for critical lithography processes may be significantly relaxed by providing specific overlay correction data for each possible process flow, wherein, in some illustrative embodiments, a restriction of the number of possible process flows may be accomplished by implementing a rule for selecting a predefined substrate holder when starting the processing of an associated group of substrates.

Abstract: A pattern designing method according to an embodiment of the present invention includes: designing a first pattern for inspection formed by arraying a plurality of first mark rows, in which rectangular marks are arrayed at predetermined intervals in a first direction, in a second direction perpendicular to the first direction and designing a second pattern for inspection formed by arraying, in the second direction, a plurality of second mark rows in which rectangular marks are arranged among the marks arrayed in the first direction of the first mark row and a forming position in the second direction is arranged to overlap the first mark row by predetermined overlapping length.

Abstract: Methods, systems, and tool sets involving reticles and photolithography processing. Several embodiments of the invention are directed toward obtaining qualitative data from within the pattern area of a reticle that is indicative of the physical characteristics of the pattern area. Additional embodiments of the invention are directed toward obtaining qualitative data indicative of the physical characteristics of the reticle remotely from a photolithography tool. These two aspects of the invention can be combined in further embodiments in which qualitative data is obtained from within the pattern area of a reticle in a tool that is located remotely from the photolithography tool. As a result, several embodiments of methods and systems in accordance with the invention provide data taken from within the pattern area to more accurately reflect the contour of the pattern area of the reticle without using the photolithography tool to obtain such measurements.

Abstract: A device manufacturing method includes a transfer of a pattern from a patterning device onto a substrate. The device manufacturing method further includes transferring a pattern of a main mark to a base layer for forming an alignment mark; depositing a pattern receiving layer on the base layer; in a first lithographic process, aligning, by using the main mark, a first mask that includes a first pattern and a local mark pattern, and transferring the first pattern and the local mark pattern to the pattern receiving layer; aligning, by using the local mark pattern, a second mask including a second pattern relative to the pattern receiving layer; and in a second lithographic process, transferring the second pattern to the pattern receiving layer; the first and second patterns being configured to form an assembled pattern.

Abstract: There is provided a method for fabricating a magnetic recording medium that provides high throughput, low manufacturing cost, and no degradation in accuracy in pattern size in fine pattern formation. A resist layer is formed on a substrate or cutting work layer. The surface of the substrate is divided into two or more areas using the center of rotation of the substrate as a reference point. An optical, contactless pattern transfer method is used to transfer a figure pattern contained in the divided area through a mask to the resist layer so as to form a latent image of the figure pattern. The pattern transfer is similarly carried out for the divided area. After the pattern transfer processes for all the divided areas are completed, the entire resist layer is developed to form a resist pattern. The resist pattern is used as a mask to cut the substrate or cutting work layer. As a result, there is provided the substrate or cut work layer onto which a fine pattern has been transferred.

Abstract: A photomask manufacturing method includes a defect information storage step of storing defect information of a mask blank, provided with an identification marker on an end face thereof, into an information storage device in correspondence to the identification marker, a placing orientation determination step of determining a placing orientation of the mask blank with respect to an exposure/writing apparatus, and an orientation correction step of performing rotation control of a rotating apparatus so that an orientation of the mask blank coincides with the determined placing orientation.

Abstract: A photomask includes a transparent substrate having a transparent property against exposing light and a halftone portion formed on the transparent substrate. In the halftone portion, a first opening having a first dimension and a second opening having a second dimension larger than the first dimension are formed. A light-shielding portion is formed on the transparent substrate to be disposed around the second opening.

Abstract: A photomask includes a transparent substrate having a transparent property against exposing light, a semi-light-shielding portion formed on the transparent substrate, a first opening formed in the semi-light-shielding portion and having a first dimension and a second opening formed in the semi-light-shielding portion and having a second dimension lager than the first dimension. A phase-shifting portion which transmits the exposing light in an opposite phase with respect to the first opening is formed on the transparent substrate around the first opening. A light-shielding portion is formed on the transparent substrate around the second opening.

Abstract: An overlay vernier key includes a semiconductor substrate on which a cell region and a scribe lane region are defined, and a plurality of vernier patterns which are formed in the scribe lane region of the semiconductor substrate and arranged in a polygonal shape. Each of the vernier patterns has a hollow polygonal shape.

Abstract: A method for photolithography in semiconductor manufacturing includes providing one or more masks for a wafer; defining a reference focus plane of a first mask of the one or more masks; defining a reference focus plane of a second mask of the one or more masks; and determining the best focus for the second mask based on the best focus of the first mask and the Z direction difference of the first and second masks, using the reference focus planes of the first and second masks.

Abstract: An exposure measurement apparatus is configured by including a size measurer measuring respective sizes of at least a pair of transferred patterns having mutually different optimal focus positions out of a plurality of transferred patterns formed by being transferred onto a transfer object, a difference value calculator obtaining a difference value between the size of one transferred pattern and the size of the other transferred pattern, a focus variation amount calculator calculating a focus variation amount of the transfer object using the difference value, and an exposure variation amount calculator calculating an exposure error amount of a wafer.

Abstract: In order to provide a reticle capable of increasing the number of chips per wafer and of enabling highly accurate alignment, and an exposure method using the reticle, a first alignment mark arrangement region (8) and a second alignment mark arrangement region (9) are provided on both sides of a multi-chip region (2) so that a sum of a size of the first alignment mark arrangement region and a size of the second alignment mark arrangement region is made the same as a size of a chip region (1).

Abstract: An exposure method includes the steps of illuminating a mask that has a contact hole pattern using an illumination light, and projecting, via a projection optical system, the contact hole pattern onto a substrate to be exposed, wherein three lights among diffracted lights from the contact hole pattern interfere with each other, wherein said mask is an attenuated phase shift mask, and wherein said illumination light forms a radial polarization illumination.

Abstract: Disclosed is a method for making long flexible circuits. Some of the long circuits may be made using a single photoimaging mask. Also disclosed are flexible circuits made by this method.

Abstract: By repeatedly executing a predetermined measurement at set intervals, data on a predetermined performance (a best focus position) of a predetermined apparatus and data on variation factors of the performance are obtained (Steps 204 to 214). Based on the obtained data, multivariate analysis is performed and a model equation that is used to predict a variation amount of the performance and includes at least one of the variation factors as a variable is derived (Step 214). Therefore, after deriving the model equation, a variation amount of the performance can be predicted using the model equation by obtaining data on the variation factor that serves as the variable (Step 238). Accordingly, it becomes possible to maintain the performance described above with good accuracy in accordance with the prediction results and also optimize the implementation timing of maintenance and the like.

Abstract: A system and a method for self-aligned dual patterning are described. The system includes a platform for supporting a plurality of process chambers. An etch process chamber coupled to the platform. An ultra-violet radiation photo-resist curing process chamber is also coupled to the platform.

Abstract: A mark for alignment and overlay, a mask having the same, and a method of using the same are provided. The mark includes a first mark pattern and a second mark pattern. The first mark pattern includes a first pattern and a second pattern, and the second mark pattern includes a third pattern and a fourth pattern. The first pattern includes a plurality of rectangular regions arranged in a first direction, and for each rectangular region, a sideline in a second direction is longer than a sideline in the first direction, wherein the first direction is perpendicular to the second direction. The second pattern is disposed on both sides of the first pattern in the second direction and includes a plurality of rectangular regions arranged in the second direction, and for each rectangular region, the sideline in the first direction is longer than a sideline in the second direction.

Abstract: A lithography mask is disclosed, comprising an alignment mark, including a first bar, a second bar crossing the first bar, and a specific pattern having different signatures with the first and second bars connecting to the second bar.

Abstract: A semiconductor device manufacturing method has forming a first resist pattern on the semiconductor substrate, and then, forming a first pattern on the semiconductor substrate by the use of the first resist pattern, and forming a second resist pattern on the semiconductor substrate by using an imprinter, and then, forming a second pattern on the semiconductor substrate by the use of the second resist pattern. The forming the first pattern, the first pattern smaller than a design pattern corresponding to the design data for forming a plurality of patterns on a semiconductor substrate being formed.

Abstract: A device manufacturing method includes a transfer of a pattern from a patterning device onto a substrate. The device manufacturing method further includes transferring a pattern of a main mark to a base layer for forming an alignment mark; depositing a pattern receiving layer on the base layer; in a first lithographic process, aligning, by using the main mark, a first mask that includes a first pattern and a local mark pattern, and transferring the first pattern and the local mark pattern to the pattern receiving layer; aligning, by using the local mark pattern, a second mask including a second pattern relative to the pattern receiving layer; and in a second lithographic process, transferring the second pattern to the pattern receiving layer; the first and second patterns being configured to form an assembled pattern.

Abstract: In a scatterometric method differential targets with different sensitivities to parameters of interest are printed in a calibration matrix and difference spectra obtained. principal component analysis is applied to the difference spectra to obtain a calibration function that is less sensitive to variations in the underlying structure than a calibration function obtained from spectra obtained from a single target.

Abstract: An overlay target on a substrate is disclosed, the overlay target including a periodic array of structures wherein every nth structure is different from the rest of the structures. The periodic array is desirably made of two interlaced gratings, one of the gratings having a different pitch from the other grating in order to create an asymmetry in the array. This asymmetry can then be measured by measuring the diffraction spectra of radiation reflected from the overlay target. Variation in the asymmetry indicates the presence of an overlay error in layers on the substrate, where overlay targets are printed on subsequent layers.

Abstract: In a photomask in which a device pattern, an alignment mark and a superimposition inspection mark are formed on a light transmitting base, each of the alignment mark and the superimposition inspection mark includes a main mark portion, and first and second auxiliary pattern portions. The main mark portion is constituted of one of a space pattern and a line pattern, the pattern having a linear width to be resolved on a photosensitive film formed on a semiconductor wafer, and each of the first and second auxiliary pattern portions includes an auxiliary pattern constituted of one of a repeated pattern of a space pattern and a repeated pattern of a line pattern, the repeated pattern having a linear width not to be resolved on the photosensitive film. The pitch of the repeated pattern is equal to the minimum pitch of the device pattern.

Abstract: An exposure method suitable for a photolithography process is described. First, a wafer with a group of alignment marks formed thereon is provided. A first alignment step is conducted by using the group of the alignment marks on the wafer to obtain a first calibration data. Next, a second alignment step is conducted by using a portion of the group of alignment marks on the wafer to obtain a second calibration data. The first calibration data is then compared with the second calibration data to obtain a comparison result. Next, a photoresist exposure step is conducted on the wafer according to the comparison result.

Abstract: A manufacturing method for conducting films on two opposite surfaces of a transparent substrate of a touch control circuit, includes: contacting a first photoresist layer having photosensitive and discolored emulsion on a first conducting coat formed on a first surface of the transparent substrate, and contacting a second photoresist layer on a second conducting coat formed on a second surface of the transparent substrate; exposing the first photoresist layer to form a circuit pattern with distinguishable color on exposed regions of the first photoresist layer; employing the circuit pattern as an aligning benchmark for the second photoresist layer, and exposing the second photoresist layer accordingly; developing and etching those arranged on the two surfaces of the transparent substrate at the same time to form a first conducting film of a touch control circuit from the first conducting coat and form a second conducting film of the touch control circuit from the second conducting coat.

Abstract: A wiring forming system comprises: maskless exposure unit which directly exposes an unexposed board by using exposure data generated based on design data relating to an wiring board; post-development inspect unit which tests the board after development, by using the exposure data and the image data of the board exposed and developed by the maskless exposure unit; etching unit which etches the developed board; and post-etching inspect unit which tests an etching pattern formed on the etched board, by using etching inspect data generated based on the design data and the image data of the board etched by the etching unit.

Abstract: A method of manufacturing a semiconductor device that includes: a first exposing step using a photomask in a first area of a semiconductor substrate; and a second exposing step using the photomask in a second area adjacent to the first area of the semiconductor substrate. The photomask includes a first transmitting pattern having a ring shape that is missing a part, and a supplemental second transmitting pattern having a shape corresponding to the missing part of the first transmitting pattern, so that a closed loop pattern is exposed by the first exposing step and the second exposing step on the semiconductor substrate.

Abstract: The invention relates to a device and a method for producing resist profiled elements. According to the invention, an electron beam lithography system is used to produce an electron beam, the axis of the beam being essentially perpendicular to a resist layer in which the resist profiled element is to be produced. The electron beam can be adjusted in terms of the electron surface dose in such a way that a non-orthogonal resist profiled element can be produced as a result of the irradiation by the electron beam.

Abstract: A lithographic method includes patterning a beam of radiation with a patterning device. The patterning device includes at least two image patterning portions and at least two metrology mark patterning portions. The method also includes projecting at least two image portions of the patterned beam of radiation sequentially onto target portions of a substrate such that the projected image portions are substantially adjacent to each other on the substrate and collectively form a composite image on the substrate. The method also includes projecting a metrology mark onto the substrate outside of the area of the composite image at the same time as projecting each of at least two of the image portions, and measuring the alignment of the metrology marks to determine the relative positions of the at least two image portions.

Abstract: A method of determining positioning error between lithographically produced integrated circuit patterns on at least two different lithographic levels of a semiconductor wafer comprising. The method includes exposing, developing and etching one or more lithographic levels to create one or more groups of marks comprising a target at one or more wafer locations. The method then includes exposing and developing a subsequent group of marks within the target on a subsequent lithographic level. The method then comprises measuring the position of the marks on each level with respect to a common reference point, and using the measured positions of the groups of marks to determine the relative positioning error between one or more pairs of the developed and etched lithographic levels on which the marks are located.

Abstract: A target system for determining positioning error between lithographically produced integrated circuit fields on at least one lithographic level. The target system includes a first target pattern on a lithographic field containing an integrated circuit pattern, with the first target pattern comprising a plurality of sub-patterns symmetric about a first target pattern center and at a same first distance from the first target pattern center. The target system also includes a second target pattern on a different lithographic field, with the second target pattern comprising a plurality of sub-patterns symmetric about a second target pattern center and at a same second distance from the second target pattern center. The second target pattern center is intended to be at the same location as the first target pattern center. The centers of the first and second target patterns may be determined and compared to determine positioning error between the lithographic fields.

Abstract: A method of manufacturing a semiconductor device answerable to refinement of circuits by correctly connecting adjacent small patterns with each other with excellent reproducibility in connective exposure and a semiconductor device manufactured by this method are proposed. According to this method of manufacturing a semiconductor device, connective exposure is performed by dividing a pattern formed on a semiconductor substrate into a plurality of patterns and exposing the plurality of divided patterns in a connective manner, by forming marks for adjusting arrangement of the patterns to be connected with each other on the semiconductor substrate before exposing patterns of a semiconductor element and connectively exposing the patterns of the semiconductor element in coincidence with the marks for adjusting arrangement.

Abstract: A near-field exposure apparatus includes a near-field exposure mask and a mechanism places a substrate, to be exposed, opposed to the near-field exposure mask. A mechanism performs relative alignment of the near-field exposure mask and the substrate to be exposed. A mechanism closely contacts the near-field exposure mask and the substrate to be exposed, with each other. A mechanism projects exposure light to the near-field exposure mask, and a soft X-ray irradiating device removes static electricity charged in at least one of the near-field exposure mask and the substrate to be exposed. The soft X-ray irradiating device is disposed such that the near-field exposure mask is located between the soft X-ray irradiating device and the substrate to be exposed.

Abstract: The invention provides an exposure method for manufacturing a device. The method includes providing a wafer having several exposure regions with a photoresist layer covering thereon. A feedback parameter map with several exposure-region feedback parameter sets respectively corresponds to the exposure regions of the wafer. At least one of the exposure-region feedback parameter sets is different from the rest of the exposure-region feedback parameter sets. According to the feedback parameter map, an exposure process is sequentially performed on each of the exposure regions of the wafer through an exposure tool to pattern the photoresist layer on the wafer. While the exposure tool performs the exposure process on each of the exposure regions, an exposure process parameter set of the exposure tool is adjusted based on the exposure-region feedback parameter sets corresponding to the exposure region in the feedback parameter map.

Abstract: Aspects of the invention can provide a method for manufacturing a microstructure, including forming a photosensitive film above a work piece, exposing the photosensitive film, as a first exposure, by irradiating interference light generated by intersecting two laser beams having a wavelength shorter than a wavelength of visible light, developing the exposed photosensitive film so as to develop a shape corresponding to a pattern of the interference light to the photosensitive film, and etching the work piece using the developed photosensitive film as an etching mask.

Abstract: A method of making a substantial replica of a first imprint template which bears a first pattern is disclosed. The method includes filling recesses of the first pattern with a first material, removing the first material from the first imprint template to form a second imprint template which bears a second pattern, the second pattern being the substantial inverse of the first pattern, filling recesses of the second pattern with a photo-curable medium, curing the photo-curable medium by illuminating it with radiation, and removing the cured medium from the second imprint template to form a third imprint template which bears a pattern that is a substantial replica of the first pattern.

Abstract: A method of semiconductor manufacturing including forming an overlay offset measurement target including a first feature on a first layer and a second feature on a second layer. The first feature and the second feature have a first predetermined overlay offset. The target is irradiated. The reflectivity of the irradiated target is determined. An overlay offset for the first layer and the second layer is calculated using the determined reflectivity.

Abstract: According to the present invention, provided is a method of manufacturing a electronic device including forming a film over a substrate, performing a photoresist over the film, performing a first exposure by using an exposure mask which includes a scribe region and a inspection mark formed in a first side of the scribe region, and performing a second exposure so that a region that is exposed to the first side in the first exposure is exposed to a second side of the scribe region which is opposite to the first side, wherein, in the second exposure, an exposure light is incident on a region where the inspection mark is projected in the first exposure.

Abstract: An apparatus and method for the simultaneous determination of focus and source boresighting error for photolithographic steppers and scanners is described. A reticle containing custom arrays of box-in-box test structures specifically designed for performing source or exit pupil division using an aperture plate is exposed onto a resist coated wafer several times. The resulting exposure patterns are measured with a conventional overlay tool. The overlay data is processed with a slope-shift algorithm for the simultaneous determination of both focus and source telecentricity as a function of field position. Additionally, methods for ameliorating metrology induced effects and methods for producing precision Bossung curves are also described. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules, it shall not be used to interpret or to limit the scope or the meaning of the claims.