Including Multiple Resist Image Formation Patents (Class 430/312)
  • Patent number: 7183025
    Abstract: A phase shift mask comprises first and second mask patterns. The first mask pattern is a backing film enabling a first optical image to be formed on a substrate. The first optical image forms a resist pattern having a width that changes depending on the distance between the phase shift mask and the substrate. The second mask pattern is a semi-transmissive film enabling a second optical image to be formed on the substrate. The second optical image can form a resist pattern having a width that changes depending on the distance between the phase shift mask and the substrate and on a thickness of the semi-transmissive film. The duty ratio of the second mask is set so that the rate at which the width of the first optical image varies will be the same as the rate at which the width of the second optical image varies.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: February 27, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Daigo Hoshino
  • Patent number: 7177072
    Abstract: A photosensitive resist layer is formed on one surface of a single-polarized ferroelectric substance having nonlinear optical effects. The resist layer has properties such that, when light is irradiated to the resist layer, only exposed areas of the resist layer or only unexposed areas of the resist layer become soluble in a developing solvent. The resist layer is then exposed to near-field light in a periodic pattern with a device, which receives exposure light and produces the near-field light in the periodic pattern. The resist layer is then developed to form a periodic pattern. A periodic electrode is then formed on the one surface of the ferroelectric substance by utilizing the periodic pattern of the resist layer as a mask, the periodic electrode being formed at positions corresponding to opening areas of the mask.
    Type: Grant
    Filed: December 20, 2005
    Date of Patent: February 13, 2007
    Assignee: Fuji Photo Film Co., Ltd.
    Inventors: Yasukazu Nihei, Masayuki Naya
  • Patent number: 7175777
    Abstract: A single, controlled etch step can be used to form a sharp tip feature along a sidewall of an etch feature. An etch process is used that is selective to a layer of tip material relative to the substrate upon which the layer is deposited. A lag can be created in the etch, such that the etch rate is slower near the sidewall. The sharp tip feature is formed from the same layer of material used to create the etch feature. The sharp tip feature can be used to decrease the minimum critical dimension of an etch process, such as may be due to the minimum resolution of a photolithographic process. The novel tip feature also can be used for other applications, such as to create a microaperture for a photosensitive device, or to create a micromold that can be used to form objects such as microlenses.
    Type: Grant
    Filed: December 2, 2003
    Date of Patent: February 13, 2007
    Assignee: National Semiconductor Corporation
    Inventors: André Paul Labonté, Lee James Jacobson
  • Patent number: 7175951
    Abstract: A method for in-situ overlay accuracy checking using a first mask having a first pattern and a second mask having a second pattern to expose a layer of photosensitive material formed on a wafer. The first pattern and the second pattern are exposed in the layer of photosensitive material using the first mask, the second mask, and a photolithographic alignment and exposure system. The layer of photosensitive material is then developed and the relative position between the first pattern and the second pattern is analyzed.
    Type: Grant
    Filed: April 19, 2002
    Date of Patent: February 13, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Hong-Shing Chou
  • Patent number: 7160654
    Abstract: A method is provided for improving layer to layer overlay of a second layer pattern on a first layer pattern formed in a substrate. A plurality of first reference marks is placed inside a pattern area on a first layer mask which is used to form the first layer pattern. A plurality of second reference marks is placed on a second layer mask which is used to form the second layer pattern and in which one second reference mark is matched with a first reference mark having the same (x,y) coordinates. Reference mark placement in the resulting first and second layer patterns is determined by metrology to determine an x-deviation and a y-deviation for each matched pair of reference marks. A correction algorithm is then used to calculate adjustments in exposure tool settings for improved overlay of the second layer pattern on the first layer pattern in subsequent exposures.
    Type: Grant
    Filed: December 2, 2003
    Date of Patent: January 9, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Fei-Gwo Tsai
  • Patent number: 7160670
    Abstract: A scintillating structure for aligning an electron or ion beam using a detector while exposing a wafer, which may be a wafer or mask, is described. The structure is formed by a resist including a polymer with carboxylic acid groups, anhydride groups, and an acid-sensitive group, for instance tert.-butylester; a photoreactive compound which releases an acid upon irradiation with UV light, electrons, or ions; a solvent; and at least one scintillating substance such as anthracene, naphthaline and/or 1,4-bis-(5-phenyl-2-oxazolyl)-benzol. After a developing and silylating step, the cross-linked structure is inert with respect to solvents of additional resists that are applied over the structure. The scintillating structure is thus not dissolved, which improves the quality of online controlled electron or ion beam writing.
    Type: Grant
    Filed: January 13, 2003
    Date of Patent: January 9, 2007
    Assignee: Infineon Technologies AG
    Inventor: Klaus Elian
  • Patent number: 7150955
    Abstract: A light-sensitive sheet comprises a support, a first light-sensitive layer, a barrier layer and a second light-sensitive layer in this order. Each of the first and second light sensitive layers independently contains a binder, a polymerizable compound and a photo-polymerization initiator. The second light-sensitive layer is more sensitive to light than the first light-sensitive layer. A light-sensitive laminate comprises a substrate, the second light-sensitive layer, the barrier layer and the first light-sensitive layer in this order.
    Type: Grant
    Filed: August 12, 2004
    Date of Patent: December 19, 2006
    Assignee: Fuji Photo Film Co., Ltd.
    Inventors: Morimasa Sato, Yuichi Wakata, Masanobu Takashima, Tomoko Tashiro
  • Patent number: 7150948
    Abstract: A photomask includes a main mask pattern having first chip patterns and having a first size corresponding to a maximum exposure area of a projection exposure apparatus. The mask further includes a sub-mask pattern having second chip patterns different from the first chip patterns, having a second size smaller than the first size, and arranged adjacently to the main mask pattern.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: December 19, 2006
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Tuguto Maruko
  • Patent number: 7150949
    Abstract: The present invention relates to methods for patterning substrates, such as reticles, masks or wafers, which reduce critical dimension variations, improving CD uniformity. In particular, it relates to tuning doses applied in passes of a multipass writing strategy to measurable characteristics of resists or radiation sensitive layers applied to the substrates. Particular writing strategies are described. Aspects of the present invention are described in the claims, specification and drawings.
    Type: Grant
    Filed: August 4, 2004
    Date of Patent: December 19, 2006
    Assignee: Micronic Laser Systems AB
    Inventors: Per Askebjer, Hans Fosshaug, Robert Eklund, Jonathan Walford
  • Patent number: 7141507
    Abstract: A method for producing a semiconductor structure including preparing a semiconductor substrate, and generating a lower first, a middle second and an upper third masking layer on a surface of the semiconductor substrate. The method further includes forming at least one first window in the upper third masking layer, structuring the middle second masking layer using the first window for transferring the first window, structuring the lower first masking layer using the first window for transferring the first window, and enlarging the first window to form a second window. The method for further includes restructuring the middle second masking layer using the second window for transferring the second window, structuring the semiconductor substrate, using the structured lower third masking layer, restructuring the lower first masking layer using the second window, and restructuring the semiconductor substrate using the restructured lower third masking layer.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: November 28, 2006
    Assignee: Infineon Technologies AG
    Inventors: Oliver Genz, Markus Kirchhoff, Stephan Machill, Alexander Reb, Barbara Schmidt, Momtchil Stavrev, Maik Stegemann, Stephan Wege
  • Patent number: 7142279
    Abstract: In a method of manufacturing a liquid crystal display using a divisional exposure for a substrate, an overlapping area at the boundary between adjacent shots is provided and the shots left and right to the boundary are exposed in a way that the areas of the shots gradually decreases and gradually increases, respectively, to reduce the brightness difference due to stitch errors between the two shots. For example, the number of unit stitch areas assigned to the left gradually decreases and the number of unit stitch areas assigned to the right shot gradually increases as it goes to the right along the transverse direction in the stitch area. A unit stitch includes an area obtained by dividing a pixel into at least two parts.
    Type: Grant
    Filed: September 18, 2002
    Date of Patent: November 28, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Mi Tak, Woon-Yong Park, Kwon-Young Choi, Myung-Jae Park
  • Patent number: 7129025
    Abstract: A fabrication method of three-dimensional microstructures is to fabricate a real 3D microstructure. First, a substrate is coated with an anti-reflection layer to absorb reflected exposure light, and then the anti-reflection layer is overlaid with a first thick photoresist. After having been fully exposed by a first photo mask, a predetermined exposure depth of the first thick photoresist is achieved by a second photo mask and dosage-controlled UV exposure. If the unexposed areas of the first thick photoresist are released during a development step, a single-layer microstructure is created. Inversely, a multi-layered microstructure can be obtained simply by repeating the process described above. After all layers are laminated on the substrate, all unexposed areas of the all thick photoresist layers are released and connected to each other during a development step.
    Type: Grant
    Filed: May 14, 2003
    Date of Patent: October 31, 2006
    Assignee: National Tsing Hua University
    Inventors: Fan-Gang Tseng, Yun-Ju Chuang
  • Patent number: 7122282
    Abstract: A method of forming a mask pattern includes a step of laminating a first resist layer on a base layer, a step of exposing the first resist layer using a first pattern with a pattern of at least one via hole, a step of developing the first resist layer exposed to remove a part of the first resist layer, the part corresponding to an area of the at least one via hole, a step of laminating a second resist layer on the first resist layer and on the base layer in the area of the at least one via hole, a step of exposing the second resist layer using a second pattern, and a step of developing the second resist layer exposed and the first resist layer to remove a part of the second resist layer and all of the first resist layer so as to form the mask pattern made of the second resist layer.
    Type: Grant
    Filed: March 20, 2003
    Date of Patent: October 17, 2006
    Assignee: TDK Corporation
    Inventors: Yoshikazu Sato, Akifumi Kamijima
  • Patent number: 7115208
    Abstract: A recording medium includes a substrate, and a recording layer formed on the substrate having (a) a recording track band, and (b) recording cells regularly arrayed in the recording track band to form a plurality rows of sub-tracks. The recording cells included in each sub-track are formed apart from each other at a pitch P in the track direction. Nearest neighboring two recording cells, each positioned on adjacent two sub-tracks in the track band, are formed apart from each other at a pitch P/n in the track direction, where 2?n?5.
    Type: Grant
    Filed: December 1, 2004
    Date of Patent: October 3, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Hieda, Masatoshi Sakurai, Koji Asakawa, Toshiro Hiraoka, Katsuyuki Naito
  • Patent number: 7108946
    Abstract: Methods of fabricating an integrated circuit on a wafer using dual mask exposure lithography is disclosed. Improved mask image alignment between a first mask image and a second mask image of a dual mask exposure technique can be achieved by aligning the second mask image to a latent image created by an exposure using the first mask image.
    Type: Grant
    Filed: January 12, 2004
    Date of Patent: September 19, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Todd P. Lukanc, Sarah N. McGowan, Bhanwar Singh, Joerg Reiss
  • Patent number: 7090783
    Abstract: A method of patterning self-assembled thin films, including forming a photoresist layer on a substrate and then patterning and etching the photoresist layer. In combination with the etched photoresist layer, a self-assembled layer is formed on the substrate using LbL self-assembly.
    Type: Grant
    Filed: March 13, 2003
    Date of Patent: August 15, 2006
    Assignee: Louisiana Tech University Research Foundation as a Division of the Louisiana Tech University Foundation
    Inventors: Tianhong Cui, Yuri Lvov, Feng Hua
  • Patent number: 7087363
    Abstract: A method of forming a top gate thin film transistor (TFT). By performing photolithography using a first reticle, a photoresist layer having a thick photoresist layer portion and a thin photoresist layer portion is formed on a silicon layer in an active area. Thus, a channel layer and source/drain regions in a silicon island are defined by the same patterning process. In addition, a gate and an LDD region in the silicon island are defined by photolithography using a second reticle and a backside exposure process. Accordingly, the top gate TFT fabrication process of the present invention requires only two reticles, and thereby reduces costs.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: August 8, 2006
    Assignee: Industrial Technology Research Institute
    Inventors: Chih-Chiang Chen, Ching-Sang Chuang, Jiun-Jye Chang
  • Patent number: 7083899
    Abstract: Disclosed is a method for manufacturing a semiconductor device by employing a dual damascene process. After a first insulation film including a conductive pattern is formed on a substrate, at least one etch stop film and at least one insulation film are alternatively formed on the first insulation film. A via hole for a contact or a trench for a metal wiring is formed through the insulation film, and then the via hole or the trench is filled with a filling film including a water-soluble polymer. After a photoresist film is coated on the filling film, the photoresist film is patterned to form a photoresist pattern and to remove the filling film. The DOF and processing margin of the photolithography process for forming the photoresist pattern can be improved because the photoresist film can have greatly reduced thickness due to the filling film.
    Type: Grant
    Filed: May 5, 2003
    Date of Patent: August 1, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bong-Cheol Kim, Dae-Youp Lee
  • Patent number: 7077974
    Abstract: A method of making, and the resultant mask, comprises developing resist layers over surfaces of a masking layer to transfer significantly reduced sized openings within glass masters attached to the surfaces of the masking layer into the resist layers. These significantly reduced sized openings within the resist layers are then transferred into the masking layer within a first etch bath by simultaneously monitoring and controlling both etchant activity and concentration of a byproduct within the etch bath formed between the masking material and the etchant. The openings may be etched to completion within the first etch bath, or alternatively, the openings may be etched to a pre-finished image size. Wherein the openings are etched to a pre-finished image size, the masking layer is immersed into a second etch bath for further micro-etching of these openings to a final desired image size.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: July 18, 2006
    Assignee: International Business Machines Corporation
    Inventors: Peter Berasi, Michael Jerome, Doris Pulaski, Robert Rippstein
  • Patent number: 7070701
    Abstract: A fine structure manufacturing method is provided. The method comprises providing a lyophilic film on a treated surface of a substrate on which a pattern having a desired form is to be formed, providing a liquid-repellent film on an upper surface of the lyophilic film, the liquid-repellent film having liquid repellency relative to a liquid material used for forming the pattern, and eliminating a part of the liquid-repellent film located on an area where the pattern is to be formed.
    Type: Grant
    Filed: October 8, 2003
    Date of Patent: July 4, 2006
    Assignee: Seiko Epson Corporation
    Inventors: Kenichi Takagi, Tomohiko Sogo, Yuji Saito
  • Patent number: 7067236
    Abstract: The present invention provides a method of manufacturing a member pattern having a patterned member on a substrate, the method including: a first exposure step of exposing a desired region of a negative type photosensitive material applied to the substrate to light from a first direction; a second exposure step of exposing the desired region of the negative type photosensitive material to light from a second direction opposite to the first direction; a development step of performing development after the exposure steps to form a precursor pattern of the member; and a step of baking the precursor pattern.
    Type: Grant
    Filed: July 16, 2003
    Date of Patent: June 27, 2006
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shuji Yamada, Takahiro Hachisu, Tadayasu Meguro
  • Patent number: 7067235
    Abstract: A method for semiconductor device feature development using a bi-layer photoresist including providing a non-silicon containing photoresist layer over a substrate; providing a silicon containing photoresist layer over the non-silicon containing photoresist layer; exposing an exposure surface of the silicon containing photoresist layer to an activating light source said exposure surface defined by an overlying pattern according to a photolithographic process; developing the silicon containing photoresist layer according to a photolithographic process to reveal a portion the non-silicon containing photoresist layer; and, dry developing said non-silicon containing photoresist layer in a plasma reactor by igniting a plasma from an ambient mixture including at least nitrogen and oxygen.
    Type: Grant
    Filed: January 15, 2002
    Date of Patent: June 27, 2006
    Inventors: Ming Huan Tsai, Hun-Jan Tao
  • Patent number: 7068433
    Abstract: Disclosed herein is a focusing screen master having a microlens array formed all over a flat substrate surface, the microlens array being constructed by arranging a plurality of types of microlenses that are different from each other in height, radius of curvature and surface configuration.
    Type: Grant
    Filed: November 16, 2004
    Date of Patent: June 27, 2006
    Assignee: Olympus Corporation
    Inventors: Hidetaka Hayashi, Satoshi Fujimori
  • Patent number: 7060626
    Abstract: A method for forming a semiconductor wafer comprising of applying a first patterned resist to at least one first predetermined region of a wafer where said at least one first predetermined region of said wafer are protected by said first patterned resist and a first remaining portion of said wafer is not protected by said first patterned resist; etching said first remaining portion of said wafer not protected by said first pattern resist; stripping the first pattern resist from said wafer; applying a second patterned resist to at least one second pre-determined region of said wafer where said at least one second predetermined region of said wafer are protected by a second patterned resist and a second remaining portion is not protected by said second patterned resist; etching said second remaining portion not protected by said second patterned resist; and stripping said second patterned resist from said wafer.
    Type: Grant
    Filed: June 25, 2003
    Date of Patent: June 13, 2006
    Assignee: International Business Machines Corporation
    Inventors: Kenneth A. Bandy, Vincent J. Carlos, Mark D. Levy, Sara L. Lucas, Timothy C. Milmore, Matthew C. Nicholls, Jason Nowakowski
  • Patent number: 7052823
    Abstract: A method of manufacturing an electroconductive film subject to edge curl due to volume contraction after baking includes sequentially repeating a film-forming step of forming a film containing a photosensitive material and an electroconductive material therein and an exposure step of irradiating a light onto a desired region of the film for a plurality of times to laminate the films. The latent images of the respective layers are integrated. The resulting latent image is developed by removing a non-latent image region of the laminate film after the laminate film is formed. Finally, the developed image is baked. The sequential repetition of the film-forming step and the exposure step act to counteract edge curl formed by volume contraction after baking.
    Type: Grant
    Filed: July 23, 2003
    Date of Patent: May 30, 2006
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yoshimi Uda, Kazuya Ishiwata, Shinsaku Kubo, Yasuyuki Watanabe
  • Patent number: 7045259
    Abstract: A system and method are described for modifying an exposure image in a radiation sensitive layer by treating the exposure image with a heterogeneous and non-uniform post exposure thermal treatment. The treatment may comprise providing different portions of the exposure feature, such as different exposure features or critical dimensions, with different thermal fluxes from a thermal modification system, such as a post exposure bake oven or hot plate configured to provide different thermal fluxes. The thermal modification system may comprise one or more adjustable spacers to adjust a radiant energy flux from a thermal energy source to the radiation sensitive layer by adjusting a separation distance between the source and the layer.
    Type: Grant
    Filed: September 26, 2001
    Date of Patent: May 16, 2006
    Assignee: Intel Corporation
    Inventors: Takeshi Ohfuji, Hiroyuki Inomata, Shiho Sasaki, Masa-aki Kurihara
  • Patent number: 7041228
    Abstract: A substrate comprising at least a first and a second coating layer on one surface of the substrate is for nanoimprint lithography, the first coating layer has a positive resist and the second coating layer has a negative resist. A process in connection with nanoimprint lithography on the substrate impresses a pattern of nanometer size in a first stage into the second coating layer by a template, following which the first coating layer, in a second stage, is exposed to a chiefly isotropic developing method on surfaces thereof that have been exposed in connection with the first stage, a method for developing and material for the first and second coating layers being selected so that the first coating layer is developed more quickly than the second coating layer, so that an undercut profile is obtained in the coating layers.
    Type: Grant
    Filed: April 10, 2001
    Date of Patent: May 9, 2006
    Assignee: Obducat Aktiebolag
    Inventor: Babak Heidari
  • Patent number: 7033735
    Abstract: A method is described for reducing the space width of holes in a first resist pattern and simultaneously removing unwanted holes to change the pattern density in the resulting second pattern. This technique provides holes with a uniform space width as small as 100 nm or less that is independent of pattern density in the second pattern. A positive resist is patterned to form holes with a first pattern density and first space width. A water soluble negative resist is coated over the first resist and selectively exposed to form a second patterned layer consisting of water insoluble plugs in unwanted holes in the first pattern and a thin water insoluble layer on the first resist pattern in unexposed portions. The plugs may form dense and isolated hole arrays while the thin insoluble layer reduces space width to the same extent in remaining holes in the second pattern.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: April 25, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Bang-Chien Ho, Jian-Hong Chen
  • Patent number: 7029799
    Abstract: There is provided a method which forms master masks used when a pattern of size larger than a region which can be exposed at one time is exposed on a to-be-exposed object. The pattern of the size larger than the region which can be exposed at one time is divided into a region of low repetitiveness and a region of high repetitiveness. A pattern of the region of low repetitiveness is drawn on at least one first master mask. Further, a pattern of the region of high repetitiveness is drawn on at least one second master mask.
    Type: Grant
    Filed: April 9, 2002
    Date of Patent: April 18, 2006
    Assignees: Kabushiki Kaisha Toshiba, Dai Nippon Printing Co., Ltd.
    Inventors: Suigen Kyoh, Soichi Inoue
  • Patent number: 7027227
    Abstract: A method for forming a three-dimensional structure made of a photosensitive material on a substrate includes the steps of determining a film thickness of the photosensitive material necessary to form the desired three-dimensional structure, comparing a predetermined maximum film thickness with the film thickness determined by the determining step, and applying, when the film thickness determined by the determining step is greater than the predetermined maximum film thickness, the photosensitive material within the maximum film thickness plural times until the photosensitive material has the film thickness on the substrate.
    Type: Grant
    Filed: January 22, 2004
    Date of Patent: April 11, 2006
    Assignee: Canon Kabushiki Kaisha
    Inventors: Keiko Chiba, Kenichiro Mori
  • Patent number: 7026254
    Abstract: A precursor that may be imaged by heat is made up of a substrate, for example a copper board, and a composite layer structure composed of two layers. Preferably, the first layer is composed of an aqueous developable polymer mixture containing a photothermal conversion material, which is contiguous to the substrate. The second layer of the composite is composed of one or more non-aqueous soluble polymers, which are soluble or dispersible in a solvent which does not dissolve the first layer. The precursor is exposed with an infrared laser or a thermal print head, and upon aqueous development, the exposed regions are removed, revealing regions of the substrate surface able to be etched or otherwise treated. The second layer may also contain a photothermal conversion material. Alternatively, the composite layer may be free of photothermal conversion material when thermal imaging is carried out using a thermal print head. The precursor may be used, for example, as a mask precursor or electronic part precursor.
    Type: Grant
    Filed: April 2, 2003
    Date of Patent: April 11, 2006
    Assignee: Eastman Kodak Company
    Inventors: Kevin Barry Ray, Anthony Paul Kitson
  • Patent number: 7022607
    Abstract: To provide a mask able to reduce the thickness of a membrane and maintain the mask strength and a method of producing a semiconductor device able to form a fine pattern with a high accuracy and a method of producing the mask. A mask comprising a thin film, holes formed at the thin film through which a charged particle beam (preferably an electron beam) passes, a support layer formed at one side of the thin film, and apertures formed at a larger size than the holes at least at portions of said holes of said support layer and a method of producing the same and a method of producing a semiconductor device including a lithography step using the same.
    Type: Grant
    Filed: November 15, 2002
    Date of Patent: April 4, 2006
    Assignee: Sony Corporation
    Inventor: Masaki Yoshizawa
  • Patent number: 7018753
    Abstract: A method of fabricating integrated circuits according to a first design by imaging a first layer on a substrate using a first mask having a block of first patterns in common with a second design, but without any other patterns of the first or second designs and imaging a second layer on the substrate using a second mask having a block of second patterns unique to the first design and at least one third layer pattern. The block of first patterns is repeatedly exposed in a first grid and the block of second patterns is repeatedly exposed in a second grid, each without overlap in the corresponding layer. The grids are aligned such that the integrated circuits and test structures in scribe lines between the integrated circuits are properly formed on the substrate. The first patterns can be for large fields and the second patterns can be for small fields.
    Type: Grant
    Filed: May 5, 2003
    Date of Patent: March 28, 2006
    Assignee: LSI Logic Corporation
    Inventors: David J. Sturtevant, Duane B. Barber, Ann I. Kang
  • Patent number: 7018548
    Abstract: A high-precision conductive thin film pattern having a high aspect ratio and a method of forming the same are provided. Further, a method of manufacturing a thin film magnetic head, a thin film inductor, and a micro device each including such a conductive thin film pattern is provided. Since a stacked layer structure including two conductive layer patterns formed by plating growth using an underfilm pattern as an electrode film and an intermediate conductive layer pattern sandwiched by the two conductive layer patterns is provided, a thicker conductive thin film pattern is obtained. An intermediate conductive layer covering a first resist frame is formed and, after that, a second resist frame is formed in a position corresponding to the first resist frame. Consequently, without causing inter-mixing, the first and second resist frames can be stacked. Thus, a thicker conductive thin film pattern can be formed easily with high precision.
    Type: Grant
    Filed: July 11, 2003
    Date of Patent: March 28, 2006
    Assignee: TDK Corporation
    Inventor: Akifumi Kamijima
  • Patent number: 7018748
    Abstract: In a process for producing hard masks, an initiator layer that contains an initiator component is applied to a substrate. Then, a photoresist is used to produce a pattern on the initiator layer, in the trenches of which pattern the initiator layer is uncovered. Then, a curable hard mask material is applied and selectively cured, so that only those sections of the hard mask material that adjoin the initiator layer are cured. Finally, uncured hard mask material is removed using a solvent, and at the same time the lands formed from the resist are also removed. The pattern obtained in this way can then be transferred to the substrate, for example using plasma.
    Type: Grant
    Filed: April 29, 2003
    Date of Patent: March 28, 2006
    Assignee: InfineonTechnologies AG
    Inventors: Michael Sebald, Ernst-Christian Richter
  • Patent number: 7018778
    Abstract: A process for forming a bipolar transistor where the doping implantation of the extrinsic base regions does not affect the emitter doping levels. The techniques is to not remove the photoresist layer used to define the poly emitter contact. The photoresist layer for defining the extrinsic base regions overlays the photoresist layer over the emitter poly. When the base photoresist is processed to expose the base regions the photoresist over the emitter poly remains in tact. In this arrangement the base implantation is prevented from driving through the emitter poly and affecting the doping levels in the emitter.
    Type: Grant
    Filed: March 24, 2003
    Date of Patent: March 28, 2006
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Steven M. Leibiger, Laurence M. Szendrei, Mark A. Doyle
  • Patent number: 7014965
    Abstract: A photolithography method for reducing effects of lens aberration. A photolithography apparatus is provided with a first reticle therein, having at least one first rectangular pattern thereon, a first photolithography is performed on a wafer by the photolithography apparatus to transfer the first rectangular pattern thereonto by simultaneously moving the first reticle and the wafer in a direction parallel to the short sides of the first rectangular pattern. The first reticle is replaced with a second reticle having at least one second rectangular pattern thereon and a second photolithography is performed by the photolithography apparatus to transfer the second rectangular pattern onto the wafer by simultaneously moving the second reticle and the wafer in a 90° plus or minus rotation in a direction parallel to the short sides of the second rectangular pattern.
    Type: Grant
    Filed: August 13, 2003
    Date of Patent: March 21, 2006
    Assignee: Nanya Technology Corporation
    Inventors: Chun-Cheng Liao, Yuan-Hsun Wu
  • Patent number: 7005215
    Abstract: A mask fabrication and repair technique including multiple exposures is provided. In this multiple exposure technique, the first exposure can define the critical dimensions (CDs) of the shapes for the mask. A subsequent exposure can eliminate isolated defects and significantly reduce the size of defects proximate to the desired shapes on the mask. Because similar processes (i.e. forming, exposing, and developing a photoresist layer) are used for creating and repairing the mask, certain repair-related defects, such as phase and transmission defects, can be minimized. Wafer repair can also be performed using the same multiple exposure technique.
    Type: Grant
    Filed: October 28, 2002
    Date of Patent: February 28, 2006
    Assignee: Synopsys, Inc.
    Inventor: Christophe Pierrat
  • Patent number: 7005220
    Abstract: A method for structuring a lithograph mask by forming a cured, electrically-conductive layer on a mask structure having a radiation-transmissive substrate and a mask layer at least in portions of the surface of the radiation-transmissive substrate before applying a resist layer, so that during a subsequent irradiation of the resist layer by means of an electronic printing, the electrically conductive layer ensures a good charge elimination. By using a cured, electrically conductive layer, no intermixing effects between the electrically-conductive layer and the resist layer occur, and the electrically-conductive layer will be stable during subsequent development steps and not stripped off.
    Type: Grant
    Filed: June 19, 2003
    Date of Patent: February 28, 2006
    Assignee: Infineon Technologies AG
    Inventors: Klaus Elian, Armelle Vix
  • Patent number: 7005241
    Abstract: A process for making a circuit board comprises the following steps of: half-etching a metal layer formed on an insulating substrate by means of a first masking which is positioned on an upper surface of the metal layer; applying a positive liquid resist on the half-etched metal layer from an upper side of the first masking; exposing the positive liquid resist with parallel light from the upper side of the first masking and developing the positive liquid resist in such a manner that a part of the positive liquid resist located under the first masking is protected to be unexposed and undeveloped; etching again the metal layer by means of a second masking composed of the first masking and the protected positive liquid resist to form a conductive pattern on the insulating substrate; and removing the first masking and the second masking from the metal layer.
    Type: Grant
    Filed: April 13, 2004
    Date of Patent: February 28, 2006
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Katsuya Fukase, Toyoaki Sakai
  • Patent number: 7001698
    Abstract: A chromium-containing half-tone phase-shift photomask comprising coarse and dense patterns coexisting in a plane is prepared by a series of pattern-forming steps including forming a resist layer on a photomask blank, exposing and patterning said resist layer, developing, etching said photomask blank and removing said resist layer. Patterns for transferring onto a wafer are formed on the photomask blank by a dry-etching method comprising dry-etching a chromium-containing half-tone phase-shift film utilizing etching gas comprised of mixed gas including (a) reactive ion etching gas, containing an oxygen-containing gas and a halogen-containing gas, and (b) reducing gas added to the gas component (a).
    Type: Grant
    Filed: November 14, 2003
    Date of Patent: February 21, 2006
    Assignees: Ulvac Coating Corporation, Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takaei Sasaki, Noriyuki Harashima, Satoshi Aoyama, Shouichi Sakamoto
  • Patent number: 6998223
    Abstract: A photosensitive resist layer is formed on one surface of a single-polarized ferroelectric substance having nonlinear optical effects. The resist layer has properties such that, when light is irradiated to the resist layer, only exposed areas of the resist layer or only unexposed areas of the resist layer become soluble in a developing solvent. The resist layer is then exposed to near-field light in a periodic pattern with a device, which receives exposure light and produces the near-field light in the periodic pattern. The resist layer is then developed to form a periodic pattern. A periodic electrode is then formed on the one surface of the ferroelectric substance by utilizing the periodic pattern of the resist layer as a mask, the periodic electrode being formed at positions corresponding to opening areas of the mask.
    Type: Grant
    Filed: August 28, 2000
    Date of Patent: February 14, 2006
    Assignee: Fuji Photo Film Co., Ltd.
    Inventors: Yasukazu Nihei, Masayuki Naya
  • Patent number: 6994939
    Abstract: A method and system of making a mask with a transparent substrate thereon is provided. A first resolution enhancement structure is formed on the first portion of the transparent substrate. A second resolution enhancement structure is formed on a second portion of the transparent substrate, with the second resolution enhancement structure different from the first resolution enhancement structure.
    Type: Grant
    Filed: October 29, 2002
    Date of Patent: February 7, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kouros Ghandehari, Jean Y. Yang, Christopher A. Spence
  • Patent number: 6995047
    Abstract: A mask containing apertures therein which is used for fabricating a channel of a thin film transistor (TFT), wherein the pixel charging time for a TFT in a high-resolution liquid crystal display (LCD) device is reduced by minimizing the length of the channel in the TFT when the active region is made of amorphous silicon. The length of the channel can be minimized by exposing light through the apertures is an exposure mask when forming the channel.
    Type: Grant
    Filed: April 19, 2002
    Date of Patent: February 7, 2006
    Assignee: LG.Philips LCD Co., Ltd.
    Inventor: Kwang-Jo Hwang
  • Patent number: 6994949
    Abstract: A dual damascene process is disclosed which reduces capacitance increases caused by excess and unnecessary remnants of an etching stop layer and which also improves multi-level interconnect structures by removing the etching stop layer except for a portion that surrounds the via hole. This reduces or eliminates capacitance increase and avoids erosion of underlying interlayer insulating layers during formation of an upper, wider trench.
    Type: Grant
    Filed: February 4, 2002
    Date of Patent: February 7, 2006
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sung-Kwon Lee, Sang-Ik Kim
  • Patent number: 6993742
    Abstract: A proximity correction tool receives an indication of a feature in a lithographic design. The proximity correction tool predicts a film edge placement for the feature in a resist film based at least in part on thermal proximity effects in the resist film.
    Type: Grant
    Filed: August 8, 2003
    Date of Patent: January 31, 2006
    Assignee: Intel Corporation
    Inventors: David S. Fryer, Vivek K. Singh, Thanh N. Phung
  • Patent number: 6989334
    Abstract: The occurrence of a package crack in the back vicinity of a die pad is restrained by making the outward appearance of the die pad of a lead frame smaller than that of a semiconductor chip which is mounted on it, and also the occurrence of a package crack in the main surface vicinity of the semiconductor chip is restrained by forming a layer of organic material with good adhesion property with the resin that constitutes the package body on the final passivation film (final passivation film) that covers the top layer of conductive wirings of the semiconductor chip.
    Type: Grant
    Filed: May 15, 2003
    Date of Patent: January 24, 2006
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Yoshinori Miyaki, Hiromichi Suzuki, Kazunari Suzuki, Takafumi Nishita, Fujio Ito, Kunihiro Tsubosaki, Akihiko Kameoka, Kunihiko Nishi
  • Patent number: 6982022
    Abstract: Disclosed is a process for forming a novel ink jet printhead which comprises: (a) providing a lower substrate in which one surface thereof has an array of drop generating elements and addressing electrodes formed thereon; (b) depositing onto the release surface of an intermediate film support a photopatternable layer comprising a precursor polymer which is a phenolic novolac resin having glycidyl ether functional groups; (c) prebaking the photopatternable layer to dry, semi-solid condition; (d) laminating the dry, semi-solid layer to the surface of the lower substrate under heat and pressure and separating it from the release surface of the intermediate film support; (e) exposing the photopatternable layer to actinic radiation in an imagewise pattern corresponding to ink nozzles and developing to form a nozzle plate section, and (f) removing the precursor polymer from the unexposed areas, thereby forming ink nozzle recesses which are aligned to communicate with the drop generating elements and terminal ends o
    Type: Grant
    Filed: May 21, 2003
    Date of Patent: January 3, 2006
    Assignee: Xerox Corporation
    Inventors: Shan Clark, Gary Kneezel, Ram Narang, Bidan Zhang, Almon Fisher
  • Patent number: 6979604
    Abstract: The present invention relates to a method of forming a pattern on a substrate and a method of manufacturing a liquid crystal display panel using the same. In order to decrease stitch defect, the shot boundary lines for respective layers of patterns do not overlap each other to be dispersed. Specifically, according to a method of forming patterns of the present invention, after a first material layer is first formed on a substrate, a first pattern is formed by performing a first photo etching including divisional light exposure with at least two areas across at least one shot boundary line on the first material layer. Subsequently, after a second material layer is formed on the first pattern, a second pattern is formed by performing a second photo etching including divisional light exposure with at least two areas across at least one shot boundary line on the second material layer. The shot boundary line in the second photo etching is spaced apart from the shot boundary line in the first photo etching.
    Type: Grant
    Filed: March 5, 2002
    Date of Patent: December 27, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Mi Tak, Woon-Yong Park, Jung-Ho Lee, Mun-Pyo Hong, Kyuha Chung
  • Patent number: 6974659
    Abstract: A method for protecting a semiconductor process wafer surface from contacting thermally degraded photoresist including providing a semiconductor process wafer having a process surface; forming a protective layer over selected areas of the process surface said protective layer including a resinous organic material having a glass transition temperature (Tg) that is about greater than a thermal treatment temperature; forming a photoresist layer over at least a portion of the protective layer to include a photolithographic patterning process; and subjecting the semiconductor process wafer to the thermal treatment temperature.
    Type: Grant
    Filed: January 16, 2002
    Date of Patent: December 13, 2005
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Yuan Su, Chia-Fu Lin, Hsin-Hui Lee, Yen-Ming Chen, Kai-Ming Ching, Li-Chih Chen