Abstract: Masks for patterning material layers of semiconductor devices, methods of patterning and methods of manufacturing semiconductor devices, and lithography systems are disclosed. A lithography mask includes a pattern of alternating lines and spaces, wherein the lines and spaces comprise different widths. When the lithography mask is used to pattern a material layer of a semiconductor device, the pattern of the material layer comprises alternating lines and spaces having substantially the same width.

Abstract: Provided methods for forming a pattern using electron beam and cell masks for electron beam lithography. The methods may include forming a resist layer on a substrate, the resist layer including a first region, a second region surrounding the first region, and a third region surrounding the second region. The second may be irradiated with electron beam at a first dose, and the third region may be irradiated with an electron beam at a second dose less than the first dose. The cell mask may include a mask substrate and a shielding region disposed on the mask substrate. A transmitting region may extend a distance from the shielding region. A gray pattern region may be disposed around the transmitting region. The gray pattern region may include patterns having a pitch smaller than a resolution limit.

Abstract: A method for adjusting the lateral critical dimension (i.e., length and width) of a feature formed in a layer on a substrate using a dry etching process. One or more thin intermediate sub-layers are inserted in the layer within which the feature is to be formed. Once an intermediate sub-layer is reached during the etching process, an etch process is performed to correct and/or adjust the lateral critical dimensions before etching through the intermediate sub-layer and continuing the layer etch.

Abstract: It is an object of the present invention to provide a method for manufacturing a substrate having film patterns such as an insulating film, a semiconductor film, and a conductive film in simple processes. It is another object of the invention to provide a method for manufacturing a semiconductor device with high throughput and high yield at low cost.

Abstract: A method of forming a pattern including a first pattern portion having a first minimum dimension and a second pattern portion having a second minimum dimension includes a first exposure step of performing exposure using a Levenson-type mask and a second exposure step of performing exposure using a half tone-type mask. When second minimum dimension is 1.3 time or more than the first minimum dimension, the exposure amount of the second exposure step is set to be equal to or smaller than the exposure amount of the first exposure step.

Abstract: A mask having features formed by self-organizing material, such as diblock copolymers, is formed on a partially fabricated integrated circuit. Initially, a copolymer template, or seed layer, is formed on the surface of the partially fabricated integrated circuit. To form the seed layer, diblock copolymers, composed of two immiscible blocks, are deposited in the space between copolymer alignment guides. The copolymers are made to self-organize, with the guides guiding the self-organization and with each block aggregating with other blocks of the same type, thereby forming the seed layer. Next, additional, supplemental diblock copolymers are deposited over the seed layer. The copolymers in the seed layer guide self-organization of the supplemental copolymers, thereby vertically extending the pattern formed by the copolymers in the seed layer.

Abstract: A non-volatile bistable nano-electromechanical switch is provided for use in memory devices and microprocessors. The switch employs carbon nanotubes as the actuation element. A method has been developed for fabricating nanoswitches having one single-walled carbon nanotube as the actuator. The actuation of two different states can be achieved using the same low voltage for each state.

Abstract: A method for forming a fine contact hole of a semiconductor device comprises performing two-step etching processes using a first exposure mask including a plurality of rectangular light transmitting regions each having a given pitch and a second exposure mask including a plurality of rectangular light transmitting regions arranged a shielding region of the first exposure mask with a ‘cross (+)’ shape in the center of rectangular light transmitting regions of the second exposure mask. Each of four corner regions of the light transmitting regions of the first exposure mask is overlapped with four corner regions of rectangular light transmitting regions of the second exposure mask. As a result, the fine contact hole pattern obtained by the method has a uniform size.

Abstract: A reticle set, includes a first photomask having a circuit pattern provided with first and second openings provided adjacent to each other sandwiching a first opaque portion, and a monitor mark provided adjacent to the circuit pattern; and a second photomask having a trim pattern provided with a second opaque portion covering the first opaque portion in an area occupied by the circuit pattern and an extending portion connected to one end of the first opaque portion and extending outside the area when the second photomask is aligned with a pattern delineated on a substrate by the first photomask.

Abstract: A method for exposing photoresist film of semiconductor device is disclosed. In accordance with the method, wafer is sequentially shifted the wafer by a predetermined distance so that the exposed regions before and after each shift have an overlapping region having an area larger than or equal to that of the die pattern to prevent defects on the exposure mask from being transcribed to the photoresist film.

Abstract: First, a first exposure process is performed using dipole illumination with only a grating-pattern forming region as a substantial object to be exposed. Next, a second exposure process is performed with only a standard-pattern forming region as a substantial object to be exposed. A development process is then performed to obtain a resist pattern. A mask for the first exposure process is such that a light blocking pattern is formed on the whole surface of a standard-pattern mask part corresponding to the standard-pattern forming region. A mask for the second exposure is such that a light blocking pattern is formed on the whole surface of a grating-pattern mask part corresponding to the grating-pattern forming region.

Abstract: A method of forming a stacked structure in an electronic device, where a photoresist for performing multi-patterning processes is used. Also, a method of manufacturing a FED in which different structures can be multi-patterned by using a single photoresist mask. The photoresist has a solubility to a solvent by heat-treatment after exposure, and a complicated structure can be formed using the photoresist.

Abstract: A method for forming high resolution patterns on a substrate surface is disclosed. A photolithographic patterning tool is loaded with a substrate having a photoimagable layer. Multiple exposures to using interference patterns and developments are performed on the photoimagable layer to define a composite line pattern in the photoimagable layer. The composite line pattern having a greater pitch density than possible with single exposure with the same photolithographic patterning tool. The lines of the composite line pattern are selectively cut or trimmed at a plurality of locations to define a desired pattern in the photoimageable layer. The cuts can themselves be achieved with a plurality of photomasks or exposure to direct write tools to achieve densities beyond that allowed by k1>0.25 limit.

Abstract: A device manufacturing method includes a transfer of a pattern from a patterning device onto a substrate. The device manufacturing method further includes transferring a pattern of a main mark to a base layer for forming an alignment mark; depositing a pattern receiving layer on the base layer; in a first lithographic process, aligning, by using the main mark, a first mask that includes a first pattern and a local mark pattern, and transferring the first pattern and the local mark pattern to the pattern receiving layer; aligning, by using the local mark pattern, a second mask including a second pattern relative to the pattern receiving layer; and in a second lithographic process, transferring the second pattern to the pattern receiving layer; the first and second patterns being configured to form an assembled pattern.

Abstract: A method for patterning and forming very small structures on a substrate such as a wafer. The process uses a difference in surface energy between a mask and the substrate to selectively deposit a hard mask material such as a metal onto the surface of the substrate. The mask can be formed extremely thin, such as only an atomic mono-layer thick, and can be patterned by ion beam photolithography. The pattern can, therefore, be formed with extremely high resolution. The thin mask layer can be constructed of various materials and can be constructed of perfluoropolyether diacrylate (PDA), which can be dip coated to and exposed to form a desirable positive photoresist mask layer.

Abstract: A method and system for patterning a substrate using a dual-tone development process is described. The method and system comprise using a resist material having a polymer backbone with a plurality of protecting groups attached thereto to improve process latitude and critical dimension uniformity for the dual-tone development process.

Abstract: A method for detecting hidden defects and patterns, the method includes: receiving an object that comprises an opaque layer positioned above an intermediate layer; defining an energy band in response to at least one characteristic of the opaque layer and at least one characteristic of a scanning electron microscope; illuminating the object with a primary electron beam; and generating images from electrons that arrive to a spectrometer having an energy within the energy band.

Abstract: A touch panel apparatus includes a position detection electrode formed in a touch region and made of ITO, and a wiring portion provided in a frame region and electrically connected to the position detection electrode. The wiring portion has a first pattern film extended from the position detection electrode and made of ITO, a second pattern film laminated on the first pattern film and made of IZO, and a third pattern film laminated on the second pattern film and made of silver or a silver alloy.

Abstract: In a resist reflow measurement key, and method of fabricating a fine pattern of a semiconductor device using the same, the resist reflow measurement key includes a first reflow key including a plurality of first pattern elements each having a first pattern with a first radius of curvature located on a first side of a first center line and a second pattern with a second radius of curvature located on a second side of the first center line, and a second reflow key including a plurality of second pattern elements each having a third pattern with a third radius of curvature located on a first side of a second center line and a fourth pattern with a fourth radius of curvature located on a second side of the second center line, the second reflow key being formed on a same plane of a substrate as the first reflow key.

Abstract: A hybrid mask set for exposing a plurality of layers on a semiconductor substrate to create an integrated circuit device is disclosed. The hybrid mask set includes a first group of one or more multi-layer masks (MLMs) for a first subset of the plurality of layers. Each MLM includes a plurality of different images for different layers, the images being separated by a relatively wide image spacer. The hybrid mask set also includes a first group of one or more production-ready masks for a second subset of the plurality of layers. Each production-ready mask includes a plurality of similar images for a common layer, each image being separated by a relatively narrow scribe street.

Abstract: A method of manufacturing a semiconductor device includes the following processes. A first resist layer covering an etching object is patterned to form a first resist pattern. Then, a filling layer that covers the first resist pattern and has a flat upper surface is formed. Then, a second resist layer covering the flat upper surface is patterned to from a second resist pattern.

Abstract: Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated circuit, are formed by processing a substrate through a mask. The mask is formed by patterning a photoresist layer which simultaneously defines mask elements corresponding to features in the array, interface and periphery areas of the integrated circuit. The pattern is transferred to an amorphous carbon layer. Sidewall spacers are formed on the sidewalls of the patterned amorphous carbon layer. A layer of protective material is deposited and then patterned to expose mask elements in the array region and in selected parts of the interface or periphery areas. Amorphous carbon in the array region or other exposed parts is removed, thereby leaving a pattern including free-standing, pitch multiplied spacers in the array region.

Abstract: In an exposure step, a combination of a first photomask and a second mask is used. The first mask has a real pattern corresponding to the pattern actually formed on the film to be processed, and a dummy pattern added for controlling pattern pitch in the first photomask within a prescribed range; and the second photomask has a pattern isolating a real-pattern-formed region from a dummy-pattern-formed region. In forming the pattern, after forming a film to be processed on a substrate, a first mask is formed on the film to be processed, by lithography, using the first photomask, and a second mask is formed on the film to be processed, by lithography, using the second photomask. Thereafter, the film to be processed is etched off and removed using the first and second masks as masks to form the pattern.

Abstract: There is provided a novel nano material cluster structure. The nano material cluster structure comprises a conductor block and a plurality of first nano material strands protruding from a surface of the conductor block. The first nano material strands extend from the conductor block in a coplanar relationship. A novel method of preparing a nano material cluster structure is also provided. The method comprises providing a layered structure having multiple layers on a substrate. The multiple layers comprise a layer having nano material strands therein. The method also comprises patterning the layered structure to define one or more recesses. The nano material strands are partially exposed through said one or more recesses. The method further comprises filling the one or more recesses with a conductive material to enclose the partially exposed nano material strands.

Abstract: A method of forming a pattern in at least one device layer in or on a substrate comprises: coating the device layer with a first photoresist layer; exposing the first photoresist using a first mask; developing the first photoresist layer to form a first pattern on the substrate; coating the substrate with a protection layer; treating the protection layer to cause a change therein where it is in contact with the first photoresist, to render the changed protection layer substantially immune to a subsequent exposure and/or developing step; coating the substrate with a second photoresist layer; exposing the second photoresist layer using a second mask; and developing the second photoresist layer to form a second pattern on the substrate without significantly affecting the first pattern in the first photoresist layer, wherein the first and second patterns together define interspersed features having a spartial frequency greater than that of the features defined in each of the first and second patterns separately.

Abstract: There is provided a semiconductor device including a wafer and a focus monitoring pattern formed on the wafer. The focus monitoring pattern having at least one pair of first and second patterns, and the first pattern has an unexposed region surrounded by an exposed region, and the second pattern has an exposed region surrounded by an unexposed region. In addition, the present invention provides a method of fabricating a semiconductor device comprising the steps of forming at least one pair of first and second patterns on a wafer, the first pattern having an unexposed region surrounded by an exposed region, the second pattern having an exposed region surrounded by an unexposed region, and checking a focusing condition on exposure by measuring widths of the first and second patterns formed on the wafer.

Abstract: A method of the present invention is presented for deep etching of features on a surface. In one embodiment, the method includes providing a substrate having a surface selected to undergo a feature etching process and coating the substrate surface with a protective layer and an imprintable layer. The coated substrate is then subjected to a feature imprinting and etching process. Subsequent to the feature etching process, exposed portions of the protective layer are removed, exposing a well-defined, topographically patterned substrate. In addition, an apparatus for undergoing a feature etching process is disclosed. The apparatus comprises a substrate, an imprintable layer selected to undergo an imprinting process, and a protective layer positioned between the substrate and the imprintable layer.

Abstract: Antireflective coating compositions and related polymers are disclosed.

Abstract: An exposure method is disclosed. A wafer coated with a photoresist layer having an exposure threshold dose is provided. The wafer has at least a central region and a peripheral region. Then, a compensating light beam having a first dose directs on the photoresist layer within the peripheral region. Next, a patterned light beam having a second dose is then projected, in a step-and-scan manner, onto the photoresist layer, thereby exposing the photoresist layer. The total dose of the first energy and the second energy is above than the exposure threshold dose.

Abstract: There is disclosed a rework process for a photoresist film over a substrate having at least an antireflection silicone resin film and the photoresist film over the silicone resin film comprising: at least removing the photoresist film with a solvent while leaving the silicone resin film unremoved; and forming a photoresist film again over the silicone resin film. In this case, the substrate over which the photoresist film is reworked can have an organic film under the silicone resin film. There can be provided a rework process for a photoresist film that can be conducted more easily at lower cost.

Abstract: A method of producing an address plate comprising the steps of; coating a layer of conducting inorganic material onto a substrate, coating a layer of photoresist above this layer of conductive material and curing this layer, exposing, through a mask, the desired pattern of the conductors onto the layer of photoresist, developing the photoresist and etching the layer of the conductive material and coating the resulting etched layer with a layer of dielectric material. A further layer of photoresist is then applied, the thickness of this layer being equal to the desired height of a relief pattern, curing the further layer of photoresist, exposing, through a second mask, the desired structure of the relief pattern onto the layer of photoresist, developing the photoresist and allowing the layer to dry. This results in spacers raised above the layer of dielectric material.

Abstract: A radiation detector using gas amplification includes: a first electrode pattern which is formed on a first surface of an insulating member and has a plurality of circular openings; and a second electrode pattern which is formed on a second surface of the insulating member opposite to the first surface thereof and has convex portions of which respective forefronts are exposed to centers of the openings of the first electrode pattern; wherein a predetermined electric potential is set between the first electrode pattern and the second electrode pattern; wherein edges of the first electrode pattern exposing to the openings are shaped in respective continuous first curved surfaces by covering the edges thereof with a first solder material.

Abstract: An operation for forming a trench after forming a via hole includes an operation for exposing a region for forming the via hole to light and an operation for exposing a region for forming the interconnect trench. More specifically, even if chemically amplified resist is buried in the via hole after the via hole is formed, then the region for forming of via hole is exposed to light again, so that the inside of the via hole is fully exposed to light. This allows removing the buried resist from the regions in via hole exposed to light, or namely the region and the region, with a developing solution, exposing at least a portion of the inner wall of the via hole to obtain the trench having a desired structure.

Abstract: A method for manufacturing an integrated circuit devices. The method includes providing a substrate, which includes an opaque film overlying the substrate, an overlying negative photoresist layer, a stop layer overlying the negative photoresist layer, and a positive photoresist layer overlying the stop layer. The method includes patterning the positive resist layer to form one or more window openings in the positive photoresist layer. The method also includes removing the exposed stop layer within the one or more window openings to expose a portion of the negative photoresist layer and patterning the exposed portion of the negative photoresist layer. The method includes developing the exposed portion of the negative photoresist layer and removing exposed portions of the opaque layer to expose an underlying portion of the substrate. The method further includes removing any remaining portions of the negative photoresist layer, stop layer, and positive photoresist layer to provide a patterned mask.

Abstract: There is disclosed a rework process for a photoresist film over a substrate having at least a first antireflection silicone resin film and the photoresist film over the first silicone resin film comprising: at least removing the photoresist film with a solvent while leaving the first silicone resin film unremoved; forming a second antireflection silicone resin film over the first silicone resin film; and forming a photoresist film again over the second silicone resin film. There can be provided a rework process for a photoresist film that can be conducted more easily at lower cost and provide more certainly an excellent resist pattern.

Abstract: According to an aspect of the invention, there is provided a pattern forming method including forming a lower layer organic film on a substrate, forming an upper layer resist film containing an inorganic element on the lower layer organic film, exposing a pattern on the upper layer resist film and performing development processing to form an opening in the upper layer resist film, supplying a coating forming agent to the upper layer resist film having the opening formed therein to embed and form a coating film in the opening of the upper layer resist film, thermally contracting the coating film to narrow the opening of the upper layer resist film, removing the coating film by dry etching processing and subsequently selectively removing the lower layer organic film with the upper layer resist film being used as a mask, thereby collectively processing the coating film and the lower layer organic film.

Abstract: A method for forming fine patterns of a semiconductor device employs a double patterning characteristic using a mask for forming a first pattern including a line pattern and a mask for separating the line pattern, and a reflow characteristic of a photoresist pattern.

Abstract: A stack of a second photoresist having a second photosensitivity and a first photoresist having a first photosensitivity, which is greater than second photosensitivity, is formed on a substrate. A first pattern is formed in the first photoresist by a first exposure and a first development, while the second photoresist underneath remains intact. A second pattern comprising an array of lines is formed in the second photoresist. An exposed portion of the second photoresist underneath a remaining portion of the first photoresist forms a narrow portion of a line pattern, while an exposed portion of the second photoresist outside the area of the remaining portions of the photoresist forms a wide portion of the line pattern. Each wide portion of the line pattern forms a bulge in the second pattern, which increases overlay tolerance between the second pattern and the pattern of conductive vias.

Abstract: Embodiments of the present disclosure provide a display substrate, a method of manufacturing the same and a display panel having the same. In an embodiment, a switching element is formed near a crossing area of a gate line and a data line to connect with the gate and data lines. A color filter layer includes a light-blocking partition pattern defining a light-transmitting area and a color filter disposed on the light-transmitting area. A light-blocking partition pattern includes an insulation pattern which covers the switching element, the gate line and the data line along a normal line direction of a base substrate and a light-blocking layer pattern formed from substantially the same pattern as an insulation layer pattern on an upper surface of the insulation layer pattern. A pixel electrode layer is disposed on the color filter to be connected to the switching element.

Abstract: A method of manufacturing a semiconductor device according to one embodiment, includes: forming a first mask material film on a workpiece film formed on a semiconductor substrate; forming a resist pattern on the first mask material film; forming a second mask material film having a desired film thickness on the first mask material film so as to cover the resist pattern; carrying out etchback of the second mask material film so as to expose the resist pattern and the first mask material film; processing the resist pattern and the first mask material film simultaneously which are exposed, while leaving the second mask material film of which etchback is carried out; and processing the workpiece film which exposes under the first mask material film.

Abstract: A semiconductor device manufacturing method has forming a first resist pattern on the semiconductor substrate, and then, forming a first pattern on the semiconductor substrate by the use of the first resist pattern, and forming a second resist pattern on the semiconductor substrate by using an imprinter, and then, forming a second pattern on the semiconductor substrate by the use of the second resist pattern. The forming the first pattern, the first pattern smaller than a design pattern corresponding to the design data for forming a plurality of patterns on a semiconductor substrate being formed.

Abstract: A method for fabricating an image sensor is disclosed. First, a semiconductor substrate is provided, in which a photosensitive region is defined on the semiconductor substrate. At least one photosensitive material is then formed on the semiconductor substrate, and a first exposure process is performed to form a tapered pattern in the photosensitive material. A second exposure process is performed to form a straight foot pattern in the photosensitive material, and a developing process is performed to remove the tapered pattern and straight foot pattern to form the photosensitive material into a plurality of photosensitive blocks. A reflow process is conducted thereafter to form the photosensitive blocks into a plurality of microlenses.

Abstract: A method of manufacturing a semiconductor device includes: forming a negative resist film having an annular pattern that masks an outer peripheral part of a wafer, on a film to be processed which is formed on the wafer; forming a positive resist film having a predetermined pattern on the negative resist film; and etching the film to be processed using the negative resist film and the positive resist film as a mask.

Abstract: The invention concerns a process for the production of a multi-layer body, wherein the multi-layer body includes at least two functional layers on a top side of a carrier substrate, which are structured in register relationship with each other, by a procedure whereby an underside of the carrier substrate is prepared in such a way that in a first region there results a transparency for a first exposure radiation and in at least one second region there results a transparency for at least one second exposure radiation different therefrom in register relationship with the first region, the underside is successively exposed with the first and the at least one second exposure radiation and the first exposure radiation is used for structuring a first functional layer and the at least one second exposure radiation is used for structuring at least one second functional layer on the top side of the carrier substrate.

Abstract: Disclosed herein is a method of manufacturing a semiconductor device that includes: performing a first exposure process with a first exposure mask having a first space pattern formed in a first direction; performing a second exposure process with a second exposure mask different from the first exposure mask, the second exposure mask having a second space pattern formed in a second direction intersected with the first direction; and forming a contact hole by a developing process.

Abstract: Provided is a manufacturing method of a semiconductor device, which is capable of realizing fine-pitch patterns and thus improving stabilization of patterning precision. The manufacturing method of the semiconductor device comprises forming a first photoresist pattern in a predetermined region on a substrate, depositing a thin film on the surface of the first photoresist pattern, and forming a second photoresist pattern in a region where the first photoresist pattern is not formed.

Abstract: A photosensitive compound has two or more structural units, in a molecule, represented by the following general formula (1): wherein R1 to R5 are selected from the group consisting of hydrogen atom, halogen atom, alkyl group, alkoxy group, acetoxy group, phenyl group, naphthyl group, and alkyl group in which a part or all of hydrogen atoms are substituted with fluorine atom; and X is a substituted or unsubstituted phenylene group or a substituted or unsubstituted naphthylene group.

Abstract: A positive type photosensitive resin composition comprises a polyacrylate resin having, in the structure, at least a structural unit represented by the following general formula (1): wherein X represents a hydroxyl group, an alkylol group having 2 to 4 carbon atoms, or a methylolamino group; R1 and R2 independently represents a hydrogen atom, or an alkyl group having 1 to 3 carbon atoms; R3 represents an alkyl group having 1 to 3 carbon atoms, an alkoxyl group having 1 to 3 carbon atoms, or an aralkyl group having an aryl group or alkyl group with 1 to 2 carbon atoms; n represents a positive integer; and m represents 0 or a positive integer, and a condensable crosslinker.

Abstract: Provided are a color electrophoretic display and a method of manufacturing the same. The color electrophoretic display includes: a plurality of lower electrodes arranged on a lower layer and disposed with a predetermined interval therebetween; a plurality of first to third photoresist chambers arranged on the plurality of lower electrodes; first to third electronic inks accommodated in the plurality of first to third photoresist chambers respectively, and discriminatively operating to an electric field to independently display red, green, and blue colors; and a plurality of upper electrodes disposed with a predetermined interval therebetween and facing the plurality of lower electrodes with the plurality of first to third photoresist chambers being held therebetween.

Abstract: Novel photoresist materials, which can be photolithographically processed in biocompatible conditions are presented in this invention. Suitable lithographic scheme for the use of these and analogous resists for biomolecule layer patterning on solid substrates are also described. The processes described enable micropatterning of more than two different proteins on solid substrates without denaturation of the proteins. The preferred resist materials are based on (meth)acrylate copolymers that contain at least one acid cleavable ester group and at least one hydrophilic group such as an alcoholic or a carboxylic group.