Abstract: A method of manufacturing a wiring circuit board includes: preparing an insulating layer; forming conductive thin films on the upper surface and the side end surface of the insulating layer; covering the conductive thin films formed on the upper surface and the side end surface of the insulating layer with photoresists; arranging a photomask so that an end portion and a portion to be provided with a conductive layer in the conductive thin film formed on the upper surface of the insulating layer are shaded and exposing the photoresist covering the conductive thin film formed on the upper surface of the insulating layer from above through the photomask; exposing the photoresist covering the conductive thin film formed on the side end surface of the insulating layer from below; forming plating resists by removing unexposed portions of the photoresists so as to form exposed portions into patterns; forming an end portion conductive layer on the end portion of the conductive thin film formed on the upper surface of

Abstract: A semiconductor device having assist features and manufacturing method thereof includes a substrate having at least an active region and a peripheral region defined thereon. The semiconductor device also includes a plurality of assist features positioned in the peripheral region, or in the active region with a dotted line pattern. The assist features are electrically connected to active circuits formed in the active region, respectively, for serving as redundant circuits that repair or replace defective circuits.

Abstract: A method of making a device includes forming a first photoresist layer over an underlying layer, patterning the first photoresist layer to form a first photoresist pattern comprising a first grid, rendering the first photoresist pattern insoluble to a solvent, forming a second photoresist layer over the first photoresist pattern, patterning the second photoresist layer to form a second photoresist pattern over the underlying layer, where the second photoresist pattern is a second grid which overlaps the first grid to form a photoresist web, and etching the underlying layer using the photoresist web as a mask.

Abstract: A method of processing a substrate includes forming a first layer having a photosensitive response to incident radiation on the substrate, forming a first pattern in the first layer, and exposing the first pattern to ultra-violet radiation. The exposure of the first pattern to ultra-violet radiation increases the resistance of the first pattern to a developer. The method also includes forming a conformal protective layer over the first pattern and at least a portion of the substrate. The method further includes forming a second layer having a photosensitive response to incident radiation over the conformal protective layer and forming a second pattern in the second layer.

Abstract: An embodiment of the invention provides an array substrate for a liquid crystal display comprising a substrate and a gate scanning line, a thin film transistor, a data line, and a passivation layer on the substrate, the passivation layer covering the gate scanning line, the thin film transistor, the data line, and a through hole being formed in the passivation layer. A pixel electrode is formed on the passivation layer and comprises a transmissive part and a reflective part, the transmissive part comprises an amorphous-type indium tin oxide film and a poly-type indium tin oxide film below the amorphous-type indium tin oxide film, and the reflective part comprises the poly-type indium tin oxide film and a metal film covering the poly-type indium tin oxide film.

Abstract: A manufacturing method for conducting films on two opposite surfaces of a transparent substrate of a touch control circuit, includes: contacting a first photoresist layer having photosensitive and discolored emulsion on a first conducting coat formed on a first surface of the transparent substrate, and contacting a second photoresist layer on a second conducting coat formed on a second surface of the transparent substrate; exposing the first photoresist layer to form a circuit pattern with distinguishable color on exposed regions of the first photoresist layer; employing the circuit pattern as an aligning benchmark for the second photoresist layer, and exposing the second photoresist layer accordingly; developing and etching those arranged on the two surfaces of the transparent substrate at the same time to form a first conducting film of a touch control circuit from the first conducting coat and form a second conducting film of the touch control circuit from the second conducting coat.

Abstract: There are provided a method for forming a resist pattern for preparing a circuit board having a landless or small-land-width through-hole(s) to realize a high-density circuit board, a method for producing a circuit board, and a circuit board. A method for forming a resist pattern, comprising the steps of forming a resin layer and a mask layer on a first surface of a substrate having a through-hole(s), and removing the resin layer on the through-hole(s) and on a periphery of the through-hole(s) on the first surface by supplying a resin layer removing solution from a second surface opposite to the first surface of the substrate, and a method for producing a circuit board using the method for forming a resist pattern, and a circuit board.

Abstract: The invention is to provide a method for producing a fine structured member and a fine hollow structure, useful for producing a liquid discharge head which is inexpensive, precise and highly reliable, also to provide a method for producing a liquid discharge head utilizing such producing method for the fine structured member and the fine hollow structure and a liquid discharge head obtained by such producing method. A positive-working photosensitive material, including a ternary polymer containing an acrylate ester as a principal component, acrylic acid for thermal crosslinking and a monomer unit for expanding a sensitivity region, is used as a material for forming the Line structured member.

Abstract: Example embodiments provide a method of fabricating a triode-structure field-emission device. A cathode, an insulating layer, and a gate metal layer may be sequentially formed on a substrate. A first resist pattern having a first opening and a second resist pattern having a second opening smaller than the first opening may be formed to be sequentially laminated on the gate metal layer. Then, the gate metal layer and the insulating layer may be etched using the first resist pattern to form a gate electrode and an insulating layer having a first hole and a second hole corresponding to the first opening. A catalyst layer may be formed on the cathode exposed through the first and second holes using the second resist pattern. After the first resist pattern, second resist pattern, and the catalyst layer on the second resist pattern are removed, an emitter may be formed on the catalyst layer in the second hole.

Abstract: A reticle for use in a semiconductor lithographic system includes at least two separated reticle parts. Each part includes a pattern to be transferred lithographically to a substrate. At least one of the two separated reticle parts is independently replaceable.

Abstract: A method of lithography patterning includes forming a first resist pattern on a substrate, the first resist pattern including a plurality of openings therein on the substrate; forming a second resist pattern on the substrate and within the plurality of openings of the first resist pattern, the second resist pattern including at least one opening therein on the substrate; and removing the first resist pattern to uncover the substrate underlying the first resist pattern.

Abstract: What is described is a lithographic method for fabricating three-dimensional structures on the micrometric and submicro-metric scale, including the operations of: depositing a layer of a first resist on a substrate; depositing a layer of a second resist on the layer of the first resist; forming a pattern of the second resist by lithography; depositing a further layer of the first resist on the previous layers; and forming a pattern of the first resist by lithography. The second resist is sensitive to exposure to charged particles or to electromagnetic radiation in a different way from the first; in other words, it is transparent to the particles or to the electromagnetic radiation to which the first resist is sensitive, and therefore the processes of exposure and development of the two resists are mutually incompatible to the extent that the exposure and development of one does not interfere with the exposure and development of the other.

Abstract: An electronic component or display device of the present invention can be provided by using a following pattern formation method. On a substrate treated with a first etching with a first resist pattern as a first mask, a second resist pattern is transfer-printed on the first resist patterns so as to partially overlap with the first resist pattern and partially extended from the first resist pattern. And then a second etching is performed by using the first resist pattern and the second resist pattern as a second mask. The first resist pattern and the second resist pattern are used for forming wirings and/or terminals, and the extended portion of the second resist pattern is used to make the wirings to have a cross section of a stair-like edge shape.

Abstract: A method of manufacturing a semiconductor device includes: forming a resist layer on an underlayer, forming an exposed pattern in the resist layer, wherein the exposed pattern comprises a soluble layer and an insoluble layer, forming a resist pattern by removing the soluble layer from the resist layer in which the exposed pattern is formed, removing an intermediate exposed area from the resist pattern, forming a new soluble layer in a surface of the resist pattern from which the intermediate exposed area is removed by applying a reaction material to the resist pattern from which the intermediate exposed area is removed, wherein the reaction material generates a solubilization material that solubilizes the resist pattern, and removing the new soluble layer from the resist pattern.

Abstract: A double exposure method for enhancing the image resolution in a lithographic system, is presented herein. The invention comprises decomposing a desired pattern to be printed on the substrate into at least two constituent sub-patterns that are capable of being optically resolved by the lithographic system, coating the substrate with a first positive tone resist layer and a thin second positive tone resist layer on top of a target layer which is to be patterned with the desired dense line pattern. The second resist material is absorbing exposure radiation during a first patterning exposure and after development during a second patterning exposure to prevent exposure above energy-to-clear of at least a portion of the first resist material underneath exposed portions of the second resist material layer.

Abstract: A photomask includes, on a translucent substrate, three or more first light-shielding portions each in insular shape having a property of shielding exposure light and spaced equidistantly, a second light-shielding portion having a property of shielding the exposure light and formed to connect the adjacent first light-shielding portions, and first light-transmitting portions each in slit shape having a property of transmitting the exposure light and formed to be surrounded with the first and second light-shielding portions. The second light-shielding portion is formed to contain a point located equidistantly from the three or more first light-shielding portions.

Abstract: Provided is a method of manufacturing a microfluidic device in which coating film patterns made of a coupling agent are formed in microchannels. The method includes: forming the coating film patterns made of the coupling agent on a Si substrate; selectively oxidizing coupling agent-free regions of the Si substrate having thereon the coating film patterns made of the coupling agent using an oxidizing agent with an oxidation potential from 1 to 2 V; and adhering a PDMS (polydimethylsiloxane) microchannel structure to the selectively oxidized Si substrate to form the microchannels.

Abstract: A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch of the interconnect trough. The process includes the steps of: forming an insulating layer on the surface of a substrate; forming an etch stop layer on the surface of the insulating layer; forming an opening in the etch stop layer; etching to a first depth through the opening in the etch stop layer and into the insulating layer to form an interconnect trough; forming a photoresist mask on the surface of the etch stop layer and in the trough; and continuing to etch through the insulating layer until reaching the surface of the substrate to form a contact hole. The above process may be repeated one or more times during the formation of multilevel metal integrated circuits.

Abstract: This invention provides methods of creating via or trench structures on a developer-soluble hardmask layer using a multiple exposure-development process. The hardmask layer is patterned while the imaging layer is developed. After the imaging layer is stripped using organic solvents, the same hardmask can be further patterned using subsequent exposure-development processes. Eventually, the pattern can be transferred to the substrate using an etching process.

Abstract: A multiple mask and a multiple masking layer technique can be used to pattern a single IC layer. A resolution enhancement technique can be used to define one or more fine-line patterns in a first masking layer, wherein each fine-line feature is sub-wavelength. Moreover, the pitch of each fine-line pattern is less than or equal to that wavelength. The portions of the fine-line features not needed to implement the circuit design are then removed or designated for removal using a mask. After patterning of the first masking layer, another mask can then be used to define coarse features in a second masking layer formed over the patterned first masking layer. At least one coarse feature is defined to connect two fine-line features, wherein the coarse feature(s) can be derived from a desired layout using a shrink/grow operation. The IC layer can be patterned using the composite mask formed by the patterned first and second masking layers.

Abstract: A method of manufacturing an electronic device includes forming a photosensitive SOG oxide layer on a multi-layer ceramics substrate having a penetrating electrode, forming an opening by subjecting the photosensitive SOG oxide layer to an exposure treatment and developing treatment so that an upper face of the penetrating electrode is exposed, and forming a passive element on the photosensitive SOG oxide layer, the passive element being connected to the penetrating electrode through the opening.

Abstract: A pattern for a gate line is formed using a first photoresist pattern and a first BARC layer. A pad and patterns for a select line, which has a width that is larger than that of the gate line, are formed using a second photoresist pattern and a second BARC layer. The gate line, the pad and the select line can be formed at a same time.

Abstract: There are provided methods of performing a photolithography process for forming asymmetric semiconductor patterns and methods of forming a semiconductor device using the same. These methods provide a way of forming asymmetric semiconductor patterns on a photoresist layer through two exposure processes. To this end, a semiconductor substrate is prepared. A planarized insulating interlayer and a photoresist layer are sequentially formed on the overall surface of the semiconductor substrate. A first semiconductor pattern of a photolithography mask is transferred to the photoresist layer, thereby forming a photoresist pattern on the photoresist layer. A second semiconductor pattern of a second photolithography mask is continuously transferred to the photoresist layer, thereby forming a second photoresist pattern on the photoresist layer.

Abstract: For patterning during integrated circuit fabrication, an image layer is activated for forming a respective first type polymer block at each of two nearest activated areas. A layer of block copolymer is formed on the image layer, and a plurality of the first type polymer blocks and a plurality of second and third types of polymer blocks are formed on an area of the image layer between outer edges of the two nearest activated areas, from the block copolymer. At least one of the first, second, and third types of polymer blocks are removed to form a variety of mask structures.

Abstract: Disclosed herein is a method for fabricating a probe needle tip of a probe card, in which, in order to prevent a poor grinding effect caused by irregular removal or flexibility of the photoresists laminated to be high in the course of polishing a first metal loaded into the opening of the photoresists laminated into a multilayer configuration upon formation of the probe needle tip of the probe card, a second metal is laminated on any one of one or more stacked photoresist layers, thus firmly holding the photoresist layers on/beneath the metal.

Abstract: In a double exposure process to print features at a reduced pitch, the critical dimension of features printed in the first exposure is measured and used as a target for the second exposure.

Abstract: Disclosed are embodiments of a lithographic patterning method that incorporates a combination of photolithography and self-assembling copolymer lithography techniques in order to create, on a substrate, a grid-pattern mask having multiple cells, each with at least one sub-50 nm dimension. The combination of different lithographic techniques further allows for precise registration and overlay of the individual grid-pattern cells with corresponding structures within the substrate. The resulting grid-pattern mask can then be used, in conjunction with directional etch and other processes, to extend the cell patterns into the substrate and, thereby form openings, with at least one sub-50 nm dimension, landing on corresponding in-substrate structures. Once the openings are formed, additional structures can be formed within the openings.

Abstract: A method and apparatus for measuring the chromatic response of lithographic projection imaging systems is described. An apparatus for determining the lens aberrations for a lithographic projection lens is provided. A substrate coated with a suitable recording media is provided. A series of lithographic exposures are performed using an exposure source with variable spectral settings. The exposures are measured, and the measurements are used to determine a chromatic response of the projection imaging system.

Abstract: A method suitable for reducing side lobe printing in a photolithography process is enabled by the use of a barrier layer on top of a photoresist on a substrate. The barrier layer is absorbing at the imaging wavelength of the underlying photoresist and thus blocks the light from reaching the photoresist. A first exposure followed by a development in an aqueous base solution selectively removes a portion of the barrier layer to reveal a section of the underlying photoresist layer. At least a portion of the revealed section of the photoresist layer is then exposed and developed to form a patterned structure in the photoresist layer. The barrier layer can also be bleachable upon exposure and bake in the present invention.

Abstract: A method for forming a mask pattern for forming a semiconductor device may include coating a photoresist, performing a primary bake process on the photoresist, exposing and developing the photoresist, and then performing a secondary bake process on the photoresist under a nitrogen and/or hydrogen gas atmosphere.

Abstract: After forming a resist film on a Si substrate, a circuit pattern for a semiconductor integrated circuit, a first L-shaped length measuring pattern and a cross-shaped monitor pattern for alignment are formed on the resist film. Next, based on these patterns, the Si substrate is patterned. Thereafter, a polysilicon film is formed above the Si substrate. Subsequently, a resist film is formed on the polysilicon film. Next, a circuit pattern for a semiconductor integrated circuit, a second L-shaped length measuring pattern and a cross-shaped monitor pattern for alignment are formed on the resist film. At this time, the second L-shaped length measuring pattern is made to face in a direction in which the first L-shaped length measuring pattern is rotated 180 degrees in plane view. By patterning the polysilicon film with these patterns as a mask, a gate electrode is formed.

Abstract: A photo-mask having a first exposure area, a second exposure area and a third exposure area is for manufacturing a thin-film transistor substrate. The photo-mask includes a first peripheral line pattern, a first dummy line pattern, a first overlapping pixel pattern and a second overlapping pixel pattern. The first peripheral line pattern is in the first exposure area. The first dummy line pattern is in the first exposure area and connected to the first peripheral line pattern. The first overlapping pixel pattern is in the first exposure area and connected to the first dummy line pattern. The first overlapping pixel pattern is complementary to the second overlapping pixel pattern in the second exposure area. After exposing through and overlapping the first and second overlapping pixel patterns, two patterns respectively formed from exposing through the first and second exposure area are unified.

Abstract: A multiple mask and a multiple masking layer technique can be used to pattern a single IC layer. A resolution enhancement technique can be used to define one or more fine-line patterns in a first masking layer, wherein each fine-line feature is sub-wavelength. Moreover, the pitch of each fine-line pattern is less than or equal to that wavelength. The portions of the fine-line features not needed to implement the circuit design are then removed or designated for removal using a mask. After patterning of the first masking layer, another mask can then be used to define coarse features in a second masking layer formed over the patterned first masking layer. At least one coarse feature is defined to connect two fine-line features. The IC layer can be patterned using the composite mask formed by the patterned first and second masking layers.

Abstract: An electrical structure and method of forming. The method comprises providing a substrate structure. A first layer comprising a first photosensitive material having a first polarity is formed over and in contact with the substrate structure. A second layer comprising photosensitive material having a second polarity is formed over and in contact with the first layer. The first polarity comprises an opposite polarity as the second polarity. Portions of the first and second layers are simultaneously exposed to a photo exposure light source. The portions of the first and second layers are developed such that structures are formed.

Abstract: A process for forming a pixel circuit is disclosed comprising: (a) providing a transparent support; (b) forming a multicolor mask having at least four different color patterns; (c) forming integrated electronic components of the pixel circuit having at least four layers of patterned functional material comprising a first conductor, a dielectric, a semiconductor, and a second conductor each layer of patterned functional material corresponding to the four different color patterns of the multicolor mask. The functional material is patterned using a photopattern corresponding to each color pattern.

Abstract: A method for manufacturing an image sensor that does not include a reflow process but includes exposing a photoresist film a plurality of times from various angles and then forming one or more micro lenses by developing the exposed photoresist film.

Abstract: A method for fabricating a semiconductor device may include forming first and second photoresist patterns that intersect with each other on and/or over an etched film, and forming a fine pattern on the etched film by etching the etched film using the first and second photoresist patterns as an etching mask. According to embodiments, a fine pattern, such as a contact hole, may be formed by performing two exposure processes. The method may use existing masks for line and/or space. The method may secure a sufficient etching margin by securing a sufficient thickness of a photoresist film through two photoresist coating processes.

Abstract: A polarization analyzing system includes a data collector collecting information on resist patterns formed over step patterns by first and second lights, the first and second lights being polarized parallel and perpendicular to the step patterns, a residual resist analyzer obtaining first and second relations between a ratio of a space to a line width of the resist patterns and the first and second residues, the first and second residues remaining at orthogonal points of the step patterns and the resist patterns, and a direction chooser choosing an optimum polarization direction reducing residues by comparing the first and second relations.

Abstract: A substrate before an insulation process, which is provided with a protection film to prevent a part of a surface area, which has electrical conductivity from being insulated, the substrate comprises: a base including the surface area, which has electrical conductivity; a protection film covering over the part of the surface area, which has electrical conductivity, and being formed on the base; the protection film including; a first protection layer having a circumferential partition wall and a second protection layer placed and embedded in an area, which is surrounded by the circumferential partition wall.

Abstract: A pattern forming method comprises forming a first resist pattern on a substrate, irradiating light on the first resist pattern, forming a resist film including a cross-linking material on the substrate and the first resist pattern, forming a second resist pattern including a cross-linking layer formed at an interface between the first resist pattern and the resist film by causing a cross-linking reaction at the interface, and irradiating light on the first resist pattern including setting an amount of the light irradiated on the first resist pattern such that a dimension of the second resist pattern is to be a predetermined dimension based on a previously prepared relationship between a difference between a dimension relating to the first resist pattern and a dimension relating to the second resist pattern and the amount of the light irradiated on the first resist pattern.

Abstract: The present invention relates to a method of forming a micro pattern of a semiconductor device. According to an aspect of the present invention, a first photoresist layer and a second photoresist layer with different exposure types are formed over a semiconductor substrate on which an etch target layer is formed, performing an exposure process on the second photoresist layer and the first photoresist layer. Second photoresist patterns are formed by developing the second photoresist layer. First photoresist patterns are formed by etching the first photoresist layer using an etch process employing the second photoresist patterns as an etch mask. Auxiliary patterns are formed by developing the first photoresist patterns. The etch target layer is etched by employing the auxiliary patterns.

Abstract: In a method for forming a photoelectric composite board (10) on which a photoelectric transducer (5) is mounted, photo-masks (111, 112, 113) which are used in processes to form the photoelectric composite board (10) are respectively disposed on the basis of a reference mark (33) previously formed on a metal thin film (101). In addition, openings (22) are formed on solder resist layers (8) by irradiating laser beams at positions defined on the basis of a reference point (4a) defined above a light deflector (4) formed on an end of a light guide (3).

Abstract: Components in integrated circuits (ICs) are fabricated as small as possible to minimize sizes of the ICs and thus reduce manufacturing costs per IC. Metal interconnect lines are formed on minimum pitches possible using available photolithographic printers. Minimum pitches possible for contacts and vias are larger than minimum pitches possible for metal interconnect lines, thus preventing dense rectilinear grid configurations for contacts and vias. The instant invention is an integrated circuit, and a method of fabricating an integrated circuit, wherein metal interconnect lines are formed on a minimum pitch possible using a photolithographic printer. Contacts and vias are arranged to provide connections to components and metal interconnect lines, as required by the integrated circuit, in configurations that are compatible with the minimum pitch for contacts and vias, including semi-dense arrays.

Abstract: The invention is directed to a method for patterning a material layer. The method comprises steps of forming a mask layer on the material layer. A multiple patterning process is performed on the mask layer for transferring at least a first pattern from a first photomask through a first photoresist and a second pattern from a second photomask from a second photoresist layer into the mask layer without performing any etching process. The mask layer exposes a portion of the material layer and the mask layer is patterned at the time that the first photoresist layer and the second photoresist layer are developed respectively. An etching process is performed to pattern the material layer by using the mask layer as an etching mask.

Abstract: A method and system for providing a twin well in a semiconductor device is described. The method and system include providing at least one interference layer and providing a first mask that covers a first portion of the semiconductor device and uncovers a second portion of the semiconductor device. The first and second portions of the semiconductor device are adjacent. The method and system also include implanting a first well in the second portion of the semiconductor device after the first mask is provided. The method and system also include providing a second mask. The interference layer(s) are configured such that energy during a blanket exposure develops the second mask that uncovers the first portion and covers the second portion of the semiconductor device. The method and system also include implanting a second well in the first portion of the semiconductor device after the second mask is provided.

Abstract: A method of forming a variable pattern across a wafer using a reticle forms a plurality of first patterns on the wafer. The first pattern is repeated across the wafer and each first pattern has a first readable element. The method also forms a plurality of second patterns on the wafer. The second patterns is repeated across the wafer and each second pattern has a second readable element. The second patterns are positioned relative to the first patterns by aligning a first second pattern relative to one portion of a corresponding first pattern and then incrementally misaligning each successive second pattern in a row or a column relative to its corresponding first pattern. Thus, each corresponding first readable element and second readable element form a corresponding variable pattern.

Abstract: Multi-beam lithography systems and methods of manufacturing semiconductor devices using the same are disclosed. For example, the method utilizes non-coincidence of boundaries of electrical fields emanating from chrome on glass or phase shifted mask features distributed over two masks for the optimization of lithographic process windows, side lobe suppression, or pattern orientation dependent process window optimization employing one mask with polarization rotating film on the backside.

Abstract: The present invention provides a method for manufacturing an electroluminescence element that has a light emitting layer containing a quantum dot and exhibits excellent life characteristics. In the method, patterning of the light emitting layer can be stably performed by a lift-off method. A photoresist layer is formed on a substrate having a first electrode layer. The photoresist layer is then exposed, developed, and patterned to ensure that a portion of the photoresist layer, which is located in a light emission area, is removed. A coating liquid containing a quantum dot having a silane coupling agent attached to the surface thereof is coated on the resultant substrate having the patterned photoresist layer and cured to form a light emitting layer. The remaining photoresist layer is then removed to lift off a portion of the light emitting layer, which is present on the photoresist layer.

Abstract: The present disclosure is directed to a method for preparing photomask patterns for a lithography process that employs a plurality of photomasks. The method comprises receiving data describing a drawn pattern. An edge of the drawn pattern is identified that can be defined using a first photomask and a second photomask, and the first photomask is chosen for patterning the edge. Patterns are formed for the first photomask and the second photomask, wherein the first photomask pattern is formed to pattern the edge, and the second photomask pattern is formed to have a wing adjacent to the edge for protecting the edge from double patterning. A process for patterning an integrated circuit device is also disclosed.

Abstract: The resist material contains a photo-acid generator having an absorption peak to exposure light having a wavelength of less than 300 nm, and a second photo-acid generator having an absorption peak to exposure light having a wavelength of 300 nm or more. The method for forming a resist pattern comprises a step for selectively exposing which exposes a coating film of the resist material to an exposure light having a wavelength of less than 300 nm, and a step for selectively exposing by using an exposure light having a wavelength of 300 nm or more. The semiconductor device comprises a pattern formed by the resist pattern. The method for forming a semiconductor device comprises a step for forming a resist pattern on an underlying layer by the aforementioned manufacturing method, and a step for patterning the underlying layer by etching using the resist pattern as a mask.