Abstract: Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes depositing a gate material over a semiconductor substrate, and depositing a first resist layer over the gate material. A first mask is used to pattern the first resist layer to form first and second resist features. The first resist features include pattern for gate lines of the semiconductor device and the second resist features include printing assist features. A second mask is used to form a resist template; the second mask removes the second resist features.

Abstract: A method for manufacturing a semiconductor device is disclosed. The method can assess exposure conditions by forming a predetermined assessment pattern on a principal surface of a semiconductor wafer. The predetermined assessment pattern includes a first assessment pattern having a remaining pattern, and a second assessment pattern which includes a remaining pattern formed in a position lower than the first assessment pattern in the direction of the optical axis of an exposure device. The method includes a preparation step, and a step of manufacturing an actual semiconductor device. The preparation step includes a forming step, a measuring step, a calculating step, and a creating step. The step of manufacturing an actual semiconductor device includes a forming step, a measuring step, a calculating step and an assessing step.

Abstract: The present invention relates to a device manufacturing method wherein a plurality of front side marks are manufactured on the front side of the substrate. These marks are used to locally align the substrate when exposing. After certain processing steps, the positions of the front side marks are measured and compared with respect to their original positions. The measured position changes of the front side marks, i.e. their behaviour, can then be analyzed. The original positions and actual positions are defined with respect to a nominal grid which is defined using global alignment marks which are positioned at the back side of the substrate. Because the global alignment marks are positioned at the back side, they are not affected by any processing step.

Abstract: A method for producing a pattern on a substrate includes providing at least one exposure of the pattern onto a layer of the substrate by a higher-precision lithography mechanism and providing at least one exposure of the pattern onto a layer of the substrate by a lower-precision lithography mechanism. The exposures can be done in either order, and additional exposures can be included. The higher-precision lithography mechanism can be immersion lithography and the lower-precision lithography mechanism can be dry lithography.

Abstract: A semiconductor device fabrication method includes preparing a substrate having a first circuit pattern of a semiconductor device; providing a mask with at least part of second circuit pattern of the semiconductor device; collimating incident direction of particles; changing at least one of the a substrate angle between a vertical axis of the substrate and the incident direction of the particles and a mask angle between a vertical axis of the mask and the incident direction so that the second circuit pattern on the mask can be aligned to the first circuit pattern on the substrate with a design margin; and selectively irradiating the particles to the substrate using the mask.

Abstract: A double exposure semiconductor process is provided for improved process margin at reduced feature sizes. During a first processing sequence, features defining non-critical dimensions of a polysilicon interconnect structure are formed, while other portions of the polysilicon layer are left un-processed. During a second processing sequence, features that define the critical dimensions of the polysilicon interconnect structure are formed without the need to execute a photoresist trimming procedure. Accordingly, only an etch process is executed, which provides higher resolution processing to create the critical dimensions needed during the second processing sequence.

Abstract: A method of manufacturing a thin-film magnetic head structure comprises the steps of preparing an insulating layer 10; forming a first resist layer 51 provided with a first slit pattern 51a corresponding to a very narrow groove part and a second slit pattern 51b corresponding to a temporary groove part integrally extending from the very narrow groove part along outer edges of a main depression onto the insulating layer 10; etching the insulating layer 10 while using the first resist layer 51 as a mask; eliminating the first resist layer 51; forming a second resist layer having an opening pattern corresponding to the main depression onto the insulating layer 10; and etching the insulating layer 10 while using the second resist layer as a mask.

Abstract: A manufacturing method of a silicon carbide semiconductor apparatus is provided. The method includes forming a first resist pattern on a surface of a silicon carbide layer formed on a silicon carbide substrate, implanting a first conduction type impurity ion in the silicon carbide layer on which the first resist pattern is formed, forming a second resist pattern by decreasing a width of the first resist pattern with etching and forming a deposition layer on the surface of the silicon carbide layer which is not covered with the second resist pattern, and implanting a second conduction type impurity ion in the silicon carbide layer on which the second resist pattern is formed, through the deposition layer.

Abstract: An ink-jet printhead and a method of manufacturing the same include a substrate on which a heater and a passivation layer protecting the heater are formed, a passage plate on which an ink chamber corresponding to the heater and an ink passage connected to the ink chamber are formed, and a nozzle plate in which an orifice corresponding to the ink chamber is formed. An exposure stop layer (ESL) that blocks passage of a photosensitive energy is formed inside the nozzle plate, and the nozzle plate and the passage plate are bonded with each other by the exposure stop layer (ESL).

Abstract: A method of lithography patterning includes forming a first material layer on a substrate, the first material layer being substantially free of silicon, and forming a patterned resist layer including at least one opening therein above the first material layer. A second material layer containing silicon is formed on the patterned resist layer and an opening is formed in the first material layer using the second material layer as a mask.

Abstract: A method of manufacturing a semiconductor device comprising forming an active region in a device substrate using a first phase shift mask (PSM) having a first patterned light shielding layer formed thereon, forming a polysilicon feature on the device substrate over the active region using a second PSM having a second patterned light shielding layer formed thereon, forming a contact feature on the polysilicon feature using a third PSM having a third patterned light shielding layer formed thereon, and forming a metal feature on the contact feature using a fourth PSM having a fourth patterned light shielding layer formed thereon, wherein at least one of the third and fourth patterned light shielding layers is patterned substantially similarly to at least one of the first and second patterned light shielding layers.

Abstract: A method, wherein a plurality of first patterns are formed in an exposure region, and second patterns are formed by plural shots, with positions of alignment marks measured for said plurality of first patterns to give first positional information; relative positions of said plurality of first patterns to a first coordinate system are measured, to thereby compute first disalignments relative to the first coordinate system; second positional information is computed by subtracting the first disalignments from the first positional information; relative positions of said plural basic regions with respect to a second coordinate system are measured, to thereby compute second disalignments of the first pattern relative to the second coordinate system; third positional information is computed by subtracting the first and second disalignments from the first positional information; third disalignments of the first pattern with respect to a third coordinate system are computed; and positioning with respect to the first p

Abstract: In an exposure step, a combination of a first photomask and a second mask is used. The first mask has a real pattern corresponding to the pattern actually formed on the film to be processed, and a dummy pattern added for controlling pattern pitch in the first photomask within a prescribed range; and the second photomask has a pattern isolating a real-pattern-formed region from a dummy-pattern-formed region. In forming the pattern, after forming a film to be processed on a substrate, a first mask is formed on the film to be processed, by lithography, using the first photomask, and a second mask is formed on the film to be processed, by lithography, using the second photomask. Thereafter, the film to be processed is etched and removed using the first and second masks as masks to form the pattern.

Abstract: There is disclosed a resist lower layer film material for a multilayer-resist film used in lithography which contains, at least, a polymer having a repeating unit represented by the following general formula (1). Thereby, there can be provided a resist lower layer film material for a multilayer-resist process, especially for a two-layer resist process, which functions as an excellent antireflection film especially for exposure with a short wavelength, namely has higher transparency, and has the optimal n value and k value, and is excellent in an etching resistance in substrate processing, and a method for forming a pattern on a substrate by lithography using it.

Abstract: A Peltier or Seebeck element has first and second conductive members having different Seebeck coefficients. To decrease the heat conduction from one to the other end of each of the conductive members, the cross-section area at the intermediate part in the length direction is smaller than those at both ends parts. In place of the decrease of the cross-section, the shape of the cross-section of the intermediate part of each of the conductive members may be changed by dividing the intermediate part into pieces, or amorphous silicon or the like having a heat conductivity lower than those of the materials of both end parts may be used for the material of the intermediate part. In such a way, a high-performance Peltier/Seebeck element such that the difference between the temperature of the heated portion of the Peltier/Seebeck element and the opposite portion can be kept to a predetermined temperature difference for a long time and its manufacturing method are provided.

Abstract: A method of forming a security device comprises: a) providing an undeveloped photoresist layer on an electrically conductive layer; b) forming a first diffractive pattern in the undeveloped photoresist layer using optical-interferometry; c) forming a second diffractive pattern in the undeveloped photoresist layer using electron beam lithography; and d) thereafter developing the photoresist layer.

Abstract: A method for patterning a material during fabrication of a semiconductor device provides for the selective formation of either asymmetrical features or symmetrical features using a symmetrical photomask, depending on which process flow is chosen. The resulting features which are fabricated use spacers formed around a patterned material. If one particular etch is used to remove a base material, symmetrical features result. If two particular etches are used to remove the base material, asymmetrical features remain.

Abstract: In a method for multiply exposing at least one substrate coated with a photosensitive layer, a first exposure is carried out in accordance with a first set of exposure parameters on a first projection system, and a second exposure is carried out in accordance with a second set of exposure parameters on a second projection system spatially separated from the first projection system. The projection systems are integrated in a common projection exposure installation. The first exposure can be carried out, for example, with an amplitude mask, the second exposure with a phase mask. The use of a number of projection systems enables multiple exposure that is performed in parallel and is therefore timesaving.

Abstract: An integrated circuit fabrication process as described herein employs a double photoresist exposure technique. After creation of a first pattern of photoresist features on a wafer, a second photoresist layer is formed over the first pattern of photoresist features. The second photoresist layer is subjected to a reflow step that softens and relaxes the second photoresist material. This reflow step causes the exposed surface of the second photoresist layer to become substantially planar. Thereafter, the second photoresist layer can be exposed and developed to create a second pattern of photoresist features on the wafer. The planar surface of the second photoresist layer, which results from the reflow step, facilitates the creation of accurate, precise, and “high fidelity” photoresist features from the second photoresist material.

Abstract: A photosensitive material for use in semiconductor manufacture comprises a copolymer that includes a plurality of photoresist chains and a plurality of hydrophobic chains, each hydrophobic chain attached to the end of one of the photoresist chains. The copolymer in response to externally applied energy will self-assemble to a photoresist layer and a hydrophobic layer.

Abstract: Provided is the design and fabrication of the novel bounce drive actuator (BDA) for the development of a new-type micro rotary motor. Although the scratch drive actuator (SDA) micro motor has been developed more than one decade, such device has limited commercial applications due to its shorter lifetime, high power consumption and sudden reverse rotation. In contrast, present invention proposes an innovative BDA micro rotary motor with different actuating mechanism and improved performance. Several significant investigations shown in this research present that the length of the SDA-plate is longer than 75 ?m and the plate length of the BDA is less than 75 ?m. Under the same driving power and frequency with SDA-based micro motor, the BDA-based micro rotary motor exhibited a consistent “reverse” rotation and a higher speed.

Abstract: The present disclosure provides a plurality of methods of performing a lithography process. In one embodiment, a substrate including a layer of photoresist is provided. The layer of photoresist is exposed. The exposed layer of photoresist is developed. A chemical rinse solution is applied to the developed photoresist. The chemical rinse solution includes an alcohol base chemical. The substrate is spun dry.

Abstract: A series structure of a chemically amplified negative tone photoresist that is not based on cross-linking chemistry is herein described. The photoresist may comprise: a first aromatic structure copolymerized with a cycloolefin, wherein the cycloolefin is functionalized with a di-ol. The photoresist may also include a photo acid generator (PAG). When at least a portion of the negative tone photoresist is exposed to light (EUV or UV radiation), the PAG releases an acid, which reacts with the functionalized di-ol to rearrange into a ketone or aldehyde. Then new ketone or aldehyde is less soluble in developer solution, resulting in a negative tone photoresist.

Abstract: A patterned structure in a wafer is created using one or more fabrication treatment processes. The patterned structure has a treated and an untreated portion. One or more diffraction sensitivity enhancement techniques are applied to the structure, the one or more diffraction sensitivity enhancement techniques adjusting one or more properties of the patterned structure to enhance diffraction contrast between the treated portion and untreated portions. A first diffraction signal is measured off an unpatterned structure on the wafer using an optical metrology device. A second diffraction signal is measured off the patterned structure on the wafer using the optical metrology device. One or more diffraction sensitivity enhancement techniques are selected based on comparisons of the first and second diffraction signals.

Abstract: A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized.

Abstract: In a method of manufacturing a semiconductor device including a wiring pattern in the form of a linear line having an intermediate portion with a locally different line width, the wiring pattern being formed by using a resist pattern, the resist pattern is formed through an exposure step using a mask pattern prepared by dividing the wiring pattern in a mask into a simple line portion and a rectangular pattern portion having a different line width, and interposing between the line portion and the rectangular pattern portion a slit having a predetermined separation width of not larger than 0.22×?/NA (? represents a wavelength of exposure light, and NA represents a numerical aperture of a projection lens).

Abstract: The invention relates to flexible circuits and more particularly to flexible printed circuits having cover layers. The cover layers may be a chemically-etchable adhesive polyimide. The cover layers may be patterned after they are applied to the flexible circuit substrate.

Abstract: There is provide a divided exposure technology capable of restraining deterioration in the performance of a solid-state image sensor. A photoresist is formed over a semiconductor substrate and subjected to divided exposure. A dividing line for divided exposure is located at least over a region of a semiconductor substrate in which an active region in which a pixel is to be formed is defined. The photoresist is then developed and patterned. By utilizing the patterned photoresist, an element isolation structure for defining the active region in the semiconductor substrate is formed in the semiconductor substrate.

Abstract: Alignment tolerances between narrow mask lines, for forming interconnects in the array region of an integrated circuit, and wider mask lines, for forming interconnects in the periphery of the integrated circuit, are increased. The narrow mask lines are formed by pitch multiplication and the wider mask lines are formed by photolithography. The wider mask lines and are aligned so that one side of those lines is flush with or inset from a corresponding side of the narrow lines. Being wider, the opposite sides of the wider mask lines protrude beyond the corresponding opposite sides of the narrow mask lines. The wider mask lines are formed in negative photoresist having a height less than the height of the narrow mask lines. Advantageously, the narrow mask lines can prevent expansion of the mask lines in one direction, thus increasing alignment tolerances in that direction.

Abstract: A method of forming a contact hole is provided. A pattern is formed in a photo resist layer. The pattern is exchanged into a silicon photo resist layer to form a first opening. Another pattern is formed in another photo resist layer. The pattern is exchanged into a silicon photo resist layer to form a second opening. The pattern having the first, and second openings is exchanged into the interlayer dielectric layer, and etching stop layer to form the contact hole. The present invention has twice exposure processes and twice etching processes to form the contact hole having small distance.

Abstract: By performing a double exposure process on the basis of bar-like or line-like features, critical via and contact openings may be defined as an intersection, thereby obtaining the desired design dimension on the basis of less critical lithography process windows. Hence, process flexibility may be enhanced while overall throughput may not be substantially negatively affected.

Abstract: A method for fabricating ultra-short T-gates on heterojunction field effect transistors (HFETs) comprising the steps of (a) providing a coating of three layers of resists, with polymethylmethacrylate (PMMA) with high molecular weight on the bottom, polydimethylglutarimide (PMGI) in the middle, and PMMA with low molecular weight on the top; (b) in a first exposure, exposing and developing the layers with a dose of a developer that is high enough to allow the developer to break the top PMMA but low to avoid contributing significantly to the overall dose received in the bottom PMMA layer; and (c) in a second exposure, using an exposure and developing process to define 0.03-0.05 um openings in the bottom PMMA layer.

Abstract: A lithographic template, a method of forming the lithographic template and a method for forming devices with the lithographic template is provided. The lithographic template (10) and the method of making comprises forming a transparent conductive layer (16) over a substrate (12). A SiCN layer (18) is formed over the transparent conductive layer (16), and a patterning layer (20) formed on the SiCN layer (18). The SiCN layer (18) is converted to an SiO2 layer by applying an O2 plasma (23). The SiO2 layer prevents damage to the transparent conductive layer (16) during cleaning and provides a binding mechanism for the imprint release coating.

Abstract: An integrated circuit system that includes: providing a first mask including a first feature; exposing the first mask to a radiation source to form an image of the first feature on a photoresist material that is larger than a structure to be formed, the photoresist material being formed over a substrate that includes the integrated circuit system; providing a second mask including a second feature; aligning the second mask over the image of the first mask to form an overlap region; and exposing the second mask to the radiation source to form an image of the second feature on the photoresist material that is larger than the structure to be formed.

Abstract: A method for patterning and forming very small structures on a substrate such as a wafer. The process uses a difference in surface energy between a mask and the substrate to selectively deposit a hard mask material such as a metal onto the surface of the substrate. The mask can be formed extremely thin, such as only an atomic mono-layer thick, and can be patterned by ion beam photolithography. The pattern can, therefore, be formed with extremely high resolution. The thin mask layer can be constructed of various materials and can be constructed of perfluorpolyether diacrylate (PDA), which can be dip coated to and exposed to form a desirable positive photoresist mask layer.

Abstract: Thermally curable undercoat composition comprising for producing a bilayer relief image comprising: a) a polymer of Structure I comprising repeating units of Structure II, III, and IV b) a phenolic crosslinker; c) a thermal acid generator (TAG); and d) a solvent.

Abstract: Manufacturing semiconductor device by steps of: a) providing substrate with antireflective coating or underlayer, b) applying first photosensitive composition over substrate, c) exposing first composition to radiation to produce first pattern, d) developing exposed first composition to produce an imaged bilayer stack, e) rinsing the stack, f) applying fixer to the stack, g) applying optional bake, h) rinsing the stack, i) applying second optional bake, j) applying second photosensitive composition onto the stack to produce multilayer stack, k) exposing second composition to produce second pattern offset from first pattern, l) developing exposed second composition to produce multilayer stack, and m) rinsing multilayer stack; the photosensitive compositions have photoacid generator and substantially aqueous base insoluble polymer whose solubility increases upon treatment with acid and further comprises an anchor group, and the fixer is a polyfunctional compound reactive with anchor group, but does not conta

Abstract: A method and system are provided for forming a pattern within an area of a photosensitive surface. An exemplary method includes performing a first exposure of the photosensitive surface in accordance with predetermined image data, wherein the first exposure occurs during a first pass and produces a first image within the area. The image data is adjusted to compensate for identified image deficiencies image deficiencies, the image deficiencies being within a region of the first image. A second exposure, of the photosensitive surface, is performed in accordance with the adjusted image data during a second pass.

Abstract: Mask and integrated circuit fabrication approaches are described to facilitate use of so called “full phase” masks. This facilitates use of masks where substantially all of a layout is defined using phase shifting. More specifically, exposure settings including relative dosing between the phase shift mask and the trim masks are described. Additionally, single reticle approaches for accommodating both masks are considered. In one embodiment, the phase shifting mask and the trim mask are exposed using the same exposure conditions, except for relative dosing. In another embodiment, the relative dosing between the phase and trim patterns is 1.0:r, 2.0<r<4.0. These approaches facilitate better exposure profiles for the resulting ICs and can thus improve chip yield and increase throughput by reducing the need to alter settings and/or switch reticles between exposures.

Abstract: The present invention relates to a method for creating a pattern on a workpiece sensitive to electromagnetic radiation. Electromagnetic radiation is emitted onto a computer controlled reticle having a multitude of modulating elements (pixels). The pixels are arranged in said computer controlled reticle according to a digital description. An image of said computer controlled reticle is created on said workpiece, wherein said pixels in said computer controlled reticle are arranged in alternate states along at least a part of one feature edge in order to create a smaller address grid. The invention also relates to an apparatus for creating a pattern on a workpiece. The invention also relates to a semiconducting wafer and a mask.

Abstract: Methods of adhering polymeric materials to a substrate, either directly or through linker molecules, are disclosed. Structures, for example, microstructures, including microwells and arrays of microwells, may be readily formed using the methods. In some embodiments, microstructures formed completely from polymeric materials are provided, making it possible to tailor the chemical and physical properties of the microstructures. For example, microwells having a bottom comprising a polar polymeric material and well sides/top comprising a non-polar polymeric material are provided. Biochemical reagents may be easily delivered to such “smart wells” because the intrinsic attraction of the well bottom for the reagents and the intrinsic repulsion between the well sides/top combine to direct the reagents to the wells.

Abstract: A method for forming a fine pattern in a semiconductor device includes the steps of: coating a first photoresist composition over a semiconductor substrate including an underlying layer, thereby forming a first photoresist film; exposing and developing the first photoresist film, thereby forming a first photoresist pattern; forming a second photoresist film that does not react with the first photoresist pattern over the resulting structure; and exposing and developing the second photoresist film, thereby forming a second photoresist pattern; wherein the first and second photoresist patterns each comprise a plurality of elements, and individual elements of the second photoresist pattern are located between adjacent individual elements of the first photoresist pattern.

Abstract: A photolithographic method uses different exposure patterns. In one aspect, a photo-sensitive layer on a substrate is subject to a first exposure using optics having a first exposure pattern, such as an x-dipole pattern, followed by exposure using optics having a second exposure pattern, such as a y-dipole pattern, via the same mask, and with the photo-sensitive layer fixed relative to the mask. A 2-D post pattern with a pitch of approximately 70-150 nm may be formed in a layer beneath the photo-sensitive layer using 157-193 nm UV light, and hyper-numerical aperture optics, in one approach. In another aspect, hard baking is performed after both of the first and second exposures to erase a memory effect of photoresist after the first exposure. In another aspect, etching of a hard mask beneath the photo-sensitive layer is performed after both of the first and second exposures.

Abstract: After forming a resist film including a hygroscopic compound, pattern exposure is performed by selectively irradiating the resist film with exposing light while supplying water onto the resist film. After the pattern exposure, the resist film is developed so as to form a resist pattern.

Abstract: A method for forming an ink jet recording head includes at least a step of forming an ink flow path pattern on a substrate by a photodecomposable positive type resist resin, a step of, once executing each of the steps of applying, exposing and baking thereon a nozzle-constituting resin layer which is a negative type resist containing an optical cation polymerization starting agent and having an epoxy resin as a chief component with respect to each of an ink flow path pattern and an ink discharge port pattern, collectively developing unexposed portions on the respective nozzle-constituting resin layers, and a step of removing the formed photodecomposable resin is minimized.

Abstract: A method for manufacturing optical components in a three-dimensional photonic crystal lattice. A first resist (9) is coated on a substrate (10) and exposed to an e-beam (11), to produce an imaged area (12). Another resist coating is applied to thicken the resist (13) and an interference exposure (15) is used to image the result. This is developed to form periodic voids (16), which may be filled with a materials having a high refractive index to form a pattern (18 and 12) when the resist (13) is removed.

Abstract: A piezoelectric device includes a substrate, a buffer layer on the substrate, a lower electrode layer on the buffer layer, a piezoelectric layer on the lower electrode layer, and an upper electrode layer on the piezoelectric layer. The piezoelectric layer has a base portion extending outwardly at its lower portion of its periphery. The piezoelectric device provides enhanced bonding strength between the substrate and the stacked structure including the upper electrode layer, the lower electrode layer, and the piezoelectric layer.

Abstract: A method for forming a big-layer lift-off mask for use in fabricating GMR read-head sensors with trackwidths of less than 0.1 microns. The mask layers are formed symmetrically on each other, each layer of the mask having a novel dog-bone shape and the lower mask layer being substantially undercut relative to the upper mask layer. The central portion of the lower mask layer forms a narrow ridge that maintains the upper mask layer at a fixed height above a substrate, thereby avoiding problems associated with big-layer lift-off masks of the prior art. The method of forming the lower ridge requires a carefully controlled undercutting of the lower mask layer, which is accomplished by using an ozone-assisted oxidation process.

Abstract: There exist a pattern-dense region where patterns having an F-letter shape are dense and a pattern-interspersed region where small rectangular dummy patterns are interspersed. In the pattern-interspersed region, the dummy patterns are arranged in a manner that at least one dummy pattern exists in a scan target range of a mask pattern defect inspecting apparatus. With the dummy patterns formed in the pattern-interspersed region at the intervals as described above, when one scan target range is scanned by the mask pattern defect inspecting apparatus, at least one dummy pattern is included in the scan target range in the pattern-interspersed region. Therefore, mix-up of alignment in this range is prevented from occurring, which makes it possible to perform proper defect inspection.

Abstract: A method for forming a pattern according to the invention comprises the steps of: forming a mask over a substrate having light-transmitting properties; forming a first region having a substance including a light-absorbing material over the substrate and the mask; forming a second region by irradiating the substance with light having a wavelength which is absorbable by the light-absorbing material through the substrate to modify a part of the substance surface; and forming a pattern by discharging a compound including a pattern forming material to the second region.