Abstract: A method for forming fine patterns of a semiconductor device is provided, the method including forming a first lower layer pattern having a width of two minimum line width and a space pattern on a semiconductor substrate prior to a C-HALO implant process and etching the first lower layer pattern to separate into a second lower layer pattern having a width of two minimum line widths and a space pattern.

Abstract: There is provided a method of making plurality of features in a first layer. A photoresist layer is formed over the first layer. Dense regions in the photoresist layer are exposed through a first mask under a first set of illumination conditions. Isolated regions in the photoresist layer are exposed through a second mask different from the first mask under a second set of illumination conditions different from the first set of illumination conditions. The exposed photoresist layer is patterned and then the first layer is patterned using the patterned photoresist layer as a mask.

Abstract: A method for dynamically registering multiple patterned layers on a substrate (3) comprises: depositing a first layer on the substrate; printing a first pattern (20) on the first layer; depositing a second layer on the first pattern; and printing a second pattern on the second layer while dynamically detecting the first pattern to align the second pattern with the first pattern.

Abstract: A method of manufacturing a printed circuit board is disclosed, in which a cavity is formed for embedding a component, which includes: providing a core board, in which an inner circuit is buried; forming a first via in the core board for interlayer conduction; selectively forming a first photoresist in a position on the core board in correspondence with a position of the cavity; stacking a first build-up layer, on which a first outer circuit is formed, on the core board; and selectively removing the first build-up layer in correspondence with the position of the cavity and removing the first photoresist. Utilizing the method, a board can be manufactured with greater precision, as the thickness tolerance of the cavity may be obtained by controlling the thickness of the photoresist, and the overall thickness of the board can be controlled by controlling the height of the cavity.

Abstract: A non-volatile memory device having memory elements with a channel length of, e.g., 45-55 nm or less, is fabricated using existing lithographic techniques. In one approach, patterns of first and second photomasks are transferred to the same photoresist layer. The first photomask can have openings with a given feature size F that are spaced apart by the feature size F, for instance. The second photomask has an opening which is sized to create a desired inter-select gate gap, such as 3 F or 5 F. A third photomask is used to provide protective portions in a second photoresist layer over the select gate structures. The final structure has memory elements of width F spaced apart by a distance F, and select gates of width 3 F spaced apart by 3 F or 5 F. In another approach, the patterns of three photomasks are transferred to respective photoresist layers to create an analogous final structure.

Abstract: A technique is disclosed that combines a bilayered photoresist structure, similar to that which is already in use in the MR head industry, with a post development UV irradiation treatment which reduces the manufacturable feature-size to be below the resolution limit. The technique is compatible with current manufacturing processes, requires no additional investment, and can be extended to ultra-small feature sizes.

Abstract: A method of manufacturing a semiconductor device with precision patterning is disclosed. A structure of a small dimension is created in a material, such as a semiconductor material, using a first and a second pattern, the patterns being identical but displaced over a distance with respect to each other. Two mask layers are used, wherein the first pattern is etched into the upper mask layer with a selective etch, and the second pattern is created on the upper mask layer or on the lower mask layer at locations where the upper mask layer has been removed. A part of the lower mask layer and/or the upper mask layer is etched according to the second pattern, resulting in a mask formed by remaining parts of the lower and upper mask layers, the mask having a structure with a dimension determined by a displacement of the second pattern with respect to the first pattern.

Abstract: A method of manufacturing a semiconductor device according to the invention is an effective technique for ensuring a sufficient process margin and enabling the formation of a fine pattern in a peripheral circuit region. The method includes forming an anti-reflective layer with a varying thickness in a peripheral circuit region and a cell region, and then over-etching the anti-reflective layer in the peripheral circuit region. The method is capable of improving the data processing speed of a semiconductor device and therefore increases the device efficiency.

Abstract: A photoexposure method photoexposes a photosensitive material layer located over a substrate while using a first set of photoexposure conditions that includes use of a first photoexposure apparatus. The photoexposure method then photoexposes the once photoexposed photosensitive material layer located over the substrate while using a second set of photoexposure conditions that includes use of a second photoexposure apparatus different from the first photoexposure apparatus. One of the first set of photoexposure conditions and the second set of photoexposure conditions does not form a latent image within the photosensitive material layer.

Abstract: A method of improved patterning of indium-tin oxide (ITO) for precision-cutting and aligning a liquid crystal display (LCD) panel includes depositing a transparent ITO layer upon a transparent substrate, depositing a non-transparent plating layer upon the transparent ITO layer and depositing a photoresist layer upon the non-transparent plating layer. The photoresist layer is patterned, exposed and developed to form a plurality of photoresist lines. The photoresist lines are exposed again in an active area only and the plating layer is etched to form a plurality of non-transparent plated lines. The ITO layer is then etched to form a plurality of ITO lines. The photoresist lines are then developed and the non-transparent plated lines are etched away in the active area only. The photoresist that is outside the active area is then removed.

Abstract: A method for double patterning a thin film on a substrate is described. The method includes forming the thin film to be patterned on the substrate, forming a developable anti-reflective coating (ARC) layer on the thin film, and forming a layer of photo-resist on the ARC layer. Thereafter, the layer of photo-resist and the ARC layer are double imaged, and developed. Once the layer of photo-resist is optionally removed, a double patterned ARC layer remains for etching the underlying thin film.

Abstract: A method for double patterning a thin film on a substrate is described. The method includes forming the thin film to be patterned on the substrate, forming a developable anti-reflective coating (ARC) layer on the thin film, and forming a layer of photo-resist on the ARC layer. Thereafter, the layer of photo-resist and the ARC layer are imaged with a first image pattern, and developed, thus forming the first image pattern in the ARC layer. The photo-resist is removed and another layer of photo-resist is formed on the ARC layer. Thereafter, the other layer of photo-resist and the ARC layer are imaged with a second image pattern, and developed, thus forming the second image pattern in the ARC layer. The other photo-resist layer is removed and a double patterned ARC layer remains for etching the underlying thin film.

Abstract: A method of double patterning a thin film is described. The method comprises forming a thin film to be patterned on a substrate, forming an anti-reflective coating (ARC) layer on the thin film, and forming a mask layer on the ARC layer. Thereafter, the mask layer is patterned to form a first pattern and a second pattern therein, and the first and second patterns are partially transferred to the ARC layer using a transfer process, such as an etching process or a developing process. Once the mask layer is removed, the first pattern and second patterns are completely transferred to the ARC layer using an etching process, and the first and second patterns in the ARC layer are transferred to the underlying thin film using another etching process.

Abstract: The invention is directed to increasing the number of semiconductor dice obtained from one semiconductor wafer and enhancing the reliability and yield of the semiconductor dice when the semiconductor dice as products and TEG dice are formed on the semiconductor wafer. TEG die pattern regions are respectively placed on the top and bottom placing a plurality of semiconductor die pattern regions regularly arrayed in a longitudinal direction therebetween. The vertical length of each of the TEG die pattern regions is substantially half of the vertical length of the semiconductor die pattern region. With this reticle, two adjacent TEG die patterns respectively formed by two continuous exposure processes form the area of one semiconductor die pattern. In this manner, the area of the TEG die patterns on the semiconductor wafer is reduced and the yield of the semiconductor dice is increased correspondingly.

Abstract: Masks for patterning material layers of semiconductor devices, methods of manufacturing semiconductor devices, and lithography systems are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a lithography mask, the lithography mask including at least one attenuation region. The at least one attenuation region includes an array of sub-resolution features. A workpiece is provided, the workpiece having a layer of photosensitive material disposed thereon. The layer of photosensitive material is affected using the lithography mask.

Abstract: A method for forming a fine pattern of a semiconductor device includes forming a first photoresist pattern over a semiconductor substrate including an underlying layer. A cross-linking layer is formed on the sidewall of the first photoresist pattern. The first photoresist pattern is removed to form a fine pattern including a silicon polymer. A second photoresist pattern is formed that is coupled to the fine pattern. The underlying layer is etched using the fine pattern and the second photoresist pattern as an etching mask. As a result, the fine pattern has a smaller size than a minimum pitch.

Abstract: A method for forming a fine pattern of a semiconductor device includes forming a first photoresist film pattern over a semiconductor substrate including an underlying layer, exposing the first photoresist film pattern to generate an acid from the first photoresist film pattern, bleaching the first photoresist film pattern, and forming a second photoresist film pattern between the first photoresist patterns.

Abstract: Disclosed herein are a method for forming a highly electrically conductive metal pattern and an electromagnetic interference filter (EMI filter) using a metal pattern formed by the method. The method comprises the steps of (i) coating a photocatalytic compound onto a substrate to form a photocatalytic film, (ii) selectively exposing the photocatalytic film to light to form a latent pattern acting as a nucleus for crystal growth, and (iii) plating the latent pattern to grow metal crystals thereon. The EMI filter comprises the metal pattern. According to the method, a highly electrically conductive metal wiring pattern can be rapidly and efficiently formed, when compared to conventional methods. In addition, the EMI filter comprising the metal pattern not only exhibits excellent performance, but also is advantageous in terms of low manufacturing costs and simple manufacture processes. Accordingly, the EMI filter can be broadly applied to flat panel display devices, such as plasma display panels (PDPs).

Abstract: Novel methods of double patterning a photosensitive resin composition are provided. The methods involve applying the photosensitive composition to a substrate and thermally crosslinking the composition. The crosslinked layer can be used to provide reflection control. Upon exposure to light, the crosslinked polymer (or oligomer or monomer) in the compositions will decrosslink, rendering the light-exposed portions soluble in typical photoresist developing solutions (e.g., alkaline developers). Advantageously, the crosslinked portions of the composition remain insoluble in the solvent used to form the photosensitive composition. As a result, the coating, lithographic, and or developing steps can be repeated multiple times in varying order, depending upon the particular process, without destroying earlier-formed patterns.

Abstract: A manufacturing method of fuel cell having micro sensors and polymer layers is disclosed. It include the following steps of: (1) depositing first polymer layer step, (2) first lithographic processing step, (3) depositing chromium layer step, (4) depositing gold layer step, (5) removing first photo-resist layer step, (6) depositing second polymer layer step, (7) second lithographic processing step, (8) plasma etching step, (9) removing second photo-resist layer step, and (10) complete step. About this invention, the polymer layers can protect the micro sensors. The micro sensors can be installed at a specific location in the flow channel. The entire manufacturing cost is lowered.

Abstract: A process of producing an electroluminescent element is provided. The production process comprises repeating at least twice a step of forming an electroluminescent layer comprising a buffer layer and a luminescent layer by patterning using a photolithographic process, thereby producing an electroluminescent element comprising a patterned electroluminescent layer. The method includes the steps of forming a first pattern part comprising a first buffer layer as the lowermost layer, and coating a solution for forming a second buffer layer in a region including the first pattern part. The first buffer layer is immiscible with the solution for forming the second buffer layer.

Abstract: The present invention relates to preparation of patterned workpieces in the production of semiconductor and other devices. Methods and devices are described utilizing resist and transfer layers over a workpiece substrate. The methods and devices produce small feature dimensions in masks and phase shift masks. The methods described may apply to both masks and direct writing on other workpieces having similarly small features, such as semiconductor, cryogenic, magnetic and optical microdevices.

Abstract: There is disclosed an ink jet recording head in which an image having a high quality level can be recorded for a long period of time by use of a material having a reduced linear expansion coefficient and a satisfactory patterning characteristic. The liquid discharge head comprises: an energy generating element which generates energy for discharging a liquid; a discharge port which discharges the liquid; and a flow path forming member to form a flow path which supplies the liquid to the discharge port, the flow path forming member being formed of a cured material of a resin composition including a cationic polymerizable resin, a cationic photopolymerization initiator, a condensation product of hydrolyzable organic silane compounds, and inorganic fine particles having an average particle diameter of 50 nm or less.

Abstract: A semiconductor device fabrication method applies a diazo novolac photoresist to a semiconductor wafer, followed by light exposure of its entire surface to form an underlying resist layer; forms a surface resist layer thereover; performs patterned-light exposure and heat treatment to the photoresist film consisting of the two resist layers formed; and exposes its entire surface to light, followed by development to process the photoresist film into a resist pattern, where the surface resist layer is in an inverse tapered shape, while the underlying resist layer is in an undercut shape relative to the surface resist layer.

Abstract: A recording medium includes a substrate, and a recording layer formed on the substrate having (a) a recording track band, and (b) recording cells regularly arrayed in the recording track band to form a plurality rows of sub-tracks. The recording cells included in each sub-track are formed apart from each other at a pitch P in the track direction. Nearest neighboring two recording cells, each positioned on adjacent two sub-tracks in the track band, are formed apart from each other at a pitch P/n in the track direction, where 2?n?5.

Abstract: A light-sensitive sheet comprises a support, a first light-sensitive layer and a second light-sensitive layer in this order. Each of the first and second light sensitive layers independently contains a binder, a polymerizable compound and a photo-polymerization initiator. The second light-sensitive layer is more sensitive to light than the first light-sensitive layer. A light-sensitive laminate comprises a substrate, the second light-sensitive layer and the first light-sensitive layer in this order.

Abstract: A method for defining geometries in a semiconductor wafer supported on a plate electrode in a processing chamber includes forming a reusable refractory coated laminar mask. The reusable refractory coated laminar mask is formed by defining the geometries in a laminar mask substrate, forming apertures through the laminar mask substrate, and forming a layer of refractory material over at least one surface of the laminar mask substrate. The reusable refractory coated laminar mask is positioned over the semiconductor wafer. Treating of the semiconductor wafer is performed through the apertures of the reusable refractory coated laminar mask. The treating may be plasma etching or ion etching.

Abstract: A reticle structure and a method of forming a photoresist profile on a substrate using the reticle having a multi-level profile. The reticle comprises (1) a transparent substrate, (2) a partially transmitting 180 degree phase shift film overlying predetermined areas of the transparent substrate to transmit approximately 20 to 70% of incident light, and (3) an opaque film overlying the predetermined areas of the partially transmitting 180 degree phase shift film. The method comprises the following steps: a) depositing a photoresist film over the substrate; b) directing light to the photoresist film through the reticle, and c) developing the photoresist film to form an opening in the resist layer where light only passed thru the substrate, and to remove intermediate thickness of the photoresist film, in the areas where the light passed through the partially transmitting 180 degree phase shift film. In an aspect, the photoresist film is comprised of a lower photoresist layer and an upper photoresist layer.

Abstract: A pattern decomposition and optical proximity correction method for double exposure comprises defining second exposure patterns by performing a logical operation on target patterns and first exposure patterns, comparing the first and second exposure patterns with the target patterns by performing a logical operation on the first and second exposure patterns, performing optical proximity correction on the first exposure patterns to form fourth exposure patterns, performing the optical proximity correction on the second exposure patterns to form fifth exposure patterns, and comparing the fourth and fifth exposure patterns with the target patterns by performing a logical operation on the fourth and fifth exposure patterns.

Abstract: A fabrication method for a damascene bit line contact plug. A semiconductor substrate has a first gate conductive structure, a second gate conductive structure and a source/drain region formed therebetween. A first conductive layer is formed in a space between the first gate conductive structure and the second gate conductive structure to be electrically connected to the source/drain region. An inter-layer dielectric with a planarized surface is formed to cover the first conductive layer, the first gate conductive structure, and the second gate conductive structure. A bit line contact hole is formed in the inter-layer dielectric to expose the top of the first conductive layer. A second conductive layer is formed in the bit line contact hole, in which the combination of the second conductive layer and the first conductive layer serves as a damascene bit line contact plug.

Abstract: A method of forming a lithographic template having an elastomer layer positioned between a body and an imprinting layer, the imprinting layer having a pattern formed thereon.

Abstract: A production method of a semiconductor device which includes the steps of exposing a resist coated on a substrate of a semiconductor device by projecting a first light pattern on the substrate of the semiconductor device the first light pattern being formed by passing light through a first mask, and exposing the resist by projecting a second light pattern on the substrate, the second light pattern being formed by passing light through a second mask. In the step of exposing the resist by projecting the second light pattern, the second light pattern is formed by excimer laser light having an annular shape and passed through the second mask.

Abstract: The presently disclosed invention provides for the fabrication of porous anodic alumina (PAA) films on a wide variety of substrates. The substrate comprises a wafer layer and may further include an adhesion layer deposited on the wafer layer. An anodic alumina template is formed on the substrate. When a rigid substrate such as Si is used, the resulting anodic alumina film is more tractable, easily grown on extensive areas in a uniform manner, and manipulated without danger of cracking. The substrate can be manipulated to obtain free-standing alumina templates of high optical quality and substantially flat surfaces PAA films can also be grown this way on patterned and non-planar surfaces. Furthermore, under certain conditions the resulting PAA is missing the barrier layer (partially or completely) and the bottom of the pores can be readily accessed electrically.

Abstract: An exposure parameter obtaining method comprising forming a charged reference pattern and a plurality of charged exposure patterns at a surface region of a to-be-exposed insulation substrate by projecting a charged beam with a first incident energy using a reference pattern whose exposure parameter has been known beforehand and all of selected exposure patterns to be corrected, forming electron signal images for the charged reference pattern and the plurality of charged exposure patterns on the basis of charged particles including secondary electrons by scanning the surface of the insulation substrate with a charged beam with a second incident energy lower than the first incident energy, and creating, on the basis of the electron signal images, the exposure parameters including at least one of position, focal point, astigmatism, rotation, and magnification for all of the selected exposure patterns to be corrected.

Abstract: Fluorocarbinol- and/or fluoroacid-functionalized silsesquioxane polymers and copolymers are provided. The polymers are substantially transparent to ultraviolet radiation (UV), i.e., radiation of a wavelength less than 365 nm and are also substantially transparent to deep ultraviolet radiation (DUV), i.e., radiation of a wavelength less than 250 nm, including 157 nm, 193 nm and 248 nm radiation, and are thus useful in single and bilayer, positive and negative, lithographic photoresist compositions, providing improved sensitivity and resolution. A process for using the composition to generate resist images on a substrate is also provided, i.e., in the manufacture of integrated circuits or the like.

Abstract: In a pattern formation method, a resist film including a compound having a lactone ring is formed on a substrate of silicon oxide. Then, pattern exposure is performed by selectively irradiating the resist film with exposing light, and the resist film is developed after the pattern exposure so as to form a resist pattern made of the resist film. Subsequently, the lactone ring included in the resist pattern is opened by exposing the resist pattern to an acrylic acid aqueous solution. Thereafter, with the resist pattern where the lactone ring has been opened used as a mask, the substrate is etched, so as to form a recess in a good shape.

Abstract: A method of manufacturing devices with device layers on both sides of a substrate according to an embodiment of the invention includes ensuring that the movements of the substrate during the exposure of the backside are a mirror image of the movements during the exposure of the frontside. In an application of such a method, positioning errors that are characteristic of direction of movement are thus reversed in the backside exposure as compared to the frontside exposure, such that the net overlay error between front and backside is zero or near zero. Embodiments of the invention may be used to reduce overlay errors arising out of certain types of positioning error at no cost, either in machine modifications or throughput.

Abstract: Stabilization of photolithography process parameters, the photomask being used, and the manufacturing method thereof is provided where a formal pattern layout is combined with a dummy pattern. A photomask is manufactured by utilizing the combined pattern layout so that density changes between the pattern structure layers of the multi-layer semiconductor integrated circuits are minimized.

Abstract: A method is provided for improving layer to layer overlay of a second layer pattern on a first layer pattern formed in a substrate. A plurality of first reference marks is placed inside a pattern area on a first layer mask which is used to form the first layer pattern. A plurality of second reference marks is placed on a second layer mask which is used to form the second layer pattern and in which one second reference mark is matched with a first reference mark having the same (x,y) coordinates. Reference mark placement in the resulting first and second layer patterns is determined by metrology to determine an x-deviation and a y-deviation for each matched pair of reference marks. A correction algorithm is then used to calculate adjustments in exposure tool settings for improved overlay of the second layer pattern on the first layer pattern in subsequent exposures.

Abstract: A method for fabricating a liquid crystal display includes: forming a gate electrode on a substrate; sequentially providing an insulation layer, a semiconductor layer and an etch stopper layer on the gate electrode; patterning the etch stopper layer and the semiconductor layer to form an etch stopper layer pattern and a semiconductor layer pattern; removing both side portions of the etch stopper layer pattern to expose the lower semiconductor layer pattern portion; forming a conductive layer on an entire surface of the substrate; patterning the conductive layer to form source and drain electrodes and defining a channel region; forming a passivation layer having a contact part on the entire surface of the substrate; and forming a pixel electrode connected with the drain electrode via the contact part on the passivation layer. An etch stopper can be used without additionally performing a masking process.

Abstract: In accordance with the objectives of the invention a new water soluble negative photoresist is provided for packing-and-unpacking (PAU) processing steps.

Abstract: Methods to reduce the write time for forming mask patterns having angled and non-angled features using electron beam lithography are disclosed. In one exemplary embodiment, non-angled features of the mask pattern are formed by exposure to an electron beam. The orientation of the substrate and a path of the generally rectangular-shaped shot from the electron beam may be relatively altered such that the substrate is exposed to the electron beam to form the angled features as if they were non-angled features. In another exemplary embodiment, the electron beam lithography system determines whether it is necessary to relatively alter the orientation of the substrate and a path of the generally rectangular-shaped shot from the electron beam to form the angled features based on the number of angled features and the time required for relatively altering the orientation. Electron beam lithography systems employing a rotatable stage, rotatable apertures, or both, are also disclosed.

Abstract: A process for forming a pattern contains steps of: forming a first mask pattern on a film to be etched on a substrate; forming a first pattern of the film to be etched by using the first mask pattern as a mask; forming a second mask pattern having a plane shape different from that of the first mask pattern by deforming the first mask pattern; and forming a second pattern of the film to be etched different from the first pattern by using the second mask pattern. By applying the process for forming a pattern, for example, to the formation of a semiconductor layer and source and drain electrodes of a TFT substrate of a liquid crystal display apparatus, the above-stated formation requiring two photoresist process steps in a conventional manufacturing method of a liquid crystal display apparatus can be carried out by only one process step, thereby reducing manufacturing cost thereof.

Abstract: A blank mask for photomasking patterns on an integrated circuit comprises a non-conductive substrate and a layer of conductive material deposited on the substrate covering substantially the entire surface of said substrate. Methods for preventing charge accumulation on a non-conductive region of a mask, which is not covered by a layer of conductive material, are provided. One method comprises controlling electron beams to prevent the beams from striking an outer region for an area more than 90 percent of the outer region when patterning a predetermined feature on the mask. The outer region comprises an area beginning from an edge of the mask and ending at 2 to 6 mm inward from the edge. Another method comprises using a blocker to prevent electron beams from hitting the outer region for an area more than 90 percent of the outer region when patterning a predetermined feature on the substrate.

Abstract: Methods to reduce the write time for forming mask patterns having angled and non-angled features using electron beam lithography are disclosed. In one exemplary embodiment, non-angled features of the mask pattern are formed by exposure to an electron beam. The orientation of the substrate and a path of the generally rectangular-shaped shot from the electron beam may be relatively altered such that the substrate is exposed to the electron beam to form the angled features as if they were non-angled features. In another exemplary embodiment, the electron beam lithography system determines whether it is necessary to relatively alter the orientation of the substrate and a path of the generally rectangular-shaped shot from the electron beam to form the angled features based on the number of angled features and the time required for relatively altering the orientation. Electron beam lithography systems employing a rotatable stage, rotatable apertures, or both, are disclosed.

Abstract: A method is provided for patterning a substrate. In such method a first mask, for example, a front-end-of-line (“FEOL”) mask is fabricated, the first mask including a plurality of first features such as FEOL features which are usable to pattern regular elements and redundancy elements of a substrate such as a microelectronic substrate and/or a micro-electromechanical substrate. The first mask is tested, i.e., inspected for defects in the features. Thereafter, a second sequentially used mask, for example, a back-end-of-line (“BEOL”) mask is fabricated which includes a plurality of second features, e.g., BEOL features, such features being usable to pattern a plurality of interconnections between individual ones of the regular elements and between the regular elements and the redundancy elements. The regular elements and the redundancy elements are patterned using the first mask and the interconnections between them are patterned using the second mask.

Abstract: A method for manufacturing quartz oscillators is provided which permits quartz oscillators having an oscillation frequency, as designed, to be obtained with small variation of individual oscillation frequency and with high reliability. The method for manufacturing quartz oscillators according to the present invention comprises the steps of forming a first resist layer (300) on one surface of a quartz substrate (100), exposing said first resist layer to light of a first amount of exposure to form a patterned first masking layer (210), forming a second resist layer (400) on the other surface of said quartz substrate, exposing said second resist layer to light of a second amount of exposure via said quartz substrate to form a patterned second masking layer (410) by using said first masking layer, and etching said quartz substrate to form quartz pieces (150) by using said patterned first masking layer and said patterned second masking layer.

Abstract: An aspect of the present invention includes a method of lithography to enhance uniformity of critical dimensions of features patterned onto a workpiece. Said workpiece is coated with a coating sensitive to electromagnetic radiation. An electromagnetic radiation source having an illumination intensity is provided. At least one object pixel of electromagnetic radiation is created. A predetermined pattern is exposed, by using said at least one object pixel, on at least a portion of said workpiece in a first exposure pass with a first dose to provide less than full exposure of said coating sensitive to electromagnetic radiation. Said exposing action is repeated at least until said portion of said coating sensitive to electromagnetic radiation is fully exposed, wherein said dose is increased for every following pass. Said fully exposed coating sensitive to electromagnetic radiation is developed.

Abstract: In a semiconductor device manufacturing method, the step of calculating an exposure time of a photoresist includes (a) a step of deciding whether or not a variation of a line width of a device pattern 104 or a resist pattern 102a in a reference chip in a plurality of semiconductor wafers 101 that are manufactured in the past and have the same wafer information as an subject semiconductor wafer 101 is contained within a tolerance over a plurality of semiconductor wafers 101 in the past, and (b) a step of correcting the exposure time every chip by using an exposure correction table 22 if it is decided in the step (a) that the variation falls within the tolerance.

Abstract: The disclosed device is directed towards a shadow mask for ion beams comprising a silicon wafer with a hole pattern arranged therein, wherein the silicon wafer is provided at a side confronting the incident ion beams with a metallic coating which stops the ion beams and dissipates heat, wherein an apertured region of the silicon wafer has a thickness from about 20 ?m to about 200 ?m and apertures in the shadow mask have lateral dimensions from about 0.5 ?m to about 3 ?m.