Multiple Etching Of Substrate Patents (Class 430/316)
  • Patent number: 10527933
    Abstract: A wire grid polarizer includes a base substrate, a wire grid pattern, a first stitch line extending in a first direction, and a second stitch line extending in a second direction which crosses the first direction, and including a first portion and a second portion which are discontinuous from each other, in which the wire grid pattern is evenly formed on all of the base substrate except where the first and second stitch lines exist, and the first and second stitch lines are where the wire grid pattern is unevenly formed.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: January 7, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seung-Won Park, Taewoo Kim, Lei Xie, Daehwan Jang, Dae-Young Lee, Gugrae Jo
  • Patent number: 10409157
    Abstract: A pattern forming method includes forming a first film on a first layer and a second film on the first film. First and second concave portions are formed in the second film. A third film is formed in the concave portions and a fourth film comprising a polymer is formed on the third film. The fourth film can be processed to phase separate and form a pattern in at least the first opening. The pattern formed in the fourth film can be used in patterning films thereunder. A fifth film can be formed which covers the first concave portion and does not cover the second concave portion. The third film in the second concave portion and the first film under the second concave portion can be processed using the fifth film. The first layer can be patterned using the first, second, or third film as a mask.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: September 10, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yusuke Kasahara
  • Patent number: 10175391
    Abstract: Planarization of defects in laser mirror and other optical component manufacture is disclosed. The planarization is performed by first depositing a relatively thick planarization layer, then carrying out a sequential deposition and etch process. The technique takes advantage of the non-uniform material removal rate as a function of etchant incident angle, and effectively buries the inclusion in a thick film with a near planar top surface. The process enables faster, more reliable manufacture of a non-defective high fluence multilayer mirror particularly suitable for high energy laser applications.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: January 8, 2019
    Assignee: Lawrence Livermore National Security, LLC
    Inventors: Christopher Stolz, Jim Folta, Paul B. Mirkarimi, Regina Soufli, Christopher C. Walton, Justin Wolfe, Carmen Menoni, Dinesh Patel
  • Patent number: 9878137
    Abstract: A method of preparing a substantially planar microdevice comprising a plurality of reservoirs is provided. In general, the method comprises forming a plurality of microdevices comprising a plurality of reservoirs from a planar layer of a biocompatible polymer. The method also comprises depositing one or more bioactive agents into the reservoirs. The microdevice is configured to attach to a target tissue and release the bioactive agent in close proximity to the tissue.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: January 30, 2018
    Assignee: The Regents of the University of California
    Inventors: Tejal A Desai, Hariharasudhan D. Chirra
  • Patent number: 9502285
    Abstract: A method of forming trenches is provided. A first layer, a second layer and a third layer are formed on the substrate. A patterned third layer with a plurality of third trenches is formed. A spacer is formed on sidewalls of the third trenches, following by removing a portion of the patterned third layer between the third trenches. By using the spacer and the patterned third layer as a mask, a patterned second layer with a plurality of second trenches is formed. Next, the patterned third layer and the spacer are completely removed, and a block layer is formed on the patterned second layer, filling into the at least one second trench to separate said second trench into at least two parts. The first layer is patterned by using the patterned second layer and the block layer as a mask to form a patterned first layer with first trenches.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: November 22, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Harn-Jiunn Wang, Chin-Lung Lin, Yi-Hsiu Lee
  • Patent number: 9218984
    Abstract: A method for manufacturing a semiconductor device includes forming an etch-target layer over a semiconductor substrate having a lower structure, forming a first mask pattern over the etch-target layer, forming a spacer material layer with a uniform thickness over the etch-target layer including the first mask pattern, forming a second mask pattern on an indented region of the space material layer, and etching the etch-target layer with the first mask pattern and the second mask pattern as an etch mask to form a fine pattern.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: December 22, 2015
    Assignee: SK hynix Inc.
    Inventors: Ki Lyoung Lee, Cheol Kyu Bok, Keun Do Ban, Jung Gun Heo
  • Patent number: 9159661
    Abstract: Integrated circuits with close electrical contacts and methods for fabricating such integrated circuits are provided. The method includes forming a first and a second contact in an interlayer dielectric, and forming a recess between the first and second contact. A etch mask is formed overlying the interlayer dielectric, and the etch mask is removed from over a recess mid-point. A center contact is formed in the interlayer dielectric at the recess mid-point.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: October 13, 2015
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Kai Frohberg, Peter Moll, Heike Scholz
  • Patent number: 9023592
    Abstract: A method of manufacturing a narrow frame touch input sheet having very good anticorrosion properties and suitable for a narrow frame capacitance type touch sensor having a double-layer transparent conductive film pattern.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: May 5, 2015
    Assignee: Nissha Printing Co., Ltd.
    Inventors: Takao Hashimoto, Hirotaka Shigeno, Takaaki Terawaki, Kazuomi Teratani, Shuzo Okumura, Yoshihiro Sakata, Takahiro Suzuki
  • Publication number: 20150064628
    Abstract: Methods of micro- and nano-patterning substrates to form transparent conductive electrode structures or polarizers by continuous near-field optical nanolithography methods using a roll-type photomask or phase-shift mask are provided. In such methods, a near-field optical nanolithography technique uses a phase-shift or photo-mask roller that comprises a rigid patterned externally exposed surface that transfers a pattern to an underlying substrate. The roller device may have an internally disposed radiation source that generates radiation that passes through the rigid patterned surface to the substrate during the patterning process. Sub-wavelength resolution is achieved using near-field exposure of photoresist material through the cylindrical rigid phase-mask, allowing dynamic and high throughput continuous patterning.
    Type: Application
    Filed: April 15, 2013
    Publication date: March 5, 2015
    Applicant: THE REGENTS OF THE UNIVERSITY OF MICHIGAN
    Inventor: Lingjie Jay Guo
  • Patent number: 8877430
    Abstract: Methods of forming microelectronic structures using multilayer processes are disclosed. The methods comprise the use of a developer-soluble protective layer adjacent the substrate surface in a multilayer stack to protect the substrate during pattern transfer. After etching, the pattern is transferred into the developer-soluble protective layer using a developer instead of etching required by previous methods. Conventional developer-soluble anti-reflective coatings and gap-fill materials can be used to form the protective layer. Custom layers with developer solubility can also be prepared. Microelectronic structures formed by the above processes are also disclosed.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: November 4, 2014
    Assignee: Brewer Science Inc.
    Inventors: Carlton Ashley Washburn, James E. Lamb, III, Brian A. Smith, Justin Lee Furse, Kang Le Wang
  • Patent number: 8877422
    Abstract: There is disclosed a resist underlayer film composition, wherein the composition contains a polymer obtained by condensation of, at least, one or more compounds represented by the following general formula (1-1) and/or (1-2), and one or more kinds of compounds and/or equivalent bodies thereof represented by the following general formula (2). There can be provided an underlayer film composition, especially for a trilayer resist process, that can form an underlayer film having reduced reflectance, namely, an underlayer film having optimum n-value and k-value, excellent filling-up properties, high pattern-antibending properties, and not causing line fall or wiggling after etching especially in a high aspect line that is thinner than 60 nm, and a patterning process using the same.
    Type: Grant
    Filed: October 7, 2011
    Date of Patent: November 4, 2014
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Tsutomu Ogihara, Daisuke Kori, Yusuke Biyajima, Toshihiko Fujii, Takeru Watanabe, Takeshi Kinsho
  • Publication number: 20140315133
    Abstract: A method for fabricating a circuit, by defining a first set of resist features on a substrate and corresponding to a first mask layout, followed by defining a second set of resist features on the substrate corresponding to a second mask layout, wherein the second set adds to the first set for rectifying an error in either mask layout. In another aspect, the method is by defining a first set of resist features on a substrate and corresponding to a first mask layout that has an error, etching the substrate while the first set protects selected regions, defining a second set of resist features on the substrate and corresponding to a second mask layout, followed by etching the substrate to selectively remove portions of the selected regions for rectifying the error.
    Type: Application
    Filed: July 1, 2014
    Publication date: October 23, 2014
    Inventor: Krishnakumar Mani
  • Publication number: 20140302440
    Abstract: A method of manufacturing a narrow frame touch input sheet having very good anticorrosion properties and suitable for a narrow frame capacitance type touch sensor having a double-layer transparent conductive film pattern.
    Type: Application
    Filed: April 2, 2014
    Publication date: October 9, 2014
    Applicant: NISSHA PRINTING CO., LTD.
    Inventors: Takao HASHIMOTO, Hirotaka SHIGENO, Takaaki TERAWAKI, Kazuomi TERATANI, Shuzo OKUMURA, Yoshihiro SAKATA, Takahiro SUZUKI
  • Patent number: 8846304
    Abstract: A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: September 30, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Choong-Ryul Ryou, Hee-Sung Kang
  • Patent number: 8835092
    Abstract: There is disclosed a resist underlayer film composition of a multilayer resist film used in lithography including (A) a fullerene derivative having a carboxyl group protected by a thermally labile group and (B) an organic solvent. There can be a resist underlayer film composition of a multilayer resist film used in lithography for forming a resist underlayer in which generation of wiggling in substrate etching can be highly suppressed and the poisoning problem in forming an upper layer pattern using a chemically amplified resist can be avoided, a process for forming the resist underlayer film, a patterning process and a fullerene derivative.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: September 16, 2014
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Takeru Watanabe, Takeshi Kinsho, Tsutomu Ogihara, Katsuya Takemura, Toshihiko Fujii, Daisuke Kori
  • Patent number: 8822138
    Abstract: There is provided a resist underlayer film having both heat resistance and etching selectivity. A composition for forming a resist underlayer film for lithography, comprising a reaction product (C) of an alicyclic epoxy polymer (A) with a condensed-ring aromatic carboxylic acid and monocyclic aromatic carboxylic acid (B). The alicyclic epoxy polymer (A) may include a repeating structural unit of Formula (1): (T is a repeating unit structure containing an alicyclic ring in the polymer main chain; and E is an epoxy group or an organic group containing an epoxy group). The condensed-ring aromatic carboxylic acid and monocyclic aromatic carboxylic acid (B) may include a condensed-ring aromatic carboxylic acid (B1) and a monocyclic aromatic carboxylic acid (B2) in a molar ratio of B1:B2=3:7 to 7:3. The condensed-ring aromatic carboxylic acid (B1) may be 9-anthracenecarboxylic acid and the monocyclic aromatic carboxylic acid (B2) may be benzoic acid.
    Type: Grant
    Filed: August 11, 2010
    Date of Patent: September 2, 2014
    Assignee: Nissan Chemical Industries, Ltd.
    Inventors: Tetsuya Shinjo, Hirokazu Nishimaki, Yasushi Sakaida, Keisuke Hashimoto
  • Patent number: 8758981
    Abstract: A photoresist underlayer composition includes a solvent, and a polysiloxane resin represented by Chemical Formula 1: {(SiO1.5—Y—SiO1.5)x(SiO2)y(XSiO1.5)z}(OH)e(OR1)f.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: June 24, 2014
    Assignee: Cheil Industries, Inc.
    Inventors: Mi-Young Kim, Sang-Kyun Kim, Hyeon-Mo Cho, Chang-Soo Woo, Sang-Ran Koh, Hui-Chan Yun, Woo-Jin Lee, Jong-Seob Kim
  • Patent number: 8758984
    Abstract: A method of forming gate conductor structures. A substrate having thereon a gate electrode layer is provided. A multi-layer hard mask is formed overlying the gate electrode layer. The multi-layer hard mask comprises a first hard mask, a second hard mask, and a third hard mask. A photoresist pattern is formed on the multi-layer hard mask. A first etching process is performed to etch the third hard mask, using the photoresist pattern as a first etch resist, thereby forming a patterned third hard mask. A second etching process is performed to etch the second hard mask and the first hard mask, using the patterned third hard mask as a second etch resist, thereby forming a patterned first hard mask. A third etching process is performed to etch a layer of the gate electrode layer, using the patterned first hard mask as a third etch resist.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: June 24, 2014
    Assignee: Nanya Technology Corp.
    Inventors: Chang-Ming Wu, Yi-Nan Chen, Hsien-Wen Liu
  • Patent number: 8722313
    Abstract: A method of manufacturing a touch screen panel includes a first process, a second process, and a third process. Each of a plurality of first electrode serials includes a plurality of first electrode patterns which are separated from each other, neighboring first electrode patterns are electrically connected to each other via a first connection pattern, and a first insulation pattern electrically insulates the first electrode serial from the second electrode serial at an intersection of the first electrode serial and the second electrode serial.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: May 13, 2014
    Assignee: LG Display Co., Ltd.
    Inventor: Seungmok Shin
  • Patent number: 8715913
    Abstract: The present invention is a silicon-containing resist underlayer film-forming composition containing at least any one of a condensation product and a hydrolysis condensation product or both of a mixture comprising: one or more kinds of a compound (A) selected from the group consisting of an organic boron compound shown by the following general formula (1) and a condensation product thereof and one or more kinds of a silicon compound (B) shown by the following general formula (2). Thereby, there can be provided a resist underlayer film applicable not only to the resist pattern formed of a hydrophilic organic compound obtained by the negative development but also to the resist pattern formed of a hydrophobic compound obtained by the conventional positive development.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: May 6, 2014
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Tsutomu Ogihara, Takafumi Ueda, Fujio Yagihashi
  • Patent number: 8693074
    Abstract: An apparatus is formed from a double active layer silicon on insulator (DSOI) substrate that includes first and second active layers separated by an insulating layer. An electrostatic comb drive is formed from the substrate to include a first comb formed from the first active layer and a second comb formed from the second active layer. The comb drive may be used to impart a tilting motion to a micro-mirror. The method of manufacturing provides comb teeth exhibiting an aspect ratio greater than 1:20, with an offset distance between comb teeth of the first and second combs that is less than about 6 ?m.
    Type: Grant
    Filed: October 30, 2012
    Date of Patent: April 8, 2014
    Assignee: STMicroelectronics International N.V.
    Inventors: Moshe Medina, Pinchas Chaviv, Yaron Fein
  • Patent number: 8680671
    Abstract: A method for transferring a pattern to one or more microelectronic layers. A first mask layer, having a patterned feature, and a second mask layer, having another patterned feature, are formed. The first mask layer and the second mask layer are at least partially covered with a film, and openings are formed in the film by removing the other patterned feature of the second mask layer. A pattern of a microelectronic layer is then defined by patterning the patterned feature of the first mask layer through the openings in the film. In one example, the patterned feature of the first mask layer is defined by forming spacers adjacent to the other patterned feature. In another example, the other patterned feature of the second mask layer is defined by removing a portion of the other patterned feature via an anisotropic etching process.
    Type: Grant
    Filed: January 28, 2009
    Date of Patent: March 25, 2014
    Assignee: Spansion LLC
    Inventor: Tzu-Yen Hsieh
  • Patent number: 8673544
    Abstract: A method for forming openings is provided. First, a substrate with a silicon-containing photo resist layer thereon is provided. Second, a first photo resist pattern is formed on the silicon-containing photo resist layer. Later, a first etching procedure is carried out on the silicon-containing photo resist layer to form a plurality of first openings by using the first photo resist pattern as an etching mask. Next, a second photo resist pattern is formed on the silicon-containing photo resist layer. Then, a second etching procedure is carried out on the silicon-containing photo resist layer to form a plurality of second openings by using the second photo resist pattern as an etching mask.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: March 18, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Pei-Yu Chou, Jiunn-Hsiung Liao
  • Patent number: 8658051
    Abstract: A method of improving lithography resolution on a semiconductor, including the steps of providing a substrate on which a protecting layer, a first etching layer and a photoresist layer are sequentially formed; patterning the photoresist layer to form an opening so as to partially reveal the first etching layer; implanting a first ion into the revealed first etching layer to form a first doped area; and implanting a second ion into the revealed first etching layer to form a second doped area, wherein the first doped area is independent from the second doped area is provided.
    Type: Grant
    Filed: May 12, 2008
    Date of Patent: February 25, 2014
    Assignee: Nanya Technology Corp.
    Inventors: Kuo-Yao Cho, Wen-Bin Wu, Ya-Chih Wang, Chiang-Lin Shih, Chao-Wen Lay, Chih-Huang Wu
  • Patent number: 8623587
    Abstract: Provided are a residue removing liquid composition capable of completely removing a resist residue and a titanium (Ti)-derived residue that remains after dry etching and ashing in via hole formation in a production process for a semiconductor substrate having metal wiring of aluminum (Al) or an Al alloy, at a low temperature in a short time, not corroding parts of an interlayer insulating material, a wiring material and others, and a cleaning method for semiconductor devices using it. The residue removing liquid composition contains (A) ammonium fluoride, (B) methanesulfonic acid, (C) a carbon-carbon triple bond-having compound, (D) a water-soluble organic solvent, and (E) water, wherein the content of (A), (C), (D) and (E) in the residue removing liquid composition is from 0.005 to 2% by mass, from 0.1 to 10% by mass, from 60 to 75% by mass and from 5 to 38% by mass, respectively, and (B) is contained in an amount of from 0.9 to 1.5 times (by mol) the amount of (A).
    Type: Grant
    Filed: July 7, 2009
    Date of Patent: January 7, 2014
    Assignee: Mitsubishi Gas Chemical Company, Inc.
    Inventors: Kyoko Kamata, Keiichi Tanaka, Hiroshi Matsunaga
  • Patent number: 8609323
    Abstract: A method of forming ceramic pattern structures of silicon carbide film includes depositing an electron-beam resist or a photo-resist onto a substrate. A portion of the resist is selectively removed from the substrate to form a resist pattern on the substrate. A film of pre-ceramic polymer that includes silicon and carbon is deposited onto the substrate and resist pattern and the pre-ceramic polymer film is cured. A portion of the cured pre-ceramic polymer film on the resist pattern is removed, thereby forming a pre-ceramic polymer pattern on the substrate. The pre-ceramic polymer pattern is then converted to a ceramic pattern.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: December 17, 2013
    Assignee: University of Massachusetts
    Inventors: Joel M. Therrien, Daniel F. Schmidt
  • Patent number: 8603732
    Abstract: There is disclosed a resist underlayer film-forming composition comprising, at least: a resin (A) obtained by condensing a compound represented by the following general formula (1) with a compound represented by the following general formula (2) by the aid of an acid catalyst; a compound (B) represented by the general formula (1); a fullerene compound (C); and an organic solvent. There can be a resist underlayer film composition in a multi-layer resist film to be used in lithography, which underlayer film is excellent in property for filling up a height difference of a substrate, possesses a solvent resistance, and is not only capable of preventing occurrence of twisting during etching of a substrate, but also capable of providing an excellently decreased pattern roughness; a process for forming a resist underlayer film by using the composition; and a patterning process.
    Type: Grant
    Filed: December 27, 2010
    Date of Patent: December 10, 2013
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Tsutomu Ogihara, Takeru Watanabe, Takeshi Kinsho, Katsuya Takemura, Toshihiko Fujii, Daisuke Kori
  • Patent number: 8598041
    Abstract: Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers formed mandrels is removed and alternating layers, formed of two mutually selectively etchable materials, are deposited around the remaining spacers. Layers formed of one of the materials are then etched, leaving behind vertically-extending layers formed of the other of the materials, which form a mask pattern. Alternatively, instead of depositing alternating layers, amorphous carbon is deposited around the remaining spacers followed by a plurality of cycles of forming pairs of spacers on the amorphous carbon, removing one of the pairs of spacers and depositing an amorphous carbon layer. The cycles can be repeated to form the desired pattern. Because the critical dimensions of some features in the pattern can be set by controlling the width of the spaces between spacers, exceptionally small mask features can be formed.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: December 3, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Sanket Sant, Gurtej Sandhu, Neal R. Rueger
  • Patent number: 8563227
    Abstract: The present disclosure provides a method of making a mask. The method includes providing a substrate having a first attenuating layer on the substrate and a first imaging layer on the first attenuating layer; performing a first exposure to the first imaging layer using a first radiation energy in writing mode; performing a first etching to the first attenuating layer; performing a second etching to the substrate; forming a second imaging layer on the first attenuating layer and the substrate; performing a second exposure to the second imaging layer using a light energy and another mask; and performing a third etching to the first attenuating layer after the second exposure.
    Type: Grant
    Filed: October 15, 2012
    Date of Patent: October 22, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Ming Chen, Ya-Ping Tseng, Ming-Tao Ho
  • Patent number: 8551691
    Abstract: A disclosed method of forming a mask pattern includes forming a first resist film on a film to be etched, opening portions on the first resist film at a predetermined pitch, a first film on the first resist film so as to cover sidewalls of the first opening portions, a second resist film, second opening portions alternately arranged with the first opening portions on the second resist film, and a second film on the second resist film so as to cover sidewalls of the second opening portions, and removing a part of the second film so that the second film is left as first sidewall portions, a part of the first resist film using the first sidewall portions as a mask to form third opening portions, and a part of the first film while leaving the first film as second sidewall portions to form fourth opening portions.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: October 8, 2013
    Assignee: Tokyo Electron Limited
    Inventor: Hidetami Yaegashi
  • Publication number: 20130241358
    Abstract: A method for fabricating a quartz crystal device includes forming a corrosion-resistant film on a first surface and a second surface of the base wafer, forming and exposing a photoresist on the corrosion-resistant film, etching the corrosion-resistant film, and performing wet-etching on through holes. The through hole has, at a +X-axis side, a first inclined surface, a second inclined surface, and a first top formed at an intersection of the first and second inclined surface, and has, at a ?X-axis side, a third inclined surface, a fourth inclined surface, and a second top connecting the third and fourth inclined surfaces. The exposing exposes the first and second surfaces such that a distance from a center in the X-axis direction to the first top becomes equal to a distance from the center to the second top in the base plate.
    Type: Application
    Filed: March 12, 2013
    Publication date: September 19, 2013
    Applicant: NIHON DEMPA KOGYO CO., LTD.
    Inventors: SHUICHI MIZUSAWA, TAKEHIRO TAKAHASHI
  • Patent number: 8455162
    Abstract: A plurality of reticles for printing structures in the same lithography level includes an alignment structure pattern within a same relative location in each reticle. Each set of process segmentations in a grating has a reticle segmentation pitch, which is common across all gratings in the plurality of reticles. Within each pair of alignment structure patterns that occupy the same relative location in any two of the plurality of reticles, the process segmentations in one reticle are shifted relative to the process segmentations in the other reticle by a fraction of a reticle segmentation pitch. After printing all patterns in the plurality of reticles, a composite printed process segmentation structure on the substrate includes printed segmentation structures that are spaced by 1/n times the printed segmentation pitch. The pattern for the next level can be aligned to the composite printed process segmentation structure in a single alignment operation.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: June 4, 2013
    Assignee: International Business Machines Corporation
    Inventors: Allen H. Gabor, Vinayan C. Menon
  • Patent number: 8450048
    Abstract: There is disclosed a method for forming a resist underlayer film of a multilayer resist film having at least three layers used in a lithography, comprising at least; a step of coating a composition for resist underlayer film containing a novolak resin represented by the following general formula (1) obtained by treating a compound having a bisnaphthol group on a substrate; and a step of curing the coated composition for the resist underlayer film by a heat treatment at a temperature above 300° C. and 600° C. or lower for 10 to 600 seconds. There can be provided a method for forming a resist underlayer film, and a patterning process using the method to form a resist underlayer film in a multilayer resist film having at least three layers used in a lithography, gives a resist underlayer film having a lowered reflectance, a high etching resistance, and a high heat and solvent resistances, especially without wiggling during substrate etching.
    Type: Grant
    Filed: September 14, 2009
    Date of Patent: May 28, 2013
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Jun Hatakeyama, Toshihiko Fujii, Tsutomu Ogihara
  • Patent number: 8445185
    Abstract: There are provided a method of manufacturing a piezoelectric vibrating reed capable of improving the reliability of a product by sorting out a defective product correctly, a piezoelectric vibrating reed, a piezoelectric vibrator having a piezoelectric vibrating reed, an oscillator, an electronic apparatus, and a radio-controlled timepiece. In a resist pattern forming step, a resist pattern is formed by performing contact exposure on a photoresist film in a state where a photomask is in close contact with the photoresist film. Before the resist pattern forming step, a photomask treatment step is included in which when a defect is found in an outer shape equivalent region equivalent to the outer pattern in the photomask, a part of a light shielding film pattern is removed to change the shape of the outer shape equivalent region where damage is present.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: May 21, 2013
    Assignee: Seiko Instruments Inc.
    Inventor: Masayuki Kawaguchi
  • Patent number: 8440576
    Abstract: A method for patterning a material is provided. The method includes patterning a second material over a first material over a substrate. A surface portion of the patterned second material is converted to form a third material and a remaining patterned second material, wherein the third material is around the remaining patterned second material. One of the remaining patterned second material and the third material is removed to form a mask. The first material is patterned by using the mask.
    Type: Grant
    Filed: April 25, 2008
    Date of Patent: May 14, 2013
    Assignee: Macronix International Co., Ltd.
    Inventor: Shih-Ping Hong
  • Patent number: 8440388
    Abstract: Silica dielectric films, whether nanoporous foamed silica dielectrics or nonporous silica dielectrics are readily damaged by fabrication methods and reagents that reduce or remove hydrophobic properties from the dielectric surface. The invention provides for methods of imparting hydrophobic properties to such damaged silica dielectric films present on a substrate. The invention also provides plasma-based methods for imparting hydrophobicity to both new and damaged silica dielectric films. Semiconductor devices prepared by the inventive processes are also provided.
    Type: Grant
    Filed: November 28, 2005
    Date of Patent: May 14, 2013
    Assignee: Honeywell International Inc.
    Inventors: Nigel P. Hacker, Michael Thomas, James S. Drage
  • Patent number: 8426112
    Abstract: There is provided a resist underlayer film for lithography causing no intermixing with a photoresist and having a dry etching rate higher than that of the photoresist, and a resist underlayer film forming composition for forming the underlayer film. A resist underlayer film forming composition for lithography comprising: a polymer containing a partial structure of Formula (1): where X1 is a group of Formula (2), Formula (3), Formula (4) or Formula (4-1): and a solvent. The polymer may contain, besides the partial structure of Formula (1), a partial structure of Formula (5): (R1)a(R3)bSi(O—)4?(a+b)??Formula (5) and/or a partial structure of Formula (6): [(R4)cSi(O—)3?c]2Y??Formula (6).
    Type: Grant
    Filed: September 10, 2008
    Date of Patent: April 23, 2013
    Assignee: Nissan Chemical Industries, Ltd.
    Inventors: Makoto Nakajima, Wataru Shibayama, Yuta Kanno
  • Patent number: 8409787
    Abstract: A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: April 2, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Choong-Ryul Ryou, Hee-Sung Kang
  • Patent number: 8399182
    Abstract: A method of fabricating a transflective type liquid crystal display device includes: forming gate and data lines with a gate insulating layer therebetween on a substrate and crossing each other to define a pixel region that includes a switching region, a reflective region, and a transmissive region; forming a thin film transistor corresponding to the switching region and connected to the gate and data lines; forming a first passivation layer on the thin film transistor; forming a reflective plate on the first passivation layer in the reflective region; forming a second passivation layer on the reflective plate; forming a pixel electrode on the second passivation layer and connected to a drain electrode of the thin film transistor; forming a third passivation layer on the pixel electrode.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: March 19, 2013
    Assignee: LG Display Co., Ltd.
    Inventors: Jae-Hyung Lim, Dong-Guk Kim, Jong-Hwae Lee
  • Patent number: 8361337
    Abstract: Nanopatterned substrates can be prepared by a method that includes forming a block copolymer film on a substrate, annealing the block copolymer film, surface reconstructing the annealed block copolymer film, coating an etch-resistant layer on the surface reconstructed block copolymer film, etching the resist-coated block copolymer film to create an etched article comprising a nanopatterned substrate, and separating the etch-resistant layer and the block copolymer film from the nanopatterned substrate. The method is applicable to a wide variety of substrate materials, avoids any requirement for complicated procedures to produce long-range order in the block copolymer film, and avoids any requirement for metal functionalization of the block copolymer.
    Type: Grant
    Filed: March 17, 2008
    Date of Patent: January 29, 2013
    Assignee: The University of Massachusetts
    Inventors: Soojin Park, Thomas P. Russell, Jia-Yu Wang, Bokyung Kim
  • Patent number: 8313889
    Abstract: A hard mask layer and a developable bottom anti-reflective coating (dBARC) layer are formed over a dielectric layer of a substrate. A first photosensitive layer is formed above the dBARC layer, exposed, and developed to form a first pattern. The dBARC layer is developed. The first pattern is etched into the hard mask layer to form a first pattern of openings in the hard mask layer. Following removal of the first photosensitive layer, a second photosensitive layer is formed within the first pattern of openings. The second photosensitive layer is exposed and developed to form a second pattern. The dBARC layer is developed. The second pattern is etched into the hard mask layer to form a second pattern of openings in the hard mask layer. Following the removal of the second photosensitive layer and the dBARC layer, the first and the second patterns are etched into the dielectric layer.
    Type: Grant
    Filed: April 1, 2010
    Date of Patent: November 20, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Vincent Yu, Chih-Yang Yeh, Hung Chang Hsieh
  • Publication number: 20120288802
    Abstract: A method of forming gate conductor structures. A substrate having thereon a gate electrode layer is provided. A multi-layer hard mask is formed overlying the gate electrode layer. The multi-layer hard mask comprises a first hard mask, a second hard mask, and a third hard mask. A photoresist pattern is formed on the multi-layer hard mask. A first etching process is performed to etch the third hard mask, using the photoresist pattern as a first etch resist, thereby forming a patterned third hard mask. A second etching process is performed to etch the second hard mask and the first hard mask, using the patterned third hard mask as a second etch resist, thereby forming a patterned first hard mask. A third etching process is performed to etch a layer of the gate electrode layer, using the patterned first hard mask as a third etch resist.
    Type: Application
    Filed: May 9, 2011
    Publication date: November 15, 2012
    Inventors: Chang-Ming Wu, Yi-Nan Chen, Hsien-Wen Liu
  • Patent number: 8309371
    Abstract: A system and method include forming an optical cavity by positioning a photonic crystal a predetermined distance from a substrate, and creating, within the cavity, a standing wave having a substantially flat wavefront. The standing wave may be created by applying an input wave to a first surface of the photonic crystal. The predetermined distance may be such that a peak intensity of the standing wave is proximate to or a calculated distance from the substrate surface. The peak intensity may vary in relation to the substrate surface. The method may include tuning the peak intensity location within the cavity by shifting the wavelength of the input wave or altering the characteristics of the photonic crystal by an external field. A second photonic crystal may be used on the other side of the substrate to replace the reflecting properties of the substrate, allowing for further smoothing of the wavefront.
    Type: Grant
    Filed: July 21, 2009
    Date of Patent: November 13, 2012
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Paul R. De La Houssaye, J. Scott Rodgers
  • Patent number: 8304172
    Abstract: A method of fabricating a semiconductor device begins by forming a layer of hard mask material on a substrate comprising a layer of semiconductor material and a layer of insulating material overlying the layer of semiconductor material, such that the layer of hard mask material overlies the layer of insulating material. A multiple exposure photolithography procedure is performed to create a combined pattern of photoresist features overlying the layer of hard mask material, and a recess line pattern is in the hard mask material, using the combined pattern of photoresist features. The method continues by covering designated sections of the recess line pattern with a blocking pattern of photoresist features, and forming a pattern of trenches in the insulating material, where the pattern of trenches is defined by the blocking pattern of photoresist features and the hard mask material.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: November 6, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Richard Schultz
  • Patent number: 8288081
    Abstract: The present disclosure provides a method of making a mask. The method includes providing a substrate having a first attenuating layer on the substrate and a first imaging layer on the first attenuating layer; performing a first exposure to the first imaging layer using a first radiation energy in writing mode; performing a first etching to the first attenuating layer; performing a second etching to the substrate; forming a second imaging layer on the first attenuating layer and the substrate; performing a second exposure to the second imaging layer using a light energy and another mask; and performing a third etching to the first attenuating layer after the second exposure.
    Type: Grant
    Filed: April 2, 2007
    Date of Patent: October 16, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Ming Chen, Ya-Ping Tseng, Ming-Tao Ho
  • Patent number: 8263321
    Abstract: An antireflective hardmask composition includes an organic solvent, an initiator, and at least one polymer represented by Formulae A, B, or C as set forth in the specification.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: September 11, 2012
    Assignee: Cheil Industries, Inc.
    Inventors: Kyong Ho Yoon, Jong Seob Kim, Dong Seon Uh, Chang Il Oh, Kyung Hee Hyung, Min Soo Kim, Jin Kuk Lee
  • Patent number: 8257908
    Abstract: [Object] To provide a coating-type underlayer coating forming composition that is applied for multi-ply coating process by thin film resist in order to prevent collapse of resist pattern after development with miniaturization of resist pattern, and that shows a sufficient etching resistance against a semiconductor substrate to be processed on processing of the substrate by having a low dry etching rate compared with the photoresist and substrate. [Means for solving problems] A coating-type underlayer coating forming composition that is used for lithography process by multi-ply coating, comprising a polymer containing a vinylnaphthalene based structural unit and an acrylic acid based structural unit containing an aromatic hydroxy group or a hydroxy-containing ester. A coating-type underlayer coating forming composition further comprising an acrylic acid based structural unit containing an aliphatic cyclic compound-containing ester or an aromatic compound-containing ester.
    Type: Grant
    Filed: August 15, 2006
    Date of Patent: September 4, 2012
    Assignee: Nissan Chemical Industries, Ltd.
    Inventors: Takahiro Sakaguchi, Tomoyuki Enomoto
  • Patent number: 8252516
    Abstract: Embodiments of the invention operate to narrow the track width of a read head used in a disk drive. In one embodiment, a magnetic read head has a track width of about 40 nm or less. The read head is fabricated by a method that includes fabricating a film stack from a substrate, a sensor material, a stop material, a first release material, a mask material, and a photo resist material. The mask material may include a masking substrate material and a second release material. The film stack is processed by forming a read head image in the photo resist material, removing portions of the film stack that lie outside the read head image of the photo resist material, stripping the film stack to remove the photo resist, mask and first release materials, and milling the sensor material according to the read head image.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: August 28, 2012
    Assignee: HGST Netherlands, B.V.
    Inventors: Quang Le, Jui-Lung Li
  • Patent number: 8241823
    Abstract: Provided is a photolithography apparatus including a photomask. The photomask includes a pattern having a plurality of features, in an example, dummy line features. The pattern includes a first region being in the form of a localized on-grid array and a second region where at least one of the features has an increased width. The apparatus may include a second photomask which may define an active region. The feature with an increased width may be adjacent, and outside, the defined active region.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: August 14, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Feng Shieh, Shinn-Sheng Yu, Anthony Yen, Shao-Ming Yu, Chang-Yun Chang, Jeff J. Xu, Clement Hsingjen Wann
  • Patent number: 8222075
    Abstract: A plurality of bit lines s arranged crossing a plurality of first word lines. A first diode is arranged at each cross point of the first word lines and the bit lines. A cathode of the first diode is connected to one of the first word lines. A first variable resistance film configuring the first diode is provided between the anodes of the first diodes and the bit lines, and configures a first memory cell together with each of the first diodes, and further, is used in common to the first diodes.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: July 17, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Eiji Ito