Abstract: The present disclosure provides a method of making a mask. The method includes providing a substrate having a first attenuating layer on the substrate and a first imaging layer on the first attenuating layer; performing a first exposure to the first imaging layer using a first radiation energy in writing mode; performing a first etching to the first attenuating layer; performing a second etching to the substrate; forming a second imaging layer on the first attenuating layer and the substrate; performing a second exposure to the second imaging layer using a light energy and another mask; and performing a third etching to the first attenuating layer after the second exposure.

Abstract: An antireflective hardmask composition includes an organic solvent, an initiator, and at least one polymer represented by Formulae A, B, or C as set forth in the specification.

Abstract: [Object] To provide a coating-type underlayer coating forming composition that is applied for multi-ply coating process by thin film resist in order to prevent collapse of resist pattern after development with miniaturization of resist pattern, and that shows a sufficient etching resistance against a semiconductor substrate to be processed on processing of the substrate by having a low dry etching rate compared with the photoresist and substrate. [Means for solving problems] A coating-type underlayer coating forming composition that is used for lithography process by multi-ply coating, comprising a polymer containing a vinylnaphthalene based structural unit and an acrylic acid based structural unit containing an aromatic hydroxy group or a hydroxy-containing ester. A coating-type underlayer coating forming composition further comprising an acrylic acid based structural unit containing an aliphatic cyclic compound-containing ester or an aromatic compound-containing ester.

Abstract: Embodiments of the invention operate to narrow the track width of a read head used in a disk drive. In one embodiment, a magnetic read head has a track width of about 40 nm or less. The read head is fabricated by a method that includes fabricating a film stack from a substrate, a sensor material, a stop material, a first release material, a mask material, and a photo resist material. The mask material may include a masking substrate material and a second release material. The film stack is processed by forming a read head image in the photo resist material, removing portions of the film stack that lie outside the read head image of the photo resist material, stripping the film stack to remove the photo resist, mask and first release materials, and milling the sensor material according to the read head image.

Abstract: Provided is a photolithography apparatus including a photomask. The photomask includes a pattern having a plurality of features, in an example, dummy line features. The pattern includes a first region being in the form of a localized on-grid array and a second region where at least one of the features has an increased width. The apparatus may include a second photomask which may define an active region. The feature with an increased width may be adjacent, and outside, the defined active region.

Abstract: A plurality of bit lines s arranged crossing a plurality of first word lines. A first diode is arranged at each cross point of the first word lines and the bit lines. A cathode of the first diode is connected to one of the first word lines. A first variable resistance film configuring the first diode is provided between the anodes of the first diodes and the bit lines, and configures a first memory cell together with each of the first diodes, and further, is used in common to the first diodes.

Abstract: A resist material utilized in photolithography patterning includes a first material, and a second material dispersed in the first material. The second material is capable of diffusing to a top surface of the resist material, and has an etch rate different from that of the first material.

Abstract: A memory cell device has a bottom electrode and a top electrode, a plug of memory material in contact with the bottom electrode, and a cup-shaped conductive member having a rim that contacts the top electrode and an opening in the bottom that contacts the memory material. Accordingly, the conductive path in the memory cells passes from the top electrode through the conductive cup-shaped member, and through the plug of phase change material to the bottom electrode.

Abstract: A method of forming a pattern including: forming an underlayer film on a support using an underlayer film-forming material, forming a hard mask on the underlayer film using a silicon-based hard mask-forming material, forming a first resist film by applying a chemically amplified positive resist composition to the hard mask, forming a first resist pattern by selectively exposing the first resist film through a first mask pattern and then performing developing, forming a first pattern by etching the hard mask using the first resist pattern as a mask, forming a second resist film by applying a chemically amplified positive silicon-based resist composition to the first pattern and the underlayer film, forming a second resist pattern by selectively exposing the second resist film through a second mask pattern and then performing developing, and forming a second pattern by etching the underlayer film using the first pattern and the second resist pattern as a mask.

Abstract: A processing system and method for chemical oxide removal (COR) is presented, wherein the processing system comprises a first treatment chamber and a second treatment chamber, wherein the first and second treatment chambers are coupled to one another. The first treatment chamber comprises a chemical treatment chamber that provides a temperature controlled chamber, and an independently temperature controlled substrate holder for supporting a substrate for chemical treatment. The substrate is exposed to a gaseous chemistry, such as HF/NH3, under controlled conditions including surface temperature and gas pressure. The second treatment chamber comprises a heat treatment chamber that provides a temperature controlled chamber, thermally insulated from the chemical treatment chamber. The heat treatment chamber provides a substrate holder for controlling the temperature of the substrate to thermally process the chemically treated surfaces on the substrate.

Abstract: A method of forming a contact hole is provided. A pattern is formed in a photo resist layer. The pattern is exchanged into a silicon photo resist layer to form a first opening. Another pattern is formed in another photo resist layer. The pattern is exchanged into a silicon photo resist layer to form a second opening. The pattern having the first, and second openings is exchanged into the interlayer dielectric layer, and etching stop layer to form the contact hole. The present invention has twice exposure processes and twice etching processes to form the contact hole having small distance.

Abstract: The present invention is to provide a method for smoothing the optical surface having a concave defect of an optical component for EUVL. The present invention relates to a method for smoothing the optical surface of an optical component for EUVL, comprising irradiating, with an excimer laser having a wavelength of 250 nm or less with a fluence of 0.5 to 2.0 J/cm2, the optical surface having a concave defect of an optical component for EUV lithography (EUVL), the optical component being made of a TiO2-containing silica glass material comprising SiO2 as a main component.

Abstract: Methods of forming a semiconductor device can be provided by simultaneously forming a plurality of mask patterns using self-aligned reverse patterning, including respective mask pattern elements having different widths.

Abstract: There is provided a resist underlayer film forming composition for lithography for forming a resist underlayer film capable of being used as a hardmask. A resist underlayer film forming composition for lithography comprising a silane compound containing an anion group, wherein the silane compound containing an anion group is a hydrolyzable organosilane in which an organic group containing an anion group is bonded to a silicon atom and the anion group forms a salt structure, a hydrolysis product thereof, or a hydrolysis-condensation product thereof. The anion group may be a carboxylic acid anion, a phenolate anion, a sulfonic acid anion, or a phosphonic acid anion. The hydrolyzable organosilane may be a compound of Formula (1): R1aR2bSi(R3)4?(a+b) (1).

Abstract: Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.

Abstract: There is provided an underlayer coating that is used as an underlayer of photoresists in lithography process of the manufacture of semiconductor devices and that has a high dry etching rate in comparison to the photoresists depending on the type of etching gas, does not intermix with the photoresists, and is capable of flattening the surface of a semiconductor substrate having holes of a high aspect ratio; and an underlayer coating forming composition for forming the underlayer coating. The underlayer coating forming composition for forming by light irradiation an underlayer coating used as an underlayer of a photoresist in a lithography process of the manufacture of semiconductor devices, includes a polymerizable compound containing 5 to 45% by mass of silicon atom (A), a photopolymerization initiator (B), and a solvent (C).

Abstract: Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated circuit, are formed by processing a substrate through a mask. The mask is formed by patterning a photoresist layer which simultaneously defines mask elements corresponding to features in the array, interface and periphery areas of the integrated circuit. The pattern is transferred to an amorphous carbon layer. Sidewall spacers are formed on the sidewalls of the patterned amorphous carbon layer. A layer of protective material is deposited and then patterned to expose mask elements in the array region and in selected parts of the interface or periphery areas. Amorphous carbon in the array region or other exposed parts is removed, thereby leaving a pattern including free-standing, pitch multiplied spacers in the array region.

Abstract: A method for etching a pattern on a surface is disclosed. A mask layer is disposed over a surface and a resist is disposed over the mask layer. The resist is exposed to light through the mask exposing primary pattern and sidelobe regions. The resist is developed and the mask layer is etched according to the resist pattern. A first material is deposited over the mask layer, wherein a gap is formed beneath the material and over the primary pattern region. The material is etched back so that the gap is exposed, and the primary pattern region is etched using the first material as a mask.

Abstract: Disclosed are probe card needles manufactured using microfabrication technology, a method for manufacturing the probe card needles, and a probe card having the probe card needles. The probe needles are manufactured by forming, on a ceramic board, probe needle bases made of conductive metal, and a polymeric elastomer layer, by using photolithography and a photoresist, and continuously depositing conductive metal layers on the probe needle bases in such a manner as to be supported by the polymeric elastomer layer. The probe card comprises: a printed circuit board (PCB) which is connected to a test head for transmitting an electrical signal from a tester; a ceramic board located below the PCB and electrically connected to the PCB by a plurality of interface pins; a jig for mechanically holding the interface pins and the multilayer ceramic board to the PCB; and a plurality of probe needles attached to the lower surface of the multilayer ceramic board and making contact with electrical/electronic devices.

Abstract: A method for fabricating a integrated circuit is disclosed. An exemplary method includes providing a substrate; forming a hard mask layer over the substrate; forming a patterned photoresist layer over the hard mask layer, such that portions of the hard mask layer are exposed; performing a dry etching process to remove the exposed portions of the hard mask layer; removing the patterned photoresist layer using at least one of a nitrogen plasma ashing and a hydrogen plasma ashing; and performing a wet etching process to remove remaining portions of the hard mask layer.

Abstract: A method for forming a fine pattern of a semiconductor device comprises forming a spin-on-carbon layer over an underlying layer, forming an anti-reflection pattern including a silicon containing polymer with a first etching mask pattern, forming a photoresist pattern including a silicon containing polymer with a second etching mask pattern between elements of the first etching mask pattern, and etching the spin-on-carbon layer with the etching mask patterns to reduce the process steps and the manufacturing cost, thereby obtaining a uniform pattern profile.

Abstract: Disclosed is a method for fabricating a liquid crystal display device comprising: providing a first substrate having a pixel portion and a pad portion; sequentially laminating a gate insulating layer, a semiconductor layer and a first conductive layer on the first substrate where a gate electrode is formed; forming a first PR pattern, which is patterned relatively thin on a channel region of a transistor to be formed, on the first conductive layer with a half-tone mask; patterning the first conductive layer with the first PR pattern; forming a second PR pattern which is aligned with an outer periphery of the first conductive layer by performing a first ashing process on the first PR pattern; patterning the semiconductor layer using the second PR pattern; forming source/drain electrodes using the second PR pattern; forming a passivation layer and a pixel electrode on the first substrate; attaching a second substrate to the first substrate; and forming a liquid crystal layer between the first substrate and the

Abstract: Methods for forming grating profiles in semiconductor laser structures comprise the steps of providing a semiconductor wafer comprising a wafer substrate, an etch stop layer disposed over the wafer substrate, a grating layer disposed over the etch stop layer, an etch mask layer disposed over the grating layer, and a photoresist layer disposed over the etch mask layer, forming a photoresist grating pattern, transferring the photoresist grating pattern into the grating layers via dry etching, and removing the photoresist layer, selectively wet etching the grating layer to form the grating profile in the grating layer. The placement of the grating layer between the etch mask and etch stop layers controls the selective wet etching step. The method also comprises removing the etch mask layer via selective wet etching without altering the grating profile, and regrowing an upper cladding layer to produce the semiconductor laser structure.

Abstract: A semiconductor device manufacturing method, a semiconductor device manufacturing equipment and a computer readable medium storing a computer program provide for easily identifying a cause of a deviation of pattern dimensions from the objective dimension. A first storage section stores a relation between a PEB temperature and a photoresist dimension of a post-lithography. A second storage section stores a relation between a PEB temperature and a post-etching dimension. A primary correction section determines a first corrected PEB temperature for conforming the photoresist dimension of a post-lithography to the objective dimension, using the relation data stored in the first storage section. A secondary correction section determines the second corrected PEB temperature for conforming the post-etching dimension using the first corrected PEB temperature to the objective dimension, using the relation data stored in the second storage section.

Abstract: There is disclosed a substrate processing method by a multi-patterning technique, which comprises a lithography process and an etching process, each of the processes is performed to one substrate at least twice. The substrate processing method is performed by using a substrate processing system comprising a plurality of process units for performing respective steps of the lithography process. When a second lithography process is performed to a substrate, process unit(s) for performing one or more steps of the second lithography process to be used in the second lithography process is automatically selected based on the process history of the first lithography process in such a way that the process unit(s) to be used in the second lithography process is (are) identical to the processed unit(s) used in the first lithography process.

Abstract: A lithographic structure consisting essentially of: an organic antireflective material disposed on a substrate; a vapor-deposited RCHX material, wherein R is one or more elements selected from the group consisting of Si, Ge, B, Sn, Fe and Ti, and wherein X is not present or is one or more elements selected from the group consisting of O, N, S and F; and a photoresist material disposed on the RCHX material. The invention is also directed to methods of making the lithographic structure, and using the structure to pattern a substrate.

Abstract: A method of fabricating a transflective type liquid crystal display device includes: forming gate and data lines with a gate insulating layer therebetween on a substrate and crossing each other to define a pixel region that includes a switching region, a reflective region, and a transmissive region; forming a thin film transistor corresponding to the switching region and connected to the gate and data lines; forming a first passivation layer on the thin film transistor; forming a reflective plate on the first passivation layer in the reflective region; forming a second passivation layer on the reflective plate; forming a pixel electrode on the second passivation layer and connected to a drain electrode of the thin film transistor; forming a third passivation layer on the pixel electrode.

Abstract: A photoresist composition includes about 100 parts by weight of resin mixture including novolak resin and acryl resin and about 10 parts to about 50 parts by weight of naphthoquinone diazosulfonic acid ester. A weight-average molecular weight of the novolak resin is no less than about 30,000. A weight-average molecular weight of the acryl resin is no less than about 20,000. The acryl resin makes up about 1% to about 15% of the total weight of the resin mixture. When a photoresist film formed using the photoresist composition is heated, a profile variation of the photoresist composition is relatively small. Therefore, a residual photoresist film has a uniform thickness, and a short circuit and/or an open defect in a TFT substrate may be reduced.

Abstract: Some embodiments include methods of patterning materials. A mass may be formed over a material, and a first mask may be formed over the mass. First spacers may be formed along features of the first mask, and then the first mask may be removed to leave a second mask corresponding to the first spacers. A pattern of the second mask may be partially transferred into the mass to form an upper portion of the mass into a third mask. The first spacers may be removed from over the third mask, and then second spacers be formed along features of the third mask. The second spacers are a fourth mask. A pattern of the fourth mask may be transferred into a bottom portion of the mass, and then the bottom portion may be used as a mask during processing of the underlying material.

Abstract: After forming a lower layer film, an intermediate layer film and a first resist film on a substrate, a first resist pattern is formed by performing first exposure. Then, after a first intermediate layer pattern is formed by transferring the first resist pattern onto the intermediate layer film, a second resist film is formed thereon, and a second resist pattern is formed by performing second exposure. Thereafter, a second intermediate layer pattern is formed by transferring the second resist pattern onto the intermediate layer film. After removing the second resist film, the lower layer film is etched by using the second intermediate layer pattern as a mask, so as to form a lower layer pattern.

Abstract: After formation of an underlayer film and an intermediate layer film, a resist pattern formed by the first pattern exposure with the first resist film and the second pattern exposure with the second resist film is transferred to the intermediate layer film. The underlayer film is etched using an intermediate layer pattern as a mask to form an underlayer film pattern. Herein, the first and second resist films are chemically amplified resist films. The second resist film contains a greater amount of additive which improves the sensitivity of the resist or which improves the alkaline solubility of resist exposed part.

Abstract: A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized.

Abstract: In accordance with the invention, there are methods of making an integrated circuit, an integrated circuit device, and a computer readable medium. A method can comprise forming a first layer over a semiconductor substrate, forming a first mask layer over the semiconductor substrate, and using the first mask layer to pattern first features. The method can also include forming a second mask layer over the first features, using the second mask layer to pattern portions of the first features, removing the second mask layer, and removing the first mask layer.

Abstract: The present disclosure is directed a method for preparing a system of photomask patterns for implementing a drawn pattern on a substrate with a multi-patterning lithography process. The method comprises receiving data describing a drawn pattern. A first photomask pattern is formed for implementing a region of the drawn pattern on the substrate. A second photomask pattern is formed comprising one or more pattern features having longitudinal edges for implementing the region of the drawn pattern on the substrate, wherein at least 90% of all the longitudinal edges of the second photomask pattern that are positioned within the region are oriented in substantially the same direction. Both a system for forming the photomask patterns and a process for patterning a device using the photomask patterns are also disclosed.

Abstract: A method of forming a lithographic template, the method including, inter alia, creating a multi-layered structure, by forming, on a body, a conducting layer, and forming on the conducting layer, a patterned layer having protrusions and recessions, the recessions exposing portions of the conducting layer; depositing a hard mask material anisotropically on the multi-layered structure covering a top surface of the patterned layer and the portions of the conducting layer; removing the patterned layer by a lift-off process, with the hard mask material remaining on the portions of the conducting layer; positioning a resist pattern on the multi-layered structure to define a region of the multi-layered structure; and selectively removing portions of the multi-layered structure in superimposition with the region using the hard mask material as an etching mask.

Abstract: There is provided a composition for forming a resist underlayer film that can be homogeneously applied and a sublimate is suppressed during the thermal curing. There is also provided a composition for forming a resist underlayer film having a high selection ratio of dry etching relative to a resist applied thereon. A composition for forming a resist underlayer film for lithography comprising: a polysilane compound having a unit structure of Formula (1): (where R1 and R2 are independently a group of —X—Y (where X is an oxygen atom, a C1-18 alkylene group or a group of —OCnH2n— (where n is an integer of 1 to 18) and Y is a lactone ring or an adamantane ring), or one of R1 and R2 is the group of —X—Y and another thereof is an aryl group, a methyl group, an ethyl group or a C3-6 cycloalkyl group); and an organic solvent.

Abstract: A circuitized substrate which utilizes at least one internal (embedded) resistor as part thereof, the resistor comprised of a material including resin and a quantity of powders of nano-particle and/or micro-particle sizes. The resistor serves to decrease the capacitance in the formed circuit while only slightly increasing the high frequency resistance, thereby improving circuit performance through the substantial elimination of some discontinuities known to exist in structures like these. An electrical assembly (substrate and at least one electrical component) is also provided.

Abstract: A processing system and method for chemical oxide removal (COR) is presented, wherein the processing system comprises a first treatment chamber and a second treatment chamber, wherein the first and second treatment chambers are coupled to one another. The first treatment chamber comprises a chemical treatment chamber that provides a temperature controlled chamber, and an independently temperature controlled substrate holder for supporting a substrate for chemical treatment. The substrate is exposed to a gaseous chemistry, such as HF/NH3, under controlled conditions including surface temperature and gas pressure. The second treatment chamber comprises a heat treatment chamber that provides a temperature controlled chamber, thermally insulated from the chemical treatment chamber. The heat treatment chamber provides a substrate holder for controlling the temperature of the substrate to thermally process the chemically treated surfaces on the substrate.

Abstract: A method for double patterning a thin film on a substrate is described. The method includes forming the thin film to be patterned on the substrate, forming a developable anti-reflective coating (ARC) layer on the thin film, and forming a layer of photo-resist on the ARC layer. Thereafter, the layer of photo-resist and the ARC layer are imaged with a first image pattern, and developed, thus forming the first image pattern in the ARC layer. The photo-resist is removed and another layer of photo-resist is formed on the ARC layer. Thereafter, the other layer of photo-resist and the ARC layer are imaged with a second image pattern, and developed, thus forming the second image pattern in the ARC layer. The other photo-resist layer is removed and a double patterned ARC layer remains for etching the underlying thin film.

Abstract: An AT cut quartz crystal resonator element includes a quartz crystal element piece having an exciting part formed from an AT cut quartz crystal plate in a rectangular shape having an X-axis direction of a quartz crystal set to a long side, and an exciting electrode formed on each of front and back main surfaces of the exciting part, in which each side surface in the longitudinal direction of the exciting part is composed of two faces, an m-face of a quartz crystal and a crystal face other than the m-face.

Abstract: Silica dielectric films, whether nanoporous foamed silica dielectrics or nonporous silica dielectrics are readily damaged by fabrication methods and reagents that reduce or remove hydrophobic properties from the dielectric surface. The invention provides for methods of imparting hydrophobic properties to such damaged silica dielectric films present on a substrate. The invention also provides plasma-based methods for imparting hydrophobicity to both new and damaged silica dielectric films. Semiconductor devices prepared by the inventive processes are also provided.

Abstract: A method for fabricating openings is provided. A dielectric layer is formed on a substrate, and a first patterned mask layer is formed on the dielectric layer along a first direction. A second patterned mask layer is then formed on the dielectric layer along a second direction which intersects with the first direction. A portion of the dielectric layer is removed using the first patterned mask layer and the second patterned mask layer as a mask so as to from the openings. The dielectric layer, the first patterned mask layer and the second patterned mask layer have different etching selectivities.

Abstract: There is provided a resist underlayer film for lithography causing no intermixing with a photoresist and having a dry etching rate higher than that of the photoresist, and a resist underlayer film forming composition for forming the underlayer film. A resist underlayer film forming composition for lithography comprising: a polymer containing a partial structure of Formula (1): where X1 is a group of Formula (2), Formula (3), Formula (4) or Formula (4-1): and a solvent. The polymer may contain, besides the partial structure of Formula (1), a partial structure of Formula (5): (R1)a(R3)bSi(O—)4?(a+b)??Formula (5) and/or a partial structure of Formula (6): [(R4)cSi(O—)3?c]2Y??Formula (6).

Abstract: Disclosed are the deactivation mechanism and chemistry platforms that make high-silicon hardmask films photo-imageable like positive-tone photoresist for microphotolithography. The deactivation mechanism requires a catalyst to promote crosslinking reactions, and a photoacid generator to deactivate the catalyst. The initial hardmask films are soluble in developers. If not radiated, films become insoluble in developers due to crosslinking reactions promoted by catalyst. If radiated, films remain soluble in developers due to deactivation of catalyst by photoacid generator. Compositions of positive-tone photo-imageable hardmask based on the chemistry of polysiloxane and polysilsesquioxanes are disclosed as well. Also disclosed is a method of modifying polysiloxane and polysilsesquioxane films for controlled diffusion of catalysts, photoacid generators, and quenchers.

Abstract: A photoresist composition and methods using the photoresist composition in multiple exposure/multiple layer processes. The photoresist composition includes a polymer comprising repeat units having a hydroxyl moiety; a photoacid generator; and a solvent. The polymer when formed on a substrate is substantially insoluble to the solvent after heating to a temperature of about 150° C. or greater. One method includes forming a first photoresist layer on a substrate, patternwise exposing the first photoresist layer, forming a second non photoresist layer on the substrate and patterned first photoresist layer. Another method includes forming a first photoresist layer on a substrate, patternwise exposing the first photoresist layer, forming a second photoresist layer on the substrate and patterned first photoresist layer and patternwise exposing the second photoresist layer.

Abstract: A method for forming a ring pattern is disclosed. The ring pattern has a first wall and a second wall. The method includes the following steps: (a) providing a substrate; (b) forming a dielectric layer on the substrate; (c) forming a first patterned photoresist layer on the dielectric layer, the first patterned photoresist layer defining the first wall; (d) etching the dielectric layer to a predetermined depth by using the first patterned photoresist as a mask, and then removing the first patterned photoresist layer; (e) forming a second patterned photoresist layer on the dielectric layer, the second patterned photoresist layer defining the second wall; (f) etching the dielectric layer by using the second patterned photoresist layer as a mask so as to form the ring pattern having the first wall and the second wall.

Abstract: Some embodiments include formation of polymer spacers along sacrificial material, removal of the sacrificial material, and utilization of the polymer spacers as masks during fabrication of integrated circuitry. The polymer spacer masks may, for example, be utilized to pattern flash gates of a flash memory array. In some embodiments, the polymer is simultaneously formed across large sacrificial structures and small sacrificial structures. The polymer is thicker across the large sacrificial structures than across the small sacrificial structures, and such difference in thickness is utilized to fabricate high density structures and low-density structures with a single photomask.

Abstract: A method for forming a damascene structure utilizes dual hard mask layers and a thin etch stop layer, and does not require a sacrificial layer within the via. A floating etch stop layer can additionally be used. The dual hard masks may be formed of dielectric and neither of the hard masks is required to contain metal. The thin etch stop layer reduces capacitance problems.

Abstract: A composition for the organic hard mask includes a polyamic acid compound, and a method for forming a pattern is used in a manufacturing process of semiconductor devices by coating the composition for organic hard mask film on an underlying layer, and depositing a second hard mask film with a silicon nitride SiON film thereon to form a double hard mask film having an excellent etching selectivity, thereby obtaining a uniform pattern.

Abstract: A method for transferring a pattern to one or more microelectronic layers. A first mask layer, having a patterned feature, and a second mask layer, having another patterned feature, are formed. The first mask layer and the second mask layer are at least partially covered with a film, and openings are formed in the film by removing the other patterned feature of the second mask layer. A pattern of a microelectronic layer is then defined by patterning the patterned feature of the first mask layer through the openings in the film. In one example, the patterned feature of the first mask layer is defined by forming spacers adjacent to the other patterned feature. In another example, the other patterned feature of the second mask layer is defined by removing a portion of the other patterned feature via an anisotropic etching process.