Abstract: A process for prohibiting amino group transport from the top surface of a layered semiconductor wafer to a photoresist layer introduces a thin film oxynitride over the silicon nitride layer using a high temperature step of nitrous oxide (N2O) plus oxygen (O2) at approximately 300° C. for about 50 to 120 seconds. By oxidizing the silicon nitride layer, the roughness resulting from the adverse affects of amino group transport eliminated. Moreover, this high temperature step, non-plasma process can be used with the more advanced 193 nanometer technology, and is not limited to the 248 nanometer technology. A second method for exposing the silicon nitride layer to an oxidizing ambient, prior to the application of antireflective coating, introduces a mixture of N2H2 and oxygen (O2) ash at a temperature greater than or equal to 250° C. for approximately six minutes. This is followed by an O2 plasma clean and/or an Ozone clean, and then the subsequent layering of the ARC and photoresist.

Abstract: Supports (40) of microelectronic devices (10) are provided with underfill apertures (60) which facilitate filling underfill gaps (70) with underfill material (74). The underfill aperture may have a longer first dimension (62) and a shorter second dimension (64). In some embodiments, a method of filling the underfill gap (70) employs a removable stencil (80). If so desired, a stencil (80) can be used to fill multiple underfill gaps through multiple underfill apertures in a single pass.

Abstract: A method for patterning a carbon-containing substrate utilizing a patterned layer of a resist material as a mask and then safely removing the mask from the substrate without adversely affecting the substrate, comprising sequential steps of: (a) providing a substrate including a surface comprising carbon; (b) forming a thin metal layer on the substrate surface; (c) forming a layer of a resist material on the thin metal layer; (d) patterning the layer of resist material; (e) patterning the substrate utilizing the patterned layer of resist material as a pattern-defining mask; and (f) removing the mask utilizing the thin metal layer as a wet strippable layer or a plasma etch/ash stop layer.

Abstract: A polymer used for a negative type resist composition having a first repeating unit of a Si-containing monomer unit, a second repeating unit having a hydroxy group or an epoxy ring and copolymerized with the first repeating unit is provided.

Abstract: A process and related structure are disclosed for using photo-definable layers that may be selectively converted to insulative materials in the manufacture of semiconductor devices, including for example dynamic random access memories (DRAMs), synchronous DRAMs (SDRAMs), static RAMs (SRAMs), FLASH memories, and other memory devices. One possible photo-definable material for use with the present invention is plasma polymerized methylsilane (PPMS), which may be selectively converted into photo-oxidized siloxane (PPMSO) through exposure to deep ultra-violet (DUV) radiation using standard photolithography techniques. According to the present invention, structures may be formed by converting exposed portions of a photo-definable layer to an insulative material and by using the non-exposed portions in a negative pattern scheme, or the exposed portions in a positive pattern scheme, to transfer a pattern into to an underlying layer.

Abstract: The invention includes methods of fabricating integrated circuitry and semiconductor processing polymer residue removing solutions. In one implementation, a method of fabricating integrated circuitry includes forming a conductive metal line over a semiconductor substrate. The conductive line is exposed to a solution comprising an inorganic acid, hydrogen peroxide and a carboxylic acid buffering agent. In one implementation, a method of fabricating integrated circuitry includes forming an insulating layer over a semiconductor substrate. A contact opening is at least partially formed into the insulating layer. The contact opening is exposed to a solution comprising an inorganic acid, hydrogen peroxide and a carboxylic acid buffering agent. In one implementation, a semiconductor processing polymer residue removing solution comprises an inorganic acid, hydrogen peroxide and a carboxylic acid buffering agent. Other aspects and implementations are contemplated.

Abstract: A method of utilizing a multilayer photoresist to form contact holes and/or conductors utilizing a dual damascene process includes utilizing layered photoresists. A contact in a conductive line can be formed in a single deposition step or in a two-stage deposition step. Image layers can remain as part of the interconnect structure or be removed by a polishing technique. The process can be utilized for any conductive structures provided above a substrate of an integrated circuit.

Abstract: It is an object to provide a technique for removing a resist favorably without leaving residue in the case of using a nonaqueous resist stripper. According to the present invention, in order to achieve the object, when a resist pattern is removed by using the nonaqueous resist stripper, it becomes easier to remove the resist pattern after dry etching or ion doping, by performing exposure treatment on the resist pattern. After a resist pattern is formed from a DNQ-novolac resin type of positive resist composition, the resist pattern is irradiated with light within the range of photosensitive wavelength of the DNQ photosensitizer, thereby removing the resist pattern with the nonaqueous resist stripper.

Abstract: A method for depositing a trench oxide filling layer (300) on a trenched substrate (224) utilizes the surface sensitivity of dielectric materials such as O3/TEOS. Such materials have different desposition rates on differently constituted surfaces at different levels on the trenched substrate (224) so that the surface profile of the deposited layer (300) is substantially self-planarized. Depositing the dielectric material on a silicon trench (228) produces a high quality filling layer, and cleaning the trench (228) prior to desposition can increase the quality. After desposition, an oxidizing anneal can be performed to grow a thermal oxide (308) at the trench surfaces and densify the dielectric material. A chemical mechanical polish can be used to remove the excess oxide material above an etch stop layer (226) of the substrate (224) which can be formed of LPCVD nitride or CVD anti-reflective coating.

Abstract: A method of producing a thin film transistor is described. The doped amorphous silicon is formed by ion implantation. The photoresist used by the ion implantation is formed by backside exposure or by half-tone photo mask, and a photo mask can therefore be eliminated.

Abstract: A substrate material for LIGA applications w hose general composition is Ti/Cu/Ti/SiO2. The SiO2 is preferably applied to the Ti/Cu/Ti wafer as a sputtered coating, typically about 100 nm thick. This substrate composition provides improved adhesion for epoxy-based photoresist materials, and particularly the photoresist material SU-8.

Abstract: The removal of defect particles that may be created during polysilicon hard mask etching, and that are embedded within the polysilicon layer, is disclosed. Oxide is first grown in the polysilicon layer exposed through the patterned hard mask layer, so that the defect particle becomes embedded within the oxide. Oxide growth may be accomplished by rapid thermal oxidation (RTO). The oxide is then exposed to an acidic solution, such as hydrofluoric (HF) acid, to remove the oxide and the embedded defect particle embedded therein.

Abstract: A photosensitive material is coated on an insulating material (13) stacked on a substrate (1) (FIG. 16A), and exposed and developed using a mask having a light-shielding film capable of controlling a light transmittance from 100% to 0% annularly and continuously to form a spiral photosensitive material (FIG. 16B). After conducting treatment at a high temperature, the insulating material under the photosensitive material is spirally formed by etching (FIG. 16C). A metal (12) is stacked on the substrate (FIG. 16D), and a photosensitive material is coated (FIG. 16E). The photosensitive material is exposed and developed using a mask having an annular light-shielding film with a light transmittance of 0% to leave the photosensitive material covering only the metal on the base of the spiral structure (FIG. 16F). After treatment at a high temperature is conducted and the metal exposed is etched (FIG. 16G), the photosensitive material is removed (FIG. 16H).

Abstract: Compositions and methods for the removal of patterned photodefinable materials, such as photoresists and/or photoimageable dielectric materials, from substrates are provided. Such compositions and methods are useful in the manufacture of electronic devices. Methods of reworking electronic device substrates by removing patterned photodefinable material from an underlying organic film are also provided.

Abstract: The present invention provides a resist pattern thickening material and the like which can thicken a resist pattern and form a fine space pattern, exceeding exposure limits of exposure light used during patterning. The resist pattern thickening material contains a resin and a surfactant. In a process for forming a resist pattern of the present invention, after a resist pattern to be thickened is formed, the resist pattern thickening material is coated on a surface thereof. A process for manufacturing a semiconductor device of the present invention includes: a step of, after forming a resist pattern to be thickened on an underlying layer, coating the thickening material on a surface of the resist pattern to be thickened so as to thicken the resist pattern to be thickened and form a resist pattern; and a step of patterning the underlying layer by etching by using the resist pattern.

Abstract: A method of manufacturing an integrated circuit includes a semiconductor substrate having bitlines under a charge-trapping material over a core region and a gate insulator material over a periphery region. A wordline-gate material, a hard mask, and a first photoresist are deposited and patterned over the core region while covering the periphery region. After removing the first photoresist, wordlines are formed from the wordline-gate material in the core region. An anti-reflective coating and a second photoresist are deposited and patterned over the periphery region and covering the core region. The anti-reflective coating is removable without damaging the charge-trapping material. After removing the second photoresist and the anti-reflective coating, gates are formed from the wordline-gate material in the periphery region and the integrated circuit completed.

Abstract: A method for semiconductor device feature development using a bi-layer photoresist including providing a non-silicon containing photoresist layer over a substrate; providing a silicon containing photoresist layer over the non-silicon containing photoresist layer; exposing an exposure surface of the silicon containing photoresist layer to an activating light source said exposure surface defined by an overlying pattern according to a photolithographic process; developing the silicon containing photoresist layer according to a photolithographic process to reveal a portion the non-silicon containing photoresist layer; and, dry developing said non-silicon containing photoresist layer in a plasma reactor by igniting a plasma from an ambient mixture including at least hydrogen and carbon monoxide.

Abstract: Polymerizable silicon-containing compounds of formula (1) wherein R1 is hydrogen, halogen or monovalent organic group are polymerized into polymers. A resist composition comprising the polymer as a base resin is sensitive to high-energy radiation, has excellent sensitivity and resolution at a wavelength of less than 300 nm, and high resistance to oxygen plasma etching, and thus lends itself to micropatterning for the fabrication of VLSIs.

Abstract: A process is described for trimming photoresist patterns during the fabrication of integrated circuits for semiconductor devices and MEMS devices. A combination of a low temperature (<20° C.), high density oxygen and argon plasma and intense UV radiation is used to simultaneously trim and harden a photoresist linewidth in an ICP chamber. As an alternative, a UV hardening step can be performed in a flood exposure tool prior to the ICP plasma etch. Another option is to perform the argon plasma treatment first to harden the resist and then in a second step apply an oxygen plasma to trim the photoresist. Vertical and horizontal etch rates are decreased in a controllable manner which is useful for producing gate lengths in MOS transistors of less than 100 nm. The process can also be used to controllably increase a space width in a photoresist feature.

Abstract: A layer for use in a modular assemblage for supporting ICs is formed with metal contacts for assembly by making a sandwich of metal interconnect members between two layers of dielectric; drilling holes through the dielectric, stopping on a metal layer bonded to the bottom surface of the module; forming blind holes stopping on the interconnect members; and plating metal through the volume of the via, both full and blind holes, thereby forming vertical and horizontal connections in a layer that be stacked to form complex interconnect assemblies.

Abstract: A wafer (18) is made using a mask (14) that has a quartz substrate (15) and a patterned stack (32) for providing a mask pattern. The patterned stack comprises an opaque layer (36) between two ARC layers (34, 38). The patterned stack reduces flare, which in turn improves critical dimension (CD) control. The stack reduces the reflections that come from the interface between the opaque layer (36) and quartz substrate (15). This stack also absorbs the reflections that come back from the direction of the wafer. The opaque layer (36) is silicon, which is opaque at wavelengths below 300 nanometers, and the ARC layers are non-stoichiometric silicon nitride.

Abstract: A method of determining overlay layers utilizing advanced lithographic materials utilizes a post-etch overlay metrology. After etching, a relatively opaque layer is removed so that registration markers such as trench isolation structures can be observed. Lithographic parameters associated with the process can be adjusted in accordance with the observations. In a preferred embodiment, an overlay error is determined and adjustments are made to the reduce the overlay error.

Abstract: Resist residues, which is formed in a process of forming Al interconnections, are removed through use of a single chemical. A chemical which contains an organic acid or a salt thereof and water and which has a pH below 8 is used as a treatment for removing resist or resist residues. The chemical may be used in a process in which Al, W, Ti, TiN, and SiO2 are exposed on the surface of a wafer after etching of an Al interconnection; in a process in which Al, W, Ti, TiN, and SiO2 are exposed on the surface of a wafer after etching a hole reaching an Al interconnection in an dielectric layer; in a process in which Cu is exposed on the surface of a semiconductor wafer after dry-etching of a Cu interconnection or etching of an interlayer dielectric film laid on a Cu interconnection; and in a process in which metal material such as W, WN, Ti, or TiN; poly-Si; SiN; and SiO2 are exposed on the surface of a wafer after etching of a metal gate.

Abstract: Supports (3) are formed to be arrayed on a support base (1), a sacrifice layer (15) is formed of a resin material, and the sacrifice layer (15) is planarized so as to expose the top of the respective supports (3), thereby forming a thin-film substrate (5) on top of the sacrifice layer (15) as planarized, and the supports (3). The sacrifice layer (15) is removed by plasma selective etching thereof through the intermediary of the thin-film substrate, and thereby a large-area thin-film substrate (5) floatingly spaced by a space (7) away from the support base (1) can be fabricated.

Abstract: Techniques are disclosed for fabricating a device using a photolithographic process. The method includes providing a first anti-reflective coating over a surface of a substrate. A layer which is transparent to a wavelength of light used during the photolithographic process is provided over the first anti-reflective coating, and a photosensitive material is provided above the transparent layer. The photosensitive material is exposed to a source of radiation including the wavelength of light. Preferably, the first anti-reflective coating extends beneath substantially the entire transparent layer. The complex refractive index of the first anti-reflective coating can be selected to maximize the absorption at the first anti-reflective coating to reduce notching of the photosensitive material.

Abstract: Disclosed is a method for manufacturing a semiconductor device by employing a dual damascene process. After a first insulation film including a conductive pattern is formed on a substrate, at least one etch stop film and at least one insulation film are alternatively formed on the first insulation film. A via hole for a contact or a trench for a metal wiring is formed through the insulation film, and then the via hole or the trench is filled with a filling film including a water-soluble polymer. After a photoresist film is coated on the filling film, the photoresist film is patterned to form a photoresist pattern and to remove the filling film. The DOF and processing margin of the photolithography process for forming the photoresist pattern can be improved because the photoresist film can have greatly reduced thickness due to the filling film.

Abstract: In an embodiment, a trench is formed above a via from a photo resist (PR) trench pattern in a dielectric layer. The trench is defined by two sidewall portions and base portions. The base portions of the sidewalls are locally treated by a post treatment using the PR trench pattern as mask to enhance mechanical strength of portions of the dielectric layer underneath the base portions. Seed and barrier layers are deposited on the trench and the via. The trench and via are filled with a metal layer. In another embodiment, a trench is formed from a PR trench pattern in a dielectric layer. A pillar PR is deposited and etched to define a pillar opening having a pillar surface. The pillar opening is locally treated on the pillar surface by a post treatment to enhance mechanical strength of portion of the dielectric layer underneath the pillar surface.

Abstract: In a method for forming a photoresist pattern, a method for forming a capacitor, and a capacitor manufactured using the same, a light is selectively irradiated onto a selected portion of a photoresist film formed on a substrate. An interfered light generated from the irradiated light is transmitted through other portions of the photoresist film except a ring-shaped portion of the photoresist film having a predetermined width along a boundary of the selected portion. The photoresist film is exposed using the interfered light and the light irradiated onto the selected portion. A cylindrical photoresist pattern having a minute width may be formed through developing the photoresist film. With the cylindrical pattern, the capacitor can be easily formed.

Abstract: A method of manufacturing a semiconductor device is provided. In one example, the method includes fabricating holes and/or trenches in organosiloxane insulating film without damaging the film by ashing and without causing a problem of shape deterioration or obstacles. The method comprising forming a second insulating film and a inorganic thin film soluble to a dissolving solution on an organosiloxane insulating film, fabricating the organosiloxane insulating film using the inorganic thin film as a hard mask, and removing the hard mask after fabrication by a dissolving solution.

Abstract: Metal bumps for connecting a nonconducting substrate and a chip without lateral shorting are provided. In a first preferred embodiment, an insulating layer covers the entire sidewalls of all the metal bumps. In a second preferred embodiment, predetermined portions of a first metal bump and a second metal bump are covered with an insulating layer. For example, a first predetermined portion of the sidewall of the first metal bump may be zcovered with an insulating layer, while a second predetermined portion of the sidewall of the second sidewall is also covered with an insulating layer.

Abstract: A technique for etching with a single layered patterned photomask at wavelengths of 193 nanometers or less. Specifically, a method for etching a bottom anti-reflectant coating layer that utilizes a combination of CF4, CH2F2, and O2 to produce a stabilized pattern in the photoresist layer. The etching process results in a structure with a defined pattern having minimal defects and that maintains integrity through the remainder of the etching.

Abstract: A positive type, photosensitive epoxy resin composition comprising (a) an epoxy resin having two or more epoxy groups in one molecule, (b) a modified phenolic resin having a triazine ring, (c) a latent basic curing agent and (d) a photosensitive acid generator; and a preferably multilayered printed circuit board of buildup mode using said composition as an insulating layer.

Abstract: One example of a separation-material composition for a photo-resist according to the present invention comprises 5.0 weight % of sulfamic acid, 34.7 weight % of H2O, 0.3 weight % of ammonium 1-hydrogen difluoride, 30 weight % of N,N-dimethylacetamide and 30 weight % of diethylene glycol mono-n-buthyl ether. Another example of a separation-material composition for a photo-resist according to the present invention comprises 1-hydroxyethylidene-1, 3.0 weight % of 1-diphosphonic acid, 0.12 weight % of anmonium fluoride, 48.38 weight % of H2O and 48.5 weight % of diethylene glycol mono-n-buthl ether.

Abstract: A dual damascene process is provided on a semiconductor substrate, having a conductive structure and a low-k dielectric layer covering the conductive structure. A first hard mask and a second hard mask are sequentially formed on the low-k dielectric layer, in which at least the hard mask contacting the low-k dielectric layer is of metallic material. Next, a first opening is formed in the second hard mask over the conductive structure, and a second opening is then formed in the first hard mask under the first opening. Afterward, the low-k dielectric layer that is not covered by the first hard mask is removed, thus a via hole is formed. Thereafter, the first hard mask that is not covered by the second hard mask is removed, and then the exposed low-k dielectric layer is removed. Thereby, a trench is formed over the via hole.

Abstract: An organic anti-reflective coating (ARC) is formed over a surface of a semiconductor substrate, and a resist layer including a photosensitive polymer is formed on the ARC. The photoresistive polymer contains a hydroxy group. The resist layer is then subjected to exposure and development to form a resist pattern. The resist pattern to then silylated to a given depth by exposing a surface of the resist pattern to a vapor phase organic silane mixture of a first organic silane compound having a functional group capable of reacting with the hydroxy group of the photoresistive polymer, and a second organic silane compound having two functional groups capable of reacting with the hydroxy group of the photoresistive polymer Then, the silylated resist pattern is thermally treated, and the organic ARC is anisotropically etched using the thermally treated resist pattern as an etching mask.

Abstract: A method and corresponding article of manufacture are provided for manufacturing a semiconductor device with contact holes of the same step formed by two photolithography processes, where the manufacture includes forming a photoresist pattern by a first photolithography process on an insulating interlayer in which a first contact hole is formed, the photoresist pattern covering the first contact hole, etching the insulating interlayer to form a second contact hole by using the photoresist pattern as an etching mask, partially removing the photoresist pattern to remove an etch by-product from the second contact hole, and performing a process on the second contact hole by using the photoresist pattern residue as a mask to thereby decrease the number of photo processes and simplify the manufacturing process.

Abstract: Method of forming a magnetic memory device are disclosed. In one embodiment, a first plurality of conductive lines are formed over a semiconductor workpiece. A plurality of magnetic material lines are formed over corresponding ones of the first plurality of conductive lines and a second plurality of conductive lines are formed over the semiconductor workpiece. The second plurality of conductive lines cross over the first conductive lines and the magnetic material lines. These second lines can be used as a mask to while the magnetic material lines are patterned.

Abstract: The present invention is directed towards contact planarization methods that can be used to planarize substrate surfaces having a wide range of topographic feature densities for lithography applications. These processes use thermally curable, photo-curable, or thermoplastic materials to provide globally planarized surfaces over topographic substrate surfaces for lithography applications. Additional coating(s) with global planarity and uniform thickness can be obtained on the planarized surfaces. These inventive methods can be utilized with single-layer, bilayer, or multi-layer processing involving bottom anti-reflective coatings, photoresists, hardmasks, and other organic and inorganic polymers in an appropriate coating sequence as required by the particular application. More specifically, this invention produces globally planar surfaces for use in dual damascene and bilayer processes with greatly improved photolithography process latitude.

Abstract: A stripping composition comprising (a) an anticorrosive agent, (b) a stripping agent and (c) a solvent, wherein the anticorrosive agent (a) is a heterocyclic compound having a nitrogen atom-containing six-membered ring.

Abstract: The invention relates to electrodes for organic components, particularly for components such as field effect transistors (OFET's) and/or light-emitting diodes (OLED's), which have conductive and highly resolved finely structured electrode tracks. The electrode and/or conductor track are/is produced by treating a conductive or non-conductive layer comprised of an organic functional polymer with a chemical compound since, at the point of contact, the chemical compound deactivates or activates the layer comprised of an organic functional polymer, i.e. renders it conductive or non-conductive. The non-conductive regions of the layer can be removed.

Abstract: A photosensitive polymer composition, having (a) a polymer selected from polyimide precursors and polyimides having an acid group protected by a protecting group and having no amino group (—NH2) at the end; and (b) a compound that generates an acid when exposed to light and capable of deprotecting the protecting group from the acid group, is employed to form layers of a semiconductor device.

Abstract: Provided is a method of forming a fine pattern, in which a silicon oxide layer is formed on a photoresist pattern and dry etching is performed on the resultant structure. According to the method, a photoresist pattern is formed on a material layer on which a fine pattern is to be formed, a silicon oxide layer is conformally deposited on the photoresist pattern without damaging the photoresist pattern, and dry etching is performed on a lower layer. During the dry etching, spacers are formed along the sidewalls of the photoresist pattern, and then, a polymer layer is formed on the photoresist pattern. Accordingly, it is possible to prevent the thinning of the photoresist pattern so that a desired pattern can be obtained, and further, to prevent striation or wiggling from occurring on the patterned material layer.

Abstract: A method for fabricating patterned layers of a desired material in a desired, design pattern upon a substrate, which method may be used in circumstances where the removal of photo-resist material may not be used to lift-off undesired portions of the material from the substrate. The method uses copper or some other conducting material instead of the photo-resist material, Which copper or other conducting material may be removed by chemical processes to lift-off the undesired portions of material deposited upon the conducting material and substrate. The copper or other conducting material is fabricated upon the substrate so as to have a lip that overhangs and shadows the boundary of photo-resist material previously fabricated upon the substrate in the desired pattern.

Abstract: The present invention provides a method of manufacturing a member pattern having a patterned member on a substrate, the method including: a first exposure step of exposing a desired region of a negative type photosensitive material applied to the substrate to light from a first direction; a second exposure step of exposing the desired region of the negative type photosensitive material to light from a second direction opposite to the first direction; a development step of performing development after the exposure steps to form a precursor pattern of the member; and a step of baking the precursor pattern.

Abstract: A droplet/electrospray device and a liquid chromatography-electrospray system are disclosed. The droplet/electrospray device comprises a substrate defining a channel between an entrance orifice on an injection surface and an exit orifice on an ejection surface, a nozzle defined by a portion recessed from the ejection surface surrounding the exit orifice, and an electrode for application of an electric potential to the substrate to optimize and generate droplets or an electrospray. A plurality of these electrospray devices can be used in the form of an array of miniaturized nozzles. The liquid chromatography-electrospray device comprises a separation substrate defining an introduction channel between an entrance orifice and a reservoir and a separation channel between the reservoir and an exit orifice, the separation channel being populated with separation posts perpendicular to the fluid flow.

Abstract: A device, method, and system for treating low-k dielectric material films to reduce damage during microelectronic component cleaning processes is disclosed. The current invention cleans porous low-k dielectric material films in a highly selectivity with minimal dielectric material damage by first treating microelectronic components to a passivating process followed by a cleaning solution process.

Abstract: A method for transferring patterns. After a patterned photoresist is formed on a substrate, the patterned photoresist is hardened, and the pattern of the hardened patterned photoresist is transferred into the substrate. Moreover, a popular method to harden is the silylation process, it is acceptable to only harder the top of the patterned photoresist or to harden both the top and the sidewall of the patterned photoresist. Besides, it is optional to change the thickness and the critical dimension of the patterned photoresist before it is hardened. Significantly, because the etch resistance of hardened patterned photoresist is higher than that of the non-hardened patterned photoresist, the method can improve any defect induced by etched photoresist during the pattern transferring process. Similarly, because a thinner non-hardened photoresist is available for the method, a smaller critical dimension of the patterned photoresist is available for the method while the photolithography technology being not improved.

Abstract: A method for creating a phase shift photomask which includes a layer of hard mask material, the inclusion of which improves the uniformity of critical dimensions on the photomask by minimizing the affect of macro and micro loading. The method for producing the phase shift photomask of the instant invention includes two etching processes. The first etching process etches the layer of hard mask, and the second etching process etches opaque material (and anti-reflective layer, if used) and phase shift layers.

Abstract: Within a method for fabricating a microelectronic fabrication there is employed a patterned positive photoresist residue layer as a protective layer within an aperture when processing an upper region of a topographic microelectronic layer having formed therein the aperture. The patterned positive photoresist residue layer is formed employing an incomplete vertical, but complete horizontal, blanket photoexposure and development of a blanket positive photoresist layer formed upon the topographic microelectronic layer and filling the aperture. The method provides the microelectronic fabrication with enhanced reliability.

Abstract: A method of forming an opening in a wafer layer is described. At least two patterned photoresist layers are formed on a wafer layer. Each photoresist layer comprises patterns of various configurations. The photoresist layers are stacked to form an opening pattern that expose the underlying wafer layer by superpositioning the space between the patterns in the first photoresist layer and the space between the patterns in the second photoresist layer. The wafer layer exposed by the opening pattern is then etched to form an opening.