Abstract: A method for forming via openings or contact holes with improved aspect ratios by using a deep UV photoresist is described. In the method, after a deep UV photoresist layer is deposited on top of a thick oxide layer, the deep UV photoresist layer is pre-treated by a curing process with UV radiation for a time period of at least 1 min, and preferably between about 1 min and about 10 min at a temperature of at least 100° C., and preferably at least 160° C. The curing process stabilizes the structure of the deep UV photoresist material and thus reduces the formation of fluorocarbon polymers by the carbon component in the photoresist material and the fluorine component in the etchant gas, and subsequently, reduces the coating of such fluorocarbon polymers at the bottom of the via openings which would otherwise stop the etching process during via or contact formation.

Abstract: The present invention relates to a method for fabricating a semiconductor device capable of improving an overlap margin that occurs when forming a conductive pattern, such as a bit line or a bit line contact. In order to achieve this effect, the method for fabricating a semiconductor device includes the steps of: forming a plug passing through an insulation layer to be contacted with a substrate board; forming a planarization insulation layer on an entire surface including the plug so as to cover defects appeared at a surface of the plug; forming a protective insulation layer on the planarization insulation layer for preventing losses of the planarization insulation layer resulted from a subsequent cleaning process; performing a process with an etchant; and forming a conductive layer contacted to the plug by passing through the protective insulation layer and the planarization insulation layer.

Abstract: There is described a method of forming a fine pattern aimed at depositing a silicon-nitride-based anti-reflection film which is stable even at high temperature and involves small internal stress. The method is also intended to preventing occurrence of a footing pattern (a rounded corner) in a boundary surface between a photoresist and a substrate at the time of formation of a chemically-amplified positive resist pattern on the anti-reflection film. The method includes the steps of forming a silicon-nitride-based film directly on a substrate or on a substrate by way of another layer; and forming a photoresist directly on the silicon-nitride-based film or on the silicon-nitride-based film by way of another layer. The silicon-nitride-based film is deposited while the temperature at which the substrate is to be situated is set so as to fall within the range of 400 to 700° C., through use of a plasma CVD system.

Abstract: A method of using resist planarization to prepare for silicidation while protecting silicon nitride spacers in the fabrication of integrated circuits is described. Field oxide areas are formed on a semiconductor substrate surrounding and electrically isolating a logic device area and a memory device area. Polysilicon gate electrodes having silicon nitride sidewall spacers and associated source/drain regions are formed in the device areas. A silicon oxide layer is deposited overlying the gate electrodes and source/drain regions. The silicon oxide layer is covered with a photoresist layer. The photoresist layer is developed until the silicon oxide layer overlying the gate electrodes is exposed and the photoresist layer is below the tops of the gate electrodes. The exposed silicon oxide layer is etched away whereby the tops of the gate electrodes are exposed and wherein the silicon nitride spacers are undamaged by the etching. All of the silicon oxide layer in the logic device area is etched away.

Abstract: A process for reducing roughness from a surface of a patterned photoresist. The process includes exposing a substrate having the patterned photoresist thereon to a vapor, wherein the vapor penetrates into and/or reacts with the surface of the photoresist. The substrate having the patterned photoresist thereon is then heated to a temperature and for a time sufficient to cause the surface of the photoresist to flow and/or react with the vapor wherein the surface roughness decreases. Optionally, the substrate is exposed to radiation during the process to increase the etch resistance of the photoresist and/or facilitate the reaction of the vapor with the surface of the photoresist.

Abstract: A two layer structure resist pattern with a T-shaped cross section, consisting of a lower layer and an upper layer with overhang portions is formed, and then the formed two layer structure resist pattern is heat-treated so that the overhang portions of the upper layer incline downward.

Abstract: A method comprising introducing a photoimageable material on a substrate; developing the photoimageable material over an opening area, the photoimageable material over a first portion of the opening area developed to a first extent and the photoimageable material over a second portion of the opening area developed to a different second extent; removing developed photoimageable material from the opening area; and forming an opening in the substrate in the opening area.

Abstract: A blank printed circuit board (10), for creating a circuit pattern thereon by direct imaging with infrared radiation. The blank printed circuit board (10) includes in sequence an insulating substrate (20), a metal layer (21), a resist layer (22) and a mask layer (23).

Abstract: A carbon-doped hard mask includes a dielectric material containing carbon which is released from the hard mask during a metal etching process. The released carbon is deposited on and bonds to sidewalls of the metal structure during the metal etching process to passivate the sidewalls of the metal structure and prevent lateral etching of the sidewalls during the metal etching process. The released carbon also prevents accumulation of metal residue in open fields.

Abstract: A photoresist or a residue of the photoresist may by removed by the hydrogen and water plasma mixture. The process may be performed at a temperature range between about 150° C. and about 450° C., preferably about 250° C., and a power range between about 500 W and about 3000 W, preferably about 1400 W.

Abstract: A method of forming an integrated circuit using an amorphous carbon film. The amorphous carbon film is formed by thermally decomposing a gas mixture comprising a hydrocarbon compound and an inert gas. The amorphous carbon film is compatible with integrated circuit fabrication processes. In one integrated circuit fabrication process, the amorphous carbon film is used as a hardmask. In another integrated circuit fabrication process, the amorphous carbon film is an anti-reflective coating (ARC) for deep ultraviolet (DUV) lithography. In yet another integrated circuit fabrication process, a multi-layer amorphous carbon anti-reflective coating is used for DUV lithography.

Abstract: The present invention relates to a method of manufacturing a semiconductor device; which comprises the steps of forming a film of a hard mask material, on a pattern-forming film which is to be used to form a prescribed pattern, and then forming a photoresist film over said film of the hard mask material; carrying out a first exposure using a first mask with a phase shifter and subsequently making a development; etching said film of the hard mask material using the formed resist pattern as a mask; forming a photoresist film so as to cover the formed hard mask pattern; carrying out a second exposure using a second mask with a pattern which enables a portion of the photoresist covering only a required part of said hard mask pattern to remain after the exposure and the development, and subsequently making a development; removing, by means of etching, an unrequited part of the hard mask which is not covered with any portion of said photoresist; and etching said pattern-forming film using the remaining hard mask pa

Abstract: A photomask including chromium patterns divided into two groups in such a fashion that the chromium patterns in one of the two chromium pattern groups alternate, one by one, with the chromium patterns in the other chromium pattern group, the chromium patterns being formed on two quartz substrate for the two chromium pattern groups, respectively, to prepare for the photomask, two separate photomasks each having an increased space defined between adjacent chromium patterns thereof so as to avoid a severe diffraction of light passing between the adjacent chromium patterns. A method for forming micro patterns of a semiconductor device using the photomask is also disclosed.

Abstract: A method of masking and etching a semiconductor substrate includes forming a layer to be etched over a semiconductor substrate. An imaging layer is formed over the layer to be etched. Selected regions of the imaging layer are removed to leave a pattern of openings extending only partially into the imaging layer. After the removing, the layer to be etched is etched using the imaging layer as an etch mask. In one implementation, an ion implant lithography method of processing a semiconductor includes forming a layer to be etched over a semiconductor substrate. An imaging layer of a selected thickness is formed over the layer to be etched. Selected regions of the imaging layer are ion implanted to change solvent solubility of implanted regions versus non-implanted regions of the imaging layer, with the selected regions not extending entirely through the imaging layer thickness.

Abstract: A method of creating an undercut sidewall profile within an opening formed in a positive resist layer disposed upon a transparent substrate includes the step of forming a positive resist layer on the upper surface of the substrate, and optically patterning the resist layer by selectively directing light at the resist layer from above the upper surface of the substrate. The lower surface of the substrate is flooded with light to partially expose the lowermost region of the resist layer, and the exposed resist is dissolved to form patterned openings therein. The resulting sidewalls of the patterned resist openings have an enlarged width adjacent the upper surface of the substrate. The sidewalls of the resist layer are then flooded with light from above the substrate, the upper region of the resist layer is cured by an electron beam, and the resist layer is developed a second time to dissolve exposed portions of the resist sidewalls, thereby forming an undercut resist sidewall profile.

Abstract: A method of forming an integrated circuit using an amorphous carbon film. The amorphous carbon film is formed by thermally decomposing a gas mixture comprising a hydrocarbon compound and an inert gas. The amorphous carbon film is compatible with integrated circuit fabrication processes. In one integrated circuit fabrication process, the amorphous carbon film is used as a hardmask. In another integrated circuit fabrication process, the amorphous carbon film is an anti-reflective coating (ARC) for deep ultraviolet (DUV) lithography. In yet another integrated circuit fabrication process, a multi-layer amorphous carbon anti-reflective coating is used for DUV lithography.

Abstract: A method of patterning electrically conductive polymers is: forming a surface of a conducting polymer on a substrate, applying a mask to this surface, applying irradiation to form regions of exposed conducting polymer and regions of unexposed conducting polymer, removing the mask, and gently removing by non-chemically reactive means the regions of exposed conducting polymer.

Abstract: Methods are provided for making stencil masks from a mask substrate preferably having sequential layers of a backside hardmask, a mask substrate, a stencil pattern forming layer and preferably a frontside hardmask layer. In one method a backside protective layer is formed after a backside etch and substrate window etch to protect the stencil pattern forming layer during the stencil pattern forming layer etching process. In another method of the invention, a frontside protective layer is provided over the etched stencil pattern forming layer surface before the substrate layer etch to form a mask window. In both methods enhanced control of critical dimensions of the mask and profile control are achieved since are backside cooling of the substrate during making of the mask can be used during the mask fabrication process.

Abstract: Partial photoresist etching is disclosed. A film on a semiconductor wafer includes a hard mask, doped polysilicon below the hard mask, undoped polysilicon below the doped polysilicon, and a stop layer below the undoped polysilicon. Photoresist etching is performed through the hard mask and the doped polysilicon by using a photoresist mask. After the photoresist mask is removed, photoresist-free etching is performed through the undoped polysilicon through to the stop layer by using the hard mask. A semiconductor device is disclosed that may be fabricated using this partial photoresist etching process.

Abstract: A method of forming a patterned photoresist with a non-distorted profile. A first photoresist is formed on a substrate. The first photoresist is suitable for patterning a trench pattern. A second photoresist is formed on the first photoresist. The second photoresist is suitable for patterning an iso-line pattern. A photolithography step is then performed to pattern the second and the first photoresist to form a patterned photoresist.

Abstract: Copolymers prepared by radical polymerization of a substituted norbornene monomer and a fluoromethacrylic acid, fluoromethacrylonitrile, or fluoromethacrylate comonomer are provided. The polymers are useful in lithographic phtoresist compositions, particularly chemical amplification resists. In a preferred embodiment, the polymers are substantially transparent to deep ultraviolet (DUV) radiation, i.e., radiation of a wavelength less than 250 nm, including 157 nm, 193 nm and 248 nm radiation, and are thus useful in DUV lithographic photoresist compositions. A process for using the composition to generate resist images on a substrate is also provided, i.e., in the manufacture of integrated circuits or the like.

Abstract: A first film is formed on a semiconductor substrate, the first film being made of material having a different etching resistance from silicon carbide. A second film of hydrogenated silicon carbide is formed on the first film. A resist film with an opening is formed on the second film. By using the resist mask as an etching mask, the second film is dry-etched by using mixture gas of fluorocarbon gas added with at least one of SF6 and NF3. The first film is etched by using the second film as a mask. A semiconductor device manufacture method is provided which utilizes a process capable of easily removing an etching stopper film or hard mask made of SiC.

Abstract: Disclosed is a method of forming a pattern comprising coating a solution containing a compound having a silicon-nitrogen linkage in the main chain thereof over a surface of a working film to form a mask, replacing the nitrogen in the mask by oxygen, forming a resist film on a surface of the mask, forming a resist pattern by subjecting the resist film to a patterning exposure and to a developing treatment, transcribing the resist pattern to the mask to form a masking pattern, and transcribing the masking pattern to the working film to form a working film pattern.

Abstract: A method of forming a silicon carbide layer for use in integrated circuits is provided. The silicon carbide layer is formed by reacting a gas mixture comprising a silicon source, a carbon source, and a nitrogen source in the presence of an electric field. The as-deposited silicon carbide layer incorporates nitrogen therein from the nitrogen source.

Abstract: Disclosed is an etching method of a laminated assembly having a metal layer and a non-thermoplastic polyimide layer bonded together via thermoplastic polyimide, which comprises using an etchant at least containing an alkali metal hydroxide, water and oxyalkylamine, wherein the concentrations of the alkali metal hydroxide (X weight %) and of the water (Y weight %) have relationships represented by coordinate points present within a region (inclusive of boundary lines) defined by the following expressions [1] and [2]:

Abstract: A phase-shifting lithographic mask, a method for its fabrication, and a method for its use in forming field-emission display emitters is described. The mask is made from a plate and has field and pattern regions that both transmit light of a given wavelength. The pattern region is a plurality of regularly spaced etched regions of the plate, with the optical path length of the pattern region differing from the optical path length of the field region by an odd integer multiple of one-half the light wavelength. Use of phase-shifting lithography improves depth-of-focus, and correspondingly relaxes planarity requirements. The pattern region of the mask is sized to expose a photoresist layer used in fabricating field-emission display emitters in just a single light exposure, thereby avoiding the disadvantages associated with conventional dual pass phase-shifting lithography.

Abstract: photosensitive resin composition of the present invention is prepared by adding inorganic particles having a functional group and a mean particle size smaller than the wavelength of light for exposure (e.g., about 1 to 100 nm) to a photosensitive resin. The inorganic particles can be of colloidal silica having a functional group. The photosensitive resin composition may be of positive or negative type, and developable with water or an alkali. The amount of the inorganic particles to be used is, relative to 100 parts by weight of the photosensitive resin, about 10 to 500 parts by weight on a solid matter basis. The use of such photosensitive resin composition makes it possible to largely improve oxygen plasma resistance, heat resistance, dry etching resistance, sensitivity, and resolution utilizing a conventional resist or lithography technique.

Abstract: A method for fabricating a mask for patterning a radiation sensitive layer in a lithographic printer is disclosed. An attenuating (absorptive or reflective) layer is coated over a substantially transparent base substrate such that after processing a two-dimensional spatially varying attenuating pattern is created with a continuously or discretely varying transmission or reflection function. In accordance with the present invention the two-dimensional attenuating pattern is formed by e-beam patterning of radiation sensitive layer to create a three-dimensional surface relief pattern. This pattern is transferred to the attenuating layer by an anisotropic etch, typically a directional reactive plasma etch. The attenuation of this radiation absorbing or reflecting layer varies with layer thickness. In one embodiment of this invention the attenuation of the mask would vary spatially in a continuous manner.

Abstract: A method to planarize a semiconductor surface using a Fence Creation and Elimination (FCE) process is described. Shallow recesses on a semiconductor surface are filled with a filling material. The filling material is deposited on the semiconductor surface to a thickness approximately equal to the depth of the shallow recesses. A selectively etchable material is formed on the filling material. A reverse mask (RM) is used to pattern the selectively etchable material to form segments of the selectively etchable material equal to the pattern of the shallow recesses and aligned to the shallow recesses. Exposed filling material is removed followed by the removal of the segments of the selectively etchable material. The remaining filling material in the shallow recesses forms fences which extend above the surface of the semiconductor. The fences are removed resulting in a planar semiconductor surface.

Abstract: A method of forming a TFT-LCD device with a rough pixel electrode is disclosed. The method comprises the following steps. First, a first passivation layer is formed on the transparent insulator substrate to cover the transistor. The first passivation layer is etched to form contact holes therein to expose a source structure and a drain structure of the transistor. A pixel electrode is formed on the first passivation layer and filled into the contact holes to connect electrically to the drain structure. A second passivation layer is formed on the first passivation layer and the pixel electrode to cover uniformly the transistor for planarization. Then a lithography procedure is done to etch the second passivation layer to make surfaces thereof rough.

Abstract: A dual damascene process is provided on a semiconductor substrate, having a conductive structure and a low-k dielectric layer covering the conductive structure. A first hard mask and a second hard mask are sequentially formed on the low-k dielectric layer, in which at least the hard mask contacting the low-k dielectric layer is of metallic material. Next, using photolithography and etching, a first opening is formed in the second hard mask over the conductive structure, and a second opening is then formed in the first hard mask under the first opening. The diameter of the first opening is larger then the second opening. Afterward, the low-k dielectric layer that is not covered by the first hard mask is removed, thus a via hole is formed. Thereafter, the first hard mask that is not covered by the second hard mask is removed, and then the exposed low-k dielectric layer is removed to reach a predetermined depth. Thereby, a trench is formed over the via hole.

Abstract: A method for producing structures in chips is realized by carrying out a sequence of structuring steps in a self-adjusting manner. By structuring a first auxiliary layer applied on a substrate, a first masking structure is formed after a first masking procedure, which first masking structure has at least one partial region projecting beyond the surface of the substrate. After this, a further structuring step is carried out, for instance, by etching, implantation or CVD, using the previously produced first masking structure as a mask. After this, the first masking structure with a view to forming a second masking structure is inverted by applying at least one second auxiliary layer onto the first masking structure. The thus formed structure is at least partially taken off and the thus denuded first auxiliary layer is selectively removed, whereupon the second masking structure is used as a mask for a further structuring step.

Abstract: The present invention provides a substrate-engraving-type chromeless phase-shift mask enabling to adopt a manufacturing method which poses no problem in quality, gives a high operating efficiency, and permits arrangement of characters and symbols, and a manufacturing method thereof. The substrate of the invention has a character/symbol section, on a surface of a transparent substrate, comprising characters and/or symbols engraved in the form of a slit-shaped or lattice-shaped pattern comprising concave grooves only in a prescribed portion corresponding to the characters and/or symbols.

Abstract: A sulfonium salt compound designated by a general formula (I), a photoresist composition containing the sulfonium salt compound and a method for patterning by employing the sulfonium salt compound.

Abstract: Novel photoresists containing at least about 0.2 molar ratio of a base with respect to the concentration of a photoacid generator present and their preparation are described. It has been discovered that inclusion of a sufficient amount of base counteracts the detrimental effects of photoacid generators, thus providing resists having submicron linewidth resolution.

Abstract: The magnetic tape recording head of the present invention is formed with magnetic poles that are comprised of a laminated NiFeN/FeN structure. The method for fabricating the magnetic poles utilizes an additive photolithographic technique including a bilayer liftoff resist. In this fabrication method magnetic pole trenches are formed in the bilayer liftoff resist such that an undercut exists in the liftoff layer. Thereafter, the laminated NiFeN/FeN structure is sputter deposited into the trench, followed by the wet chemical removal of the bilayer resist.

Abstract: The present invention provides a multiple exposure method for defining a rectangular pattern on a photoresist layer. The method comprises the following steps. First, a rectangular region is defined on the photoresist layer, having a first margin pair and a second margin pair corresponding to the rectangular pattern. Next, a first exposure process is performed on a first exposure region of the photoresist layer. An extension of the first margin pair acts as a boundary between the first exposure region and the rectangular region. Next, a second exposure process is performed on a second exposure region of the photoresist layer. An extension of the second margin pair acts as a boundary between the second exposure region and the rectangular region. Finally, a development process is performed on the first exposure region and the second exposure region to create the rectangular pattern on a substrate.

Abstract: A negative photoresist for transferring a photomask to a semiconductor wafer includes a passivated component that is activated by an exposure radiation, the activated component being configured to interact with the uppermost layer of the semiconductor wafer at the interface, the interaction ensuring increased adhesion between the negative photoresist and the substrate. Alternatively, a positive photoresist for transferring a photomask to a semiconductor wafer includes a component that is passivated by an exposure radiation, the activated component being configured to interact with the uppermost layer of the semiconductor wafer at the interface, the interaction ensuring increased adhesion between the positive photoresist and the substrate.

Abstract: A system and method for forming a plurality of structures in a low dielectric constant layer is disclosed. The low dielectric constant layer is disposed on a semiconductor. The method and system include exposing the low dielectric constant layer to an agent that improves adhesion of a photoresist, providing a layer of the photoresist on the low dielectric constant layer, patterning the photoresist, and etching the low dielectric constant layer to form the plurality of structures.

Abstract: A new method of forming a bi-layer photoresist mask with a reduced critical dimension bias between isolated and dense lines and reduced edge roughness is described. A layer to be etched is provided on a semiconductor substrate wherein the surface of the layer has an uneven topography. The layer to be etched is coated with a first planarized photoresist layer which is baked. The first photoresist layer is coated with a second silicon-containing photoresist layer which is baked. Portions of the second photoresist layer not covered by a mask are exposed to actinic light. The exposed portions of the second photoresist layer are developed away. Then, portions of the first photoresist layer not covered by the second photoresist layer remaining are developed away in a dry development step wherein sufficient SO2 gas is included in the developing recipe to reduce microloading to form a bi-layer photoresist mask comprising the first and second photoresist layers remaining.

Abstract: The present invention provides integrated circuit fabrication methods and devices wherein dual damascene structures (332 and 334) are formed in consecutive dielectric layers (314 and 316) having dissimilar etching characteristics. The present invention also provides for such methods and devices wherein these dielectric layers have different dielectric constants. Additional embodiments of the present invention include the use of single layer masks, such as silicon-based photosensitive materials which form a hard mask (622) upon exposure to radiation. In additional embodiments, manufacturing systems (710) are provided for fabricating IC structures. These systems include a controller (700) which is adapted for interacting with a plurality of fabrication stations (720, 722, 724, 726, 728 and 730).

Abstract: A simple method for calculating the optimum amount of HDP deposited material that needs to be removed during CMP (without introducing dishing) is described. This method derives from our observation of a linear relationship between the amount of material that needs to be removed in order to achieve full planarization and a quantity called “OD for CMP density”. The latter is defined as PA×(100−PS) where PA is the percentage of active area relative to the total wafer area and PS is the percentage of sub-areas relative to the total wafer area. The sub-areas are regions in the dielectric, above the active areas, that are etched out prior to CMP. Thus, once the materials have been characterized, the optimum CMP removal thickness is readily calculated for a wide range of different circuit implementations.

Abstract: The present invention relates to a method of manufacturing a microstructure such as a barrier lib or a spacer formed at an internal space between two flat panels constructing a flat panel display and, in particular, to a method of manufacturing a microstructure using a photosensitive glass substrate. The method of manufacturing a microstructure in accordance with the present invention includes the steps of preparing a photosensitive glass substrate, forming a mask pattern having a light transmission unit and a shading unit on the photosensitive glass substrate, exposing the photosensitive glass substrate, heat-treating the photosensitive glass substrate, and etching an unexposed portion of the photosensitive glass substrate. In addition, the process of changing the thermal expansive coefficient of the microstructure by heat-treating the photosensitive substrate again can be additionally included after etching and removing the unexposed portion.

Abstract: Disclosed is an in-situ process that prevents pattern collapse from occurring after they have been etched in S02-containing plasmas. The developed process involving treating the etched wafer to another plasma comprising of a chemically reducing gas such as Hz. This treatment chemically reduces the hygroscopic sulfites/sulfates left on the surface after the main etch step. The lower sulfite/sulfate concentration on the wafer translates into considerably less moisture pick up and prevents high aspect ratio feature collapse.

Abstract: A method of fabricating an integrated optical component on a silicon-on insulator chip comprising a silicon layer (1) separated from a substrate (2) by an insulating layer (3), the component having a first set of features, eg a rib waveguide (5) at a first level in the silicon layer (1) adjacent the insulating layer (3) and a second set of features, eg a triangular section (5B) at a second level in the silicon layer (1) further from the insulating layer (3), the method comprising the steps of: selecting a silicon-on-insulator chip having a silicon layer (1) of sufficient thickness for the first set of features; fabricating the first set of features in the silicon layer (1) at a first level in the silicon layer; increasing the thickness of the silicon layer (1) in selected areas to form a second level of the silicon layer (1) over part of the first level; and then fabricating the second set of features at the second level in the silicon layer (1).

Abstract: Novel norbornene fluoroacrylate copolymers are provided. The polymers are useful in lithographic photoresist compositions, particularly chemical amplification resists. In a preferred embodiment, the polymers are substantially transparent to deep ultraviolet (DUV) radiation, i.e., radiation of a wavelength less than 250 nm, including 157 nm, 193 nm and 248 nm radiation, and are thus useful in DUV lithographic photoresist compositions. A process for using the composition to generate resist images on a substrate is also provided, i.e., in the manufacture of integrated circuits or the like.

Abstract: There is disclosed a method of producing nano or micro-scale chemical reactor devices and novel devices produced by said method. The method of the invention uses deposited sacrificial layers to provide various channels and reservoirs of reactor devices. Reactor devices of the present invention are chemical reactor devices, electro-chemical reactor devices, or chemical/electro-chemical deivices. A fuel cell embodiment is disclosed.

Abstract: This production process is designed to produce a chromium layer (4) making it possible as it were for the material of the connection bump (8) to remain in a region perfectly bounded by the chromium layer (4).

Abstract: A process and structure for copper damascene interconnects including a tungsten-nitride (WN2) barrier layer formed by atomic layer deposition is disclosed. The process method includes of forming a copper damascene structure by forming a first opening through a first insulating layer. A second opening is formed through a second insulating layer which is provided over the first insulating layer. The first opening being in communication with the second opening. A tungsten-nitride (WN2) layer is formed in contact with the first and second openings. And, a copper layer is provided in the first and second openings. Copper is selectively deposited using a selective electroless deposition technique at low temperature to provide improved interconnects having lower electrical resistivity and more electro/stress-migration resistance than conventional interconnects. Additionally, metal adhesion to the underlying substrate materials is improved and the amount of associated waste disposal problems is reduced.

Abstract: There is provided a positive photoresist for near-field exposure excellent in light utilization efficiency even with small layer thickness of the photoresist layer for image formation, and allowing for reduced pattern edge roughness, and a photolithography method including a step of exposing by the near-field exposure the photoresist layer for image formation made thereof. In a positive photoresist containing an alkali-soluble novolak resin and a quinone diazide compound, the film thickness of the photoresist at the time of exposure is not larger than 100 nm, and the absorption coefficient of the photoresist &agr; (&mgr;m−1) for the exposure light is such that 0.5≦&agr;≦7.