Abstract: A Si-containing water-soluble polymer layer is formed on a resist pattern, and contacting portions of the resist pattern and the Si-containing water-soluble polymer layer are reacted to form Si-containing material layers. Thereafter, the portions of the Si-containing water-soluble polymer layer, which have not reacted with the resist pattern, are removed using deionized water so that Si-containing material layers encompassing the resist pattern remain. Since such Si-containing material layers improve the etching resistance and the thickness of the resist pattern, the semiconductor material having a step difference can be etched. In addition, a CD of the adjacent resist pattern can be increased. Furthermore, since an etching resistance against an electron-beam improves, the shrinkage of the CD when measuring the CD using an in-line scanning electron microscope (ILS) is prevented so that the CD can be maintained.

Abstract: A photolithographic process that involves building a sandwich photoresist structure. A first photoresist layer is formed over a substrate. An anti-reflection layer is formed over the first photoresist layer. A second photoresist layer is formed over the anti-reflection layer. A first photo-exposure is conducted and the exposed second photoresist layer is developed to pattern the second photoresist layer and the anti-reflection layer. Using the second photoresist layer and the anti-reflection layer as a mask, a second photo-exposure and a second photoresist development are conducted to pattern the first photoresist layer.

Abstract: In a method for forming a planarized layer on a semiconductor device having concave and convex structures, a dielectric film is formed on a semiconductor substrate; a photoresist pattern is formed to have a thickness on a portion of the dielectric film other than a convex portion greater than h/n (h and n are real numbers of one or more) to remove the convex portion of the dielectric film by a depth of approximately h. The photoresist pattern is re-flowed to have a thickness below h/n at a portion from an edge of the convex portion to a slant portion of the dielectric film. The dielectric film is etched using an etchant having a selectivity of 1:n between the photoresist pattern and the dielectric film. An edge of the photoresist pattern is made thin by re-flowing thereby minimizing a pillar, hence allowing simple, fast, planarization of the dielectric film.

Abstract: A method of fabricating a plasma display panel includes forming one or more electrodes on a substrate, forming a dielectric layer on the first electrode including the substrate, laminating a dry film photoresist on the dielectric layer, patterning the dry film photoresist using a mask, forming one or more capillary discharge sites in the dielectric layer using sand blasting, and removing the patterned dry film photoresist from the substrate. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: A desired pattern is formed in a photoresist layer that overlies a semiconductor wafer using a reflective mask. This mask is formed by consecutively depositing a reflective layer, an absorber layer and an anti-reflective (ARC) layer. The ARC layer is patterned according to the desired pattern. The ARC layer is inspected to find areas in which the desired pattern is not achieved. The ARC layer is then repaired to achieve the desired pattern with the absorber layer protecting the reflective layer. The desired pattern is transferred to the absorber layer to reveal the reflective portion of mask. Radiation is reflected off the reflective mask to the semiconductor wafer to expose the photoresist layer overlying the semiconductor wafer with the desired pattern.

Abstract: A photoresist pattern is formed, without being exposed, by using photoresist having a residual layer proportion characteristic by which the photoresist dissolves at a suitable rate in a developing solution. First, a target layer to be patterned and a photoresist layer are sequentially formed on a substrate having a pattern that defines a step on the substrate. Some of the photoresist layer is treated with the developing solution, to thereby form a photoresist pattern whose upper surface is situated beneath the step and hence, exposes part of the target layer. Next, the exposed part of the target layer, and the photoresist pattern are removed. A silicidation process may be carried out thereafter on the area(s) from which the target layer has been removed. The method is relatively simple because it does not involve an exposure process. Furthermore, the method can be used to manufacture devices having very fine linewidths, i.e.

Abstract: Provided is a process for creating vias for a circuit assembly including the steps of (a) applying a curable coating composition to a substrate, some or all of which is electrically conductive, to form an uncured coating thereon; (b) applying a resist over the uncured coating; (c) imaging the resist in predetermined locations; (d) developing the resist to expose predetermined areas of the uncured coating; (e) removing the exposed areas of the uncured coating; and (f heating the coated substrate of step (e) to a temperature and for a time sufficient to cure the coating. Also disclosed is a process of fabricating a circuit assembly.

Abstract: Provided is a process for creating a via through a substrate including the steps of (a) providing a substantially void-free film of a curable composition; (b) applying a resist onto the curable film; (c) imaging the resist in predetermined locations; (d) developing the resist to expose predetermined areas of the curable film; (e) removing the exposed areas of the curable film to form holes through the curable film; and (f) heating the curable film of step (e) to a temperature and for a time sufficient to cure the curable composition. Also disclosed is a process of fabricating a circuit assembly which includes building patterned circuit layers upon a substrate that has vias provided by the aformentioned process.

Abstract: After films composing a TFT are laminated on an insulating substrate, a resist mask having a plurality of regions with different film thicknesses is formed by patterning on the uppermost layer of the above-stated films. Then, a conductor film is formed by patterning with a liftoff method using this resist mask. Alternatively, using other resist mask having a plurality of regions with different film thicknesses as an etching mask, a plurality of material films among the laminated material films are processed in succession. By the above-stated new pattern forming method and the processing method, the liquid crystal display device, which has been manufactured by five photolitho processes in a conventional art is manufactured by two or three photolitho processes.

Abstract: An organic electroluminescent display apparatus and method for manufacturing same is disclosed; the method prevents the anode and the cathode from defects and short circuit, and with the suitable geometry of the electrical insulation ramparts, the mechanical properties of the cathode insulating ramparts are increased such that the adhesion between the cathode insulating ramparts and the substrate is enhanced.

Abstract: A method for forming an opening is described. A material layer, a patterned protective layer and a photoresist layer are sequentially formed on a substrate. A first exposure step is performed to form a line/space image on the photoresist layer with a first exposure dosage lower than that required for development. A second exposure step is then performed to define a region to be removed in the photoresist layer with a second exposure dosage, while the sum of the first and the second exposure dosages is equal to that required for development. A development step is conducted to remove the photoresist layer in the region to expose a portion of the patterned protective layer and a portion of the material layer. An etching process is then performed to form an opening in the material layer by using the photoresist layer and the patterned protective layer as a mask.

Abstract: Disclosed are methods of manufacturing electronic devices, particularly integrated circuits. Such methods include the use of low dielectric constant material prepared by using a removable porogen material.

Abstract: A method of forming a system on chip(SOC) comprising read only memory(ROM) and nitride read only memory(NROM) by utilizing nitride read only memory. The method is to form a plurality of field oxide layers on a surface of a substrate in order to define an active area of each device. An ONO dielectric layer is then formed on the surface of the substrate, thereafter performing a photolithography and ion implantation process to form a plurality of N-type bit lines and P-type pocket doping areas in the substrate inside the memory area. After that, an etching process is performed in order to remove regions of the ONO dielectric layer in the periphery area and regions of the ONO dielectric layer in the memory area, optionally. After that, a thermal oxidation process is utilized in order to form a buried drain oxide layer atop each bit line and a gate oxide layer on the surface of the active area in the periphery area, respectively.

Abstract: A manufacturing method for a MOSFET gate structure. The method comprises providing a substrate, sequentially depositing a pad layer and a dielectric layer thereon, defining a gate trench passing through the dielectric layer and the pad layer to expose a predetermined gate area of the substrate, sequentially forming a gate dielectric layer, a first conductive layer, a second conductive layer, and a cap layer on the exposed substrate in the gate trench to form a damascene gate structure, and removing the dielectric layer.

Abstract: A method of forming an opening in a wafer layer. At least two patterned photoresist layers are formed on a wafer layer. Using different photoresist layers, many openings are defined. The wafer layer is then etched to form the opening. Each photoresist layer has a parallel linear pattern such as parallel strips or an array of rectangular blocks. The photoresist layers are superposed in a way that spaces between the patterns for each photoresist layers overlapped with each other for form openings that expose the underlying wafer layers. The wafer layer exposed in the openings is then etched to form contact/via holes without rounded corners while the rounded profiles has been cancelled by the superposition of the photoresist layers.

Abstract: An etch barrier to be used in a photolithograph process is disclosed. A silicon rich etch barrier is deposited on a substrate using a low energy deposition technique. A diamond like carbon layer is deposited on the silicon rich etch barrier. Photoresist is then placed on this etch barrier DLC combination. To form photolithographic features, successive steps of oxygen and flourine reactive ion etching is used.

Abstract: This invention provides a pattern formation material for electron beam lithography, which contains an alkali-soluble resin, a photoacid generator, and dissolution inhibiting groups, and also provides a pattern formation method and exposure mask fabrication method using the material. As the dissolution inhibiting groups, this invention uses a first dissolution inhibiting group which increases the sensitivity of the pattern formation material when the material is left to stand in a vacuum after an electron beam irradiation, and a second dissolution inhibiting group which decreases the sensitivity under the same condition. In this invention, the ratio of the first dissolution inhibiting group to the second dissolution inhibiting group is so adjusted that the size of an alkali-soluble portion, which is made soluble in an alkali solution by an electron beam irradiation, is substantially held constant independently of the standing time in a vacuum.

Abstract: A process is described for trimming photoresist patterns during the fabrication of integrated circuits for semiconductor devices and MEMS devices. A combination of a low temperature (<20° C.), high density oxygen and argon plasma and intense UV radiation is used to simultaneously trim and harden a photoresist linewidth in an ICP chamber. As an alternative, a UV hardening step can be performed in a flood exposure tool prior to the ICP plasma etch. Another option is to perform the argon plasma treatment first to harden the resist and then in a second step apply an oxygen plasma to trim the photoresist. Vertical and horizontal etch rates are decreased in a controllable manner which is useful for producing gate lengths in MOS transistors of less than 100 nm. The process can also be used to controllably increase a space width in a photoresist feature.

Abstract: A desirable pattern is formed in a photoresist layer that overlies a semiconductor wafer using an attenuating phase shift reflective mask. This mask is formed by consecutively depositing an attenuating phase shift layer, a buffer layer and a repairable layer. The repairable layer is patterned according to the desirable pattern. The repairable layer is inspected to find areas in which the desirable pattern is not achieved. The repairable layer is then repaired to achieve the desirable pattern with the buffer layer protecting the attenuating phase shift layer. The desirable pattern is transferred to the buffer layer and then transferred to the attenuating phase shift layer to achieve the attenuating phase shift reflective mask. Radiation is reflected off the attenuating phase shift reflective mask to the photoresist layer to expose it with the desirable pattern.

Abstract: A thinner for rinsing photoresist including 50 to 80 wt. % of n-butyl acetate, propylene glycol alkyl ether, and propylene glycol alkyl ether acetate, is provided. The thinner is neither toxic to humans nor ecologically undesirable and has no unpleasant odor. The waste solutions thereof and associated waste water are easily handed so as to render this thinner environmental friendly. Additionally, the photoresist thinner of the present invention has excellent rinsing ability.

Abstract: A method of fabricating a semiconductor multilevel interconnect structure employs a dual hardmask technique in a dual damascene process. The method includes using amorphous carbon as a first hardmask layer capable of being etched by a second etch process, and a second hardmask layer capable of being etched by a first etch process, as a dual hardmask. By virtue of the selective etch chemistry employed with the dual hardmask, the method affords flexibility unattainable with conventional processes. The via is never in contact with the photoresist, thus eliminating residual photoresist at the trench/via edge and the potential “poisoning” of the intermetal dielectric layer. Since trench/via imaging is completed before further etching, any patterning misalignments can be easily reworked. Because the amorphous carbon layer and the second hardmask layer are used as the dual hardmask, the photoresist can be made thinner and thus optimized for the best imaging performance.

Abstract: A dual damascene process using a single photo mask in which a photo mask having patterns with different transparency is applied. A mask layer with a dual layer opening is formed first and then serves as an etching mask to form a dual opening in the dielectric layer. Then a metal layer is filled in the dual layer opening in the dielectric layer to form a dual damascene structure. Therefore, only a single photolithography process is necessary and overlay due to misalignment can be avoided.

Abstract: A method including forming a photoimageable material on a substrate; developing the photoimageable material over an opening area, the photoimageable material over a first portion of the opening area developed to a first extent and the photoimageable material over a second portion of the opening area developed to a different second extent; removing developed photoimageable material from the opening area; and forming an opening in the substrate in the opening area.

Abstract: The present invention to a method for forming an exposed portion of a circuit pattern in a printed circuit board, wherein a solder resist is coated on a substrate having a circuit pattern, is hardened, and thereafter is processed by a laser in order to form a portion exposing the circuit pattern such as the solder land. When the solder resist is processed by the laser, the number of errors can be greatly reduced as compared to a processing error occurred in exposure or developing process, whereby a circuit pattern that is integrated higher than the solder land is formed for thereby miniaturizing the printed circuit board.

Abstract: A chemically amplified resist composition comprises an aqueous base soluble polymer or copolymer having one or more polar functional groups, wherein at least one of the functional groups is protected with a cycloaliphatic silyl ketal group but may also include other protecting groups as well as unprotected acidic functionalities. A ratio of protected to unprotected acidic functionalities is preferably selected to most effectively modulate a solubility of the resist composition in an aqueous base or other developer. The resist composition further comprises an acid generator, preferably a photoacid generator (PAG), and a casting solvent, and may also include other components, such as, a base additive and/or surfactant.

Abstract: A method for improving a photolithographic patterning process in a dual damascene process including providing at least one via opening in a substrate including a low dielectric constant material; blanket depositing a photo-sensitive resinous layer to fill the at least one via opening; partially removing the photo-sensitive resinous layer to form an at least partially filled via plug; photo-curing the via plug such that an activating light source causes a polymer cross-linking chemical reaction; and, forming a trench line opening disposed substantially over the at least one via opening using a trench line photoresist to pattern the trench line opening.

Abstract: Disclosed is a method for fabricating a plate-type magnetic resistance sensor chip simply and easily. First, a characteristic membrane composed of NiCo and NiFe is deposited over a surface of a glass wafer, exposed to light, and etched in a predetermined pattern to establish sensing parts. Then, a protective film is formed atop each of the sensing parts by depositing a SiO2 membrane over the glass wafer, exposing the SiO2 membrane to light, and etching the SiO2 membrane in the same pattern as in the sensing part. The resulting structure is subjected to sand blasting to form through-holes at every corner of the sensing parts. A NiFe film is deposited around the through-holes on both sides of the glass wafer and within the through-holes to form conductors.

Abstract: Photoresist compositions, which can attain high-accuracy etching without causing separation and flexible printed wiring boards prepared with the photoresist compositions are disclosed. In order to etch a polyimide precursor layer on a conductive circuit, a photoresist composition comprising a photopolymerizable organic material (A), a water-soluble resin (B) and an amino-group-containing resin (C) is applied on the surface of the polyimide precursor layer to form a photoresist layer. Then, the photoresist layer is patterned by a photolithographic process. The polyimide precursor layer is etched and the pattern of the photoresist layer is transferred to the polyimide precursor layer. The amino-group-containing resin (C) in the photoresist layer is combined with an acid anhydride in the polyimide precursor layer to attain good adhesion and high-accuracy etching without causing separation of the photoresist layer.

Abstract: A method of passivating silicon-oxide based low-k materials using a supercritical carbon dioxide passivating solution comprising a silylating agent is disclosed. The silylating agent is preferably an organosilicon compound comprising organo-groups with five carbon atoms such as hexamethyldisilazane (HMDS) and chlorotrimethylsilane (TMCS) and combinations thereof. The silicon oxide-based low-k material, in accordance with embodiments of the invention, is maintained at temperatures in a range of 40 to 200 degrees Celsius, and preferably at a temperature of about 150 degrees Celsius, and at pressures in a range of 1,070 to 9,000 psi, and preferably at a pressure of about 3,000 psi, while being exposed to the supercritical passivating solution. In accordance with further embodiments of the invention, a silicon oxide-based low-k material is simultaneously cleaned and passivated using a supercritical carbon dioxide cleaning solution.

Abstract: A method of forming a resist pattern includes a step of forming a resist pattern on a substrate or on a layer formed on a substrate using a resist material containing a material generating acid by exposure or heating, a step of coating only a water-soluble cross-linking agent on the resist pattern, the water-soluble cross-linking agent being cross-linked in the presence of acid, a step of coating a resin material containing at least a water-soluble resin on the water-soluble cross-linking agent, and a step of exposing or heating the resist pattern to generate acid from the resist pattern, a cross-linking reaction of the water-soluble cross-linking agent being occurred in the presence of the generated acid to form a covering layer over the resist pattern.

Abstract: There is provided a method for forming a photoresist layer for photolithographic applications which has increased structural strength. The photoresist layer is exposed through a mask and developed. The photoresist layer is then treated to change its material properties before the photoresist layer is dried. Also provided are a semiconductor fabrication method employing a treated photoresist and a composition for a treatable photoresist.

Abstract: Within a method for forming a patterned polyimide layer, there is first provided a substrate. There is then formed over the substrate a blanket polyamic acid layer. There is then formed upon the blanket polyamic acid layer a patterned photoresist layer. There is then hardened the patterned photoresist layer to form a hardened patterned photoresist layer. There is then patterned, while employing the hardened patterned photoresist layer as an etch mask layer, the blanket polyamic acid layer to form a patterned polyamic acid layer. Finally, there is then thermally annealed the patterned polyamic acid layer to form a patterned polyimide layer. By employing as an etch mask when forming from the blanket polyamic acid layers the patterned polyamic acid layer the hardened patterned photoresist layer, rather than an unhardened patterned photoresist layer, the patterned polyamic acid layer, and consequently also the patterned polyimide layer, are formed with enhanced dimensional control.

Abstract: Nanolaminates are formed by alternating deposition, e.g., by combustion chemical vapor deposition (CCVD), layers of resistive material and layers of dielectric material. Outer resistive material layers are patterned to form discrete patches of resistive material. Electrical pathways between opposed patches of resistive material on opposite sides of the laminate act as capacitors. Electrical pathways horizontally through resistive material layers, which may be connected by via plated holes, act as resistors.

Abstract: The present invention provides a resist composition comprising (A) polyhydroxystyrene in which at least a portion of hydrogen atoms of hydroxyl groups are substituted with an acid-dissociable dissolution inhibiting group, and the solubility in an alkali solution of the polyhydroxystyrene increasing when the acid-dissociable dissolution inhibiting group is eliminated by an action of an acid, and (B) a component capable of generating an acid by irradiation with radiation, wherein a retention rate of the acid-dissociable dissolution inhibiting group of the component (A) after a dissociation test using hydrochloric acid is 40% or less, and also provides a chemical amplification type positive resist composition which contains polyhydroxystyrene in which at least a portion of hydrogen atoms of hydroxyl groups are substituted with a lower alkoxy-alkyl group having a straight-chain or branched alkoxy group, and the solubility in an alkali solution of the polyhydroxystyrene increasing when the lower alkoxy-alkyl group

Abstract: The present invention aims to provide a method of manufacturing a semiconductor device having an SOI structure, which is capable of setting an etching process so as to cause contact etching to widely have a process margin even in a semiconductor elemental device using an extra-thin SOI layer. The present method is a method of manufacturing a fully depleted-SOI device. A cobalt layer is formed on an SOI layer. Cobalt is transformed into a cobalt silicide layer by heat treatment. An interlayer insulating film is formed on the cobalt silicide layer, and a contact hole is defined in the interlayer insulating film by dry etching. As an etching gas used in such a dry etching step, a CHF3/CO gas is used. An etching condition is set through the use of a dry etching rate held substantially constant by use of the etching gas. Described specifically, etching time is suitable set.

Abstract: Disclosed are methods of manufacturing electronic devices, particularly integrated circuits. Such methods include the use of low dielectric constant material prepared by using a removable porogen material.

Abstract: Disclosed are methods of manufacturing electronic devices, particularly integrated circuits. Such methods include the use of low dielectric constant material prepared by using a removable porogen material.

Abstract: A method of photolithography. An anti-reflective coating is formed on the conductive layer. An nitrogen plasma treatment is performed. A photo-resist layer is formed and patterned on the anti-reflective coating. The conductive layer is defined. The photo-resist layer is removed. The anti-reflective layer is removed by using phosphoric acid.

Abstract: Provision of a manufacturing method for forming lamination of a plurality of dielectric layers on a substrate of a plasma display panel. A forming process for forming a photosensitive glass material layer and a patterning process for exposing required regions of the resulting photosensitive glass material layer to light are repeated in each formation of a first photosensitive glass material layer L1 and a second photosensitive glass material layer L2. After completion of the individual forming process and the individual patterning process for each of the first and second photosensitive glass material layers L1 and L2, a developing process for removing the unexposed regions and a burning process following the developing process are each performed on both of the first and second photosensitive glass material layers L1 and L2 together.

Abstract: The present invention pertains to a method for depositing built-up structures on the surface of patterned masking material used for semiconductor device fabrication. Such built-up structures are useful in achieving critical dimensions in the fabricated device. The composition of the built-up structure to be fabricated is dependant upon the plasma etchants used during etching of underlying substrates and on the composition of the substrate material directly underlying the masking material.

Abstract: A method of producing an integrated circuit configuration where trenches are formed surrounding active regions in a main surface of a semiconductor substrate. A photoresist layer is applied to the insulating layer and structured forming a mask using a data processing device, by the following steps: Providing an idealized pattern representing trenches with contours corresponding to contours of the trenches. Producing an idealized mask pattern on the basis of the idealized pattern shifted by an allowance in comparison with the idealized pattern, the idealized mask pattern has surface zones whose distance apart is shorter than a given minimum measurement. The idealized mask pattern is used to produce a further idealized mask pattern in which the surface zones are replaced by minimum surface elements with length measurements which are greater than the given minimum measurement. The trenches are then filled by depositing an insulating layer using the formed mask.

Abstract: A composition for an anti-reflective layer capable of simultaneously being developed together with a photoresist layer after exposure of the photoresist layer in a photolithography process and a method for forming patterns in a semiconductor device using the composition, wherein the anti-reflective light absorbing layer composition includes a polymer having a (meth)acrylate repeating unit, a light-absorbing group of diazoquinones chemically bound to the (meth)acrylate repeating unit, a photoacid generator, a cross-linker which thermally cross-links the polymer and is decomposed from the polymer by an acid, and a catalyst for the cross-linking reaction of the polymer. The method for forming patterns in a semiconductor device involves forming an anti-reflective layer on a semiconductor substrate using the composition and simultaneously exposing the anti-reflective layer and a photoresist layer, thereby chemically transforming the anti-reflective layer so it is able to be developed.

Abstract: A method of forming small features, comprising the following steps. A substrate having a dielectric layer formed thereover is provided. A spacing layer is formed over the dielectric layer. The spacing layer has a thickness equal to the thickness of the small feature to be formed. A patterned, re-flowable masking layer is formed over the spacing layer. The masking layer having a first opening with a width “L”. The patterned, re-flowable masking layer is re-flowed to form a patterned, re-flowed masking layer having a re-flowed first opening with a lower width “1”. The re-flowed first opening lower width “1” being less than the pre-reflowed first opening width “L”. The spacing layer is etched down to the dielectric layer using the patterned, re-flowed masking layer as a mask to form a second opening within the etched spacing layer having a width equal to the re-flowed first opening lower width “1”. Removing the patterned, re-flowed masking layer.

Abstract: A patterning method includes providing a first material (e.g., copper) and transforming at a least a surface region of the first material to a second material (e.g., copper oxide). One or more portions of the second material (e.g., copper oxide) are converted to one or more converted portions of first material. (e.g., copper) while one or more portions of the second material (e.g., copper oxide) remain. One or more portions of the remaining second material (e.g., copper oxide) are removed selectively relative to converted portions of first material (e.g., copper). Further, a thickness of the converted portions may be increased. Yet further, a diffusion barrier layer may be used for certain applications.

Abstract: A method for forming cells array of mask read only memory, at least includes: form numerous gate structures on substrate; form numerous doped regions in uncovered part of substrate; form first conductor layer on uncovered part of substrate with a thickness essentially equal to thickness of gate structures; form first dielectric layer on first conductor layer; form second conductor layer on both gate structures and first dielectric layer; perform a pattern transform process for transferring both second conductor layer and gate structures into conductor lines as word lines; form second dielectric layer on sidewalls of conductor lines to form spacer; form code photoresist on second conductor layer; and perform ions implantation process for implant numerous ions into partial substrate which is not covered by code photoresist.

Abstract: Disclosed are methods of manufacturing electronic devices, particularly integrated circuits. Such methods include the use of low dielectric constant material prepared by using a removable porogen material.

Abstract: There is provided a negative radiation-sensitive composition, which is suitable for exposure of a far ultraviolet light comprising a wavelength 193 nm of ArF excimer-laser, freed from causes of resolution deterioration such as swelling due to permeation of a developer and residual of a resist film between lines of the pattern, and capable of forming a high resolution pattern.

Abstract: The invention is directed to a method of fabricating sub-wavelength features in semiconductors and insulators by starting with optical lithography patterns defined in a resist and then employing shadow-evaporation and directional etching to define nano-scale features. The directionality of this process is used together with a carefully defined photoresist mask to define an ion etching mask which allows the formation of very narrow trenches adjacent to the photoresist regions. Such narrow trenches can be used for electrical device isolation, for the definition of very small flow channels, and for the deposition of very narrow electrical contacts and wires.

Abstract: The present invention provides an organic anti-reflective film composition suitable for use in submicrolithography. The composition comprises a compound of chemical formula 11 and a compound of chemical formula 12. The organic anti-reflective film effectively absorbs the light penetrating through the photoresist film coated on top of the anti-reflective film, thereby greatly reducing the standing wave effect. Use of organic anti-reflective films of the present invention allows patterns to be formed in a well-defined, ultrafine configuration, providing a great contribution to the high integration of semiconductor devices. wherein a, b, c, R′, R″, R1, R2, R3, and R4 are those defined herein.

Abstract: A method for forming a passivation coating on a semiconductor wafer. The method comprises: forming a silicon dioxide layer on the semiconductor wafer, forming a silicon nitride layer on the silicon dioxide layer; forming a polyimide layer on the silicon nitride layer; patterning and etching the polyimide layer to expose a portion of the silicon nitride layer according to a first photomask; and etching the silicon dioxide layer and the exposed silicon nitride layer to expose the fuse, the fuse window and the metal layer, the silicon dioxide layer and the silicon nitride layer being etched by an anisotropic etching step using the patterned polyimide layer as a mask.