Metal Etched Patents (Class 430/318)
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Patent number: 12019833Abstract: A touch structure, a touch display panel and an electronic device are provided. The touch structure includes a first metal mesh layer and a second metal mesh layer, the first metal mesh layer includes a first touch electrode and second touch sub-electrodes, the second metal mesh layer includes second connection electrodes spaced apart from each other, and each of the second connection electrodes is electrically connected with an adjacent second touch sub-electrode through via holes in the insulation layer. At least two first metal meshes of the second touch sub-electrodes include multiple vertices overlapping with at least two second metal meshes of the second connection electrodes, the multiple vertices include connection vertices, and the via holes are respectively disposed at the connection vertices; at most one of vertices adjacent to each connection vertex is a connection vertex. The touch structure can effectively reduce capacitance load on the touch electrodes.Type: GrantFiled: April 1, 2020Date of Patent: June 25, 2024Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Kemeng Tong, Fan He, Cong Fan, Junxi Wang
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Patent number: 11907486Abstract: A touch structure, a touch display panel and an electronic device are provided. The touch structure includes a first metal mesh layer and a second metal mesh layer, the first metal mesh layer includes a first touch electrode and second touch sub-electrodes, the second metal mesh layer includes second connection electrodes spaced apart from each other, and each of the second connection electrodes is electrically connected with an adjacent second touch sub-electrode through via holes in the insulation layer. At least two first metal meshes of the second touch sub-electrodes include multiple vertices overlapping with at least two second metal meshes of the second connection electrodes, the multiple vertices include connection vertices, and the via holes are respectively disposed at the connection vertices; at most one of vertices adjacent to each connection vertex is a connection vertex. The touch structure can effectively reduce capacitance load on the touch electrodes.Type: GrantFiled: April 1, 2020Date of Patent: February 20, 2024Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Kemeng Tong, Fan He, Cong Fan, Junxi Wang
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Patent number: 11869770Abstract: Methods, systems, and computer programs are presented for selective deposition of etch-stop layers for enhanced patterning during semiconductor manufacturing. One method includes an operation for adding a photo-resist material (M2) on top of a base material (M1) of a substrate, M2 defining a pattern for etching M1 in areas where M2 is not present above M1. The method further includes operations for conformally capping the substrate with an oxide material (M3) after adding M2, and for gap filling the substrate with filling material M4 after the conformally capping. Further, a stop-etch material (M5) is selectively grown on exposed surfaces of M3 and not on surfaces of M4 after the gap filling. Additionally, the method includes operations for removing M4 from the substrate after selectively growing M5, and for etching the substrate after removing M4 to transfer the pattern into M1. M5 adds etching protection to enable deeper etching into M1.Type: GrantFiled: July 29, 2021Date of Patent: January 9, 2024Assignee: Lam Research CorporationInventors: Nagraj Shankar, Kapu Sirish Reddy, Jon Henri, Pengyi Zhang, Elham Mohimi, Bhavin Jariwala, Arpan Pravin Mahorowala
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Patent number: 11789571Abstract: A touch structure, a touch display panel and an electronic device are provided. The touch structure includes a first metal mesh layer including first touch electrodes spaced and extended along a first direction, each first touch electrode includes first touch sub-electrodes and first connection electrodes arranged along the first direction and connected with each other, and the first metal mesh layer further includes second touch sub-electrodes spaced and arranged sequentially along a second direction; at least one first metal mesh includes three insulated first metal mesh parts which are respectively belong to three insulated touch sub-electrodes; the three touch sub-electrodes include two first touch sub-electrodes adjacent in the second direction and a second touch sub-electrode, or includes two second touch sub-electrodes adjacent in the first direction and a first touch sub-electrode.Type: GrantFiled: April 1, 2020Date of Patent: October 17, 2023Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Kemeng Tong, Fan He, Cong Fan, Junxi Wang
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Patent number: 11782542Abstract: The first and second touch electrodes constitute a mesh shape of staying away from overlap with the light-emitting pixels. Each electrode body has a first slim portion between adjacent light-emitting pixels in the first direction. Each electrode body has a first wide portion between adjacent light-emitting pixels in the second direction. The first wide portion is wider than the first slim portion. The jumper electrode has a second slim portion between adjacent light-emitting pixels in the first direction. The jumper electrode has a second wide portion between adjacent light-emitting pixels in the second direction. The second wide portion is wider than the second slim portion. The light-emitting pixels each have a planar shape longer in the second direction than in the first direction. The first and second wide portions are overlapped and electrically conductive, penetrating the insulation film.Type: GrantFiled: October 13, 2020Date of Patent: October 10, 2023Assignee: Japan Display Inc.Inventors: Mitsuhide Miyamoto, Hajime Akimoto
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Patent number: 11782558Abstract: A touch structure, a touch display panel and an electronic device are provided. The touch structure includes multiple first touch sub-electrodes and second touch sub-electrodes. Multiple first metal lines in a boundary region between adjacent first and second touch sub-electrodes respectively include multiple spaces; each space divides a first metal line, where it is located, into two first metal line segments to insulate the adjacent first and second touch sub-electrodes. The spaces include multiple first spaces which are in a first line and respectively on multiple first metal lines intersecting with the first line that is substantially extended along a certain direction. Between at least two first spaces is provided with at least one first metal line intersecting the first straight line, and no space is at an intersection of the each one first metal line and the first line. The touch structure has a good effect of shadow elimination.Type: GrantFiled: April 1, 2020Date of Patent: October 10, 2023Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Cong Fan, Fan He, Kemeng Tong, Zhenhua Zhang
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Patent number: 11714105Abstract: A socket electrically connects a first electric component and a second electric component, including: a base part in which a through hole extending through the base part from a top surface to a bottom surface in a vertical direction is formed; a contact pin inserted to the through hole such that a pin lower end is exposed from the bottom surface, and configured such that, when in use, a pin upper end makes contact with the first electric component; and a sheet member including a through electrode extending therethrough in the vertical direction, disposed at the base part in a state where the sheet member faces the bottom surface, and configured such that, when in use, an upper end of the through electrode makes contact with the pin lower end and a lower end of the through electrode makes contact with the second electric component.Type: GrantFiled: March 30, 2021Date of Patent: August 1, 2023Assignee: Enplas CorporationInventor: Leo Azumi
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Patent number: 11335658Abstract: A method comprises applying a metal-paste printing process to a surface-mount device to form a metal pillar, placing a first semiconductor die adjacent to the surface-mount device, forming a molding compound layer over the first semiconductor die and the surface-mount device, grinding the molding compound layer until a top surface of the first semiconductor die is exposed and forming a plurality of interconnect structures over the molding compound layer.Type: GrantFiled: December 17, 2018Date of Patent: May 17, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jing-Cheng Lin, Chen-Hua Yu, Jui-Pin Hung, Der-Chyang Yeh
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Patent number: 10451777Abstract: The present disclosure relates to the technical field of metal surface plasma and light emitting display, and provides an optical component for controlling a light emergent direction and a manufacturing method thereof. An optical component for controlling a light emergent direction includes: a transparent substrate; a plurality of metal film strips arranged in parallel at equal pitches on the surface of the transparent substrate along a first direction and extending in a second direction that is perpendicular to the first direction; and dielectric gratings formed respectively on the plurality of metal film strips, wherein slits of the dielectric gratings extend along the second direction.Type: GrantFiled: March 28, 2018Date of Patent: October 22, 2019Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.Inventor: Jinghai Liu
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Patent number: 9820386Abstract: A method of forming an electronic assembly. The method includes covering a patterned conductive layer that is on a dielectric layer with a solder resist; depositing a metal layer on to the solder resist; depositing a photo resist onto the metal layer; patterning the photo resist; etching the metal layer that is exposed from the photo resist to form a metal mask; removing the photo resist; and plasma etching the solder resist that is exposed from the metal mask. An electronic assembly for securing for an electronic card. The electronic assembly includes a patterned conductive layer that is on a dielectric layer; and a solder resist covering the patterned conductive layer and the dielectric layer, wherein the solder resist includes openings that expose the patterned conductive layer, wherein the openings in the solder resist only have organic material on side walls of the respective openings.Type: GrantFiled: March 18, 2016Date of Patent: November 14, 2017Assignee: Intel CorporationInventors: Kristof Darmawikarta, Rahul Jain, Robert Alan May, Sheng Li, Sri Ranga Sai Boyapati
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Patent number: 9686867Abstract: Methods to systematize the development of machines using inexpensive, fast, and convenient fabrication processes are disclosed. In an embodiment, a folding pattern and corresponding circuit design can provide the blueprints for fabrication. The folding pattern may be provided (e.g. laser machined) on a flat sheet of substrate material, such as a polymer. The circuit pattern may be generated by etching or applying (e.g. sputtering) a copper foil layer onto the substrate. Circuit components and actuators may then be added at specified locations. The flat substrate may then be folded along the predefined locations to form the final machine. The machine may operate autonomously to perform a task.Type: GrantFiled: December 21, 2012Date of Patent: June 20, 2017Assignees: Massachussetts Institute of Technology, President and Fellows of Harvard CollegeInventors: Daniela Rus, Robert J. Wood, Cagdas Denizel Onal, Michael Tolley
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Patent number: 9666609Abstract: This disclosure relates to an array substrate wiring and manufacturing and repairing method thereof. The array substrate wiring comprises a first wiring formed on the substrate for transmitting electric signals; an insulating layer formed on the first wiring; a second wiring formed on the insulating layer, being opposite to the first wiring, the second wiring being in a hanging state and not transmitting electric signals. By means of such a double layer wiring structure, the holes produced in the insulating layer are blocked using the second wiring in the upper layer, such that the outside moisture cannot reach the first wiring via the holes in the insulating layer, thereby protecting the first wiring for transmitting electric signals from corrosion and scratch.Type: GrantFiled: August 26, 2014Date of Patent: May 30, 2017Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Chao Liu, Yujun Zhang, Zengsheng He, Lei Chen
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Patent number: 9404188Abstract: This invention relates to novel corrosion inhibitors which are capable of sequestering metal ions such as calcium and magnesium and are derived in part from renewable carbohydrate feedstocks. The corrosion inhibitors are mixtures containing one or more hydroxycarboxylic acid salts and one or more suitable oxoacid anion salts.Type: GrantFiled: November 10, 2011Date of Patent: August 2, 2016Assignee: Rivertop RenewablesInventors: Tyler N. Smith, Donald E. Kiely, Kylie Kramer-Presta
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Patent number: 9337033Abstract: A process for patterning a hard mask material with line-space patterns below a 30 nm pitch and a 15 nm critical dimension by employing a spin-on titanium-silicon (TiSi) polymer or oligomer as a tone inversion material is provided. The spin-on TiSi material is spin-coated over a patterned OPL that includes a first pattern generated from a DSA based process. The spin-on TiSi material fill trenches within the patterned OPL to form a tone inverted pattern by removing the patterned OPL selective to the spin-on TiSi material. The inverted pattern is a complementary pattern to the first pattern, and is transferred into the underlying hard mask material by an anisotropic etch.Type: GrantFiled: November 19, 2015Date of Patent: May 10, 2016Assignee: International Business Machines CorporationInventors: Martin Glodde, Wu-Song Huang, Hiroyuki Miyazoe, Ratnam Sooriyakumaran, Hsinyu Tsai
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Patent number: 9293319Abstract: Methods of removing metal from a portion of a substrate are useful in integrated circuit fabrication. Methods include exposing the substrate to an oxidizing environment comprising at least one oxidizing agent and at least one reducing agent, and exposing the substrate to a reducing environment comprising at least one reducing agent and at least one oxidizing agent.Type: GrantFiled: March 9, 2011Date of Patent: March 22, 2016Assignee: Micron Technology, Inc.Inventors: Brian Dolan, Robert J. Hanson, Chan Lim
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Patent number: 9274432Abstract: A method for isolating microstructural regions or features on a surface for electrochemical experimentation comprising polishing a metal sample, coating the metal sample with a photoresist, selecting a region of interest of the metal sample, exposing the region of interest with light energy, developing the exposed photoresist and creating a developed region.Type: GrantFiled: September 14, 2012Date of Patent: March 1, 2016Assignee: The United States of America, as represented by the Secretary of the NavyInventors: Farrel Martin, Alberto Píqué, Raymond C Y Auyeung, Steve Policastro
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Patent number: 9253890Abstract: Provided is a patterned conductive film may include a conductive interconnected nano-structure film. The conductive interconnected nano-structure film may include a first region and a second region adjacent to the first region. A conductivity of the first region may be at least 1000 times a conductivity of the second region.Type: GrantFiled: November 15, 2013Date of Patent: February 2, 2016Assignee: Industrial Technology Research InstituteInventors: Yu-Pei Chang, Ming-Huan Yang, Chun-Yi Chiu
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Patent number: 9150969Abstract: In a method of etching a metal layer of an object to be processed, the metal layer is etched by ion sputtering etching while forming a protective film containing carbon on a surface of a mask of the object. The object is exposed to an oxygen plasma after etching the metal layer. The object is exposed to hexafluoroacetylacetone after exposing the object to the oxygen plasma.Type: GrantFiled: March 4, 2014Date of Patent: October 6, 2015Assignee: TOKYO ELECTRON LIMITEDInventors: Eiichi Nishimura, Fumiko Yamashita, Koyumi Sasa
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Patent number: 9040227Abstract: A microstructure manufacturing method includes forming a layer of a photosensitive resin on a substrate surface having an electrical conductivity, forming a structure of the photosensitive resin by exposing the layer of the photosensitive resin to light and developing the layer of the photosensitive resin to expose a part of the substrate surface, forming a first plated layer on the exposed part of the substrate surface by soaking the structure of the photosensitive resin in a first plating solution, curing the structure of the photosensitive resin after forming the first plated layer, removing at least part of the first plated layer after curing the structure of the photosensitive resin, and forming a second plated layer on a part where the first plated layer is removed, by soaking the structure of the photosensitive resin in a second plating solution different from the first plating solution.Type: GrantFiled: February 17, 2012Date of Patent: May 26, 2015Assignee: Canon Kabushiki KaishaInventors: Takayuki Teshima, Yutaka Setomoto
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Patent number: 8951425Abstract: A method of forming at least one curved plate having first and second layers, the first layer being formed of a first material and the second layer being formed of a second material, the method including forming one or more blocks of a fusible material on a surface of a substrate; baking the one or more blocks to deform their shape; and depositing the first and second materials over the one or more deformed blocks to form the first and second layers.Type: GrantFiled: March 28, 2013Date of Patent: February 10, 2015Assignee: STMicroelectronics (Crolles 2) SASInventors: Stéphane Monfray, Thomas Skotnicki, Onoriu Puscasu, Christophe Maitre
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Patent number: 8945820Abstract: The present invention is a silicon-containing resist underlayer film-forming composition containing a condensation product and/or a hydrolysis condensation product of a mixture comprising: one or more kinds of a compound (A) selected from the group consisting of an organic boron compound shown by the general formula (1) and a condensation product thereof and one or more kinds of a silicon compound (B) shown by the general formula (2). Thereby, there can be provided a silicon-containing resist underlayer film-forming composition being capable of forming a pattern having a good adhesion, forming a silicon-containing film which can be used as a dry-etching mask between a photoresist film which is the upperlayer film of the silicon-containing film and an organic film which is the underlayer film thereof, and suppressing deformation of the upperlayer resist during the time of dry etching of the silicon-containing film; and a patterning process.Type: GrantFiled: November 2, 2012Date of Patent: February 3, 2015Assignee: Shin-Etsu Chemical Co., Ltd.Inventors: Tsutomu Ogihara, Takafumi Ueda, Yoshinori Taneda
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Patent number: 8927189Abstract: A photoresist composition including a binder resin including a novolac resin represented by Chemical Formula 1, a diazide photosensitive initiator, and a solvent including a base solvent and an auxiliary solvent, wherein the base solvent includes propylene glycol monomethyl ether acetate, and the auxiliary solvent includes dimethyl-2-methylglutarate and ethyl beta-ethoxypropionate, wherein in Chemical Formula 1, R1 to R9 are each independently a hydrogen atom or an alkyl group, “a” is an integer number from 0 through 10, “b” is an integer number from 0 through 100, and “c” is an integer number from 1 through 10.Type: GrantFiled: August 7, 2013Date of Patent: January 6, 2015Assignee: Samsung Display Co., Ltd.Inventors: Gwui-Hyun Park, Pil Soon Hong, Jinho Ju, Taegyun Kim, Jin-Su Byun, Dong Min Kim, Seung Ki Kim, Doo Youn Lee
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Publication number: 20140377690Abstract: A manufacturing method of a mask plate and an array substrate is provided. The mask plate is for manufacturing fanout leads in a non-effective display area on an array substrate. The mask plate includes a fanout lead pattern having a plurality of fanout impression lines, wherein each fanout impression line has a predetermined line width, and each of some of the fanout impression lines has at least one curve portion, wherein for one fanout impression line, a line width of the at least one curve portion is smaller than the predetermined line width of the fanout impression line. A manufacturing method of an array substrate utilizes the foregoing mask plate to manufacture the array substrate.Type: ApplicationFiled: July 1, 2013Publication date: December 25, 2014Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd.Inventor: Hua Zheng
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Patent number: 8911932Abstract: Disclosed are the deactivation mechanism and chemistry platforms that make high-silicon hardmask films photo-imageable like positive-tone photoresist for microphotolithography. The deactivation mechanism requires a catalyst to promote crosslinking reactions, and a photoacid generator to deactivate the catalyst. The initial hardmask films are soluble in developers. If not radiated, films become insoluble in developers due to crosslinking reactions promoted by catalyst. If radiated, films remain soluble in developers due to deactivation of catalyst by photoacid generator. Compositions of positive-tone photo-imageable hardmask based on the chemistry of polysiloxane and polysilsesquioxanes are disclosed as well. Also disclosed is a method of modifying polysiloxane and polysilsesquioxane films for controlled diffusion of catalysts, photoacid generators, and quenchers.Type: GrantFiled: April 12, 2010Date of Patent: December 16, 2014Inventor: Sam Xunyun Sun
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Patent number: 8906491Abstract: Described is a multi-layer body (1), in particular a transfer film, having a replication lacquer layer and a metallic layer which is arranged on the replication lacquer layer and which has a plurality of microscopically fine pattern regions (14m) and a background region (14d) completely surrounding each of the pattern regions (14m), wherein the pattern regions (14m) are arranged in a raster (14r) of the raster width D and the pattern regions are respectively arranged separated from each other at a spacing B by the background region. Also described is a process for the production of such a multi-layer body.Type: GrantFiled: August 9, 2006Date of Patent: December 9, 2014Assignee: Leonhard Kurz Stiftung & Co. KGInventors: Rene Staub, Walter Kurz
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Patent number: 8822138Abstract: There is provided a resist underlayer film having both heat resistance and etching selectivity. A composition for forming a resist underlayer film for lithography, comprising a reaction product (C) of an alicyclic epoxy polymer (A) with a condensed-ring aromatic carboxylic acid and monocyclic aromatic carboxylic acid (B). The alicyclic epoxy polymer (A) may include a repeating structural unit of Formula (1): (T is a repeating unit structure containing an alicyclic ring in the polymer main chain; and E is an epoxy group or an organic group containing an epoxy group). The condensed-ring aromatic carboxylic acid and monocyclic aromatic carboxylic acid (B) may include a condensed-ring aromatic carboxylic acid (B1) and a monocyclic aromatic carboxylic acid (B2) in a molar ratio of B1:B2=3:7 to 7:3. The condensed-ring aromatic carboxylic acid (B1) may be 9-anthracenecarboxylic acid and the monocyclic aromatic carboxylic acid (B2) may be benzoic acid.Type: GrantFiled: August 11, 2010Date of Patent: September 2, 2014Assignee: Nissan Chemical Industries, Ltd.Inventors: Tetsuya Shinjo, Hirokazu Nishimaki, Yasushi Sakaida, Keisuke Hashimoto
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Patent number: 8778573Abstract: The present invention provides a manufacturing method of transparent electrode and mask thereof. The method includes: forming a film on a glass substrate, and coating photo-resist on film; irradiating photo-resist through mask, wherein the mask at corresponding active area of liquid crystal panel forming, from outer area to inner area, at least a first area and a second area, gap of pattern corresponding to transparent electrode in first area being first gap, gap of pattern in second area being second gap, first gap being greater than corresponding default gap, difference between first gap and corresponding default gap being greater than difference between second gap and corresponding default gap: and performing photolithography and etching processes on substrate after exposure to form transparent electrodes on substrate. As such, the present invention can reduce gap errors of formed transparent electrodes in entire active area to improve display effect.Type: GrantFiled: October 9, 2012Date of Patent: July 15, 2014Assignee: Shenzhen China Star Optoelectronics Technology co., Ltd.Inventors: Cheng-hung Chen, Zui Wang
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PRINTED CIRCUIT BOARD HAVING COPPER PLATED LAYER WITH ROUGHNESS AND METHOD OF MANUFACTURING THE SAME
Publication number: 20140186651Abstract: Disclosed herein are a printed circuit board having a copper plated layer with an anchor shaped surface and roughness by forming the copper plated layer having an anisotropic crystalline orientation structure using a plating inhibitor at the time of forming the copper plated layer serving as a circuit wiring and using composite gas plasma and a dilute acid solution, and a method of manufacturing the same.Type: ApplicationFiled: December 24, 2013Publication date: July 3, 2014Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Sung Han, Yoon Su Kim, Doo Sung Jung, Eun Jung Lim, Kyoung Moo Harr, Kyung Suk Shim, Kyung Seob Oh -
Patent number: 8758984Abstract: A method of forming gate conductor structures. A substrate having thereon a gate electrode layer is provided. A multi-layer hard mask is formed overlying the gate electrode layer. The multi-layer hard mask comprises a first hard mask, a second hard mask, and a third hard mask. A photoresist pattern is formed on the multi-layer hard mask. A first etching process is performed to etch the third hard mask, using the photoresist pattern as a first etch resist, thereby forming a patterned third hard mask. A second etching process is performed to etch the second hard mask and the first hard mask, using the patterned third hard mask as a second etch resist, thereby forming a patterned first hard mask. A third etching process is performed to etch a layer of the gate electrode layer, using the patterned first hard mask as a third etch resist.Type: GrantFiled: May 9, 2011Date of Patent: June 24, 2014Assignee: Nanya Technology Corp.Inventors: Chang-Ming Wu, Yi-Nan Chen, Hsien-Wen Liu
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Publication number: 20140160373Abstract: A capacitive touch panel includes at least one first conductive series extending along a first direction and at least one second conductive series extending along a second direction on a substrate. The first conductive series includes a plurality of first electrodes disposed along the first direction and a plurality of first connecting electrodes respectively disposed between two adjacent first electrodes. The second conductive series includes a plurality of second electrodes disposed along the second direction and a plurality of second connecting electrodes respectively disposed between two adjacent second electrodes. The first direction intersects the second direction. At least one kind of elements of the first electrodes, the first connecting electrodes, the second electrodes, and the second connecting electrodes are formed from a metal mash layer, and the first conductive series and the second conductive series are electrically isolated from each other.Type: ApplicationFiled: December 6, 2013Publication date: June 12, 2014Applicant: WINTEK CORPORATIONInventors: Chang-Hsuan Hsu, Wen-Chun Wang, Cheng-Yi Chou, Chong-Wei Li, Ching-Fu Hsu, Chih-Yuan Wang
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Patent number: 8715913Abstract: The present invention is a silicon-containing resist underlayer film-forming composition containing at least any one of a condensation product and a hydrolysis condensation product or both of a mixture comprising: one or more kinds of a compound (A) selected from the group consisting of an organic boron compound shown by the following general formula (1) and a condensation product thereof and one or more kinds of a silicon compound (B) shown by the following general formula (2). Thereby, there can be provided a resist underlayer film applicable not only to the resist pattern formed of a hydrophilic organic compound obtained by the negative development but also to the resist pattern formed of a hydrophobic compound obtained by the conventional positive development.Type: GrantFiled: November 5, 2012Date of Patent: May 6, 2014Assignee: Shin-Etsu Chemical Co., Ltd.Inventors: Tsutomu Ogihara, Takafumi Ueda, Fujio Yagihashi
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Publication number: 20140113386Abstract: Embodiments of the disclosure are directed to a device for molecule sensing. In some embodiments, the device includes a first electrode separated from a second electrode by a dielectric layer. The first electrode comprises a large area electrode and the second electrode comprises a small area electrode. At least one opening (e.g., trench) cut or otherwise created into the dielectric layer exposes a tunnel junction therebetween whereby target molecules in solution can bind across the tunnel junction.Type: ApplicationFiled: October 10, 2013Publication date: April 24, 2014Applicant: ARIZONA BOARD OF REGENTS, acting for and on behalf of ARIZONA STATE UNIVERSITYInventors: Brett Gyarfas, Stuart Lindsay, Pei Pang
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Patent number: 8697345Abstract: A photoresist stripping solution comprising (a) a specified quaternary ammonium hydroxide, such as tetrabutylammonium hydroxide, tetrapropylammonium hydroxide, methyltributylammonium hydroxide or methyltripropylammonium hydroxide, (b) a water-soluble amine, (c) water, (d) a corrosion inhibitor and (e) a water-soluble organic solvent, the compounding ratio of component (a) to component (b) being in the range of from 1:3 to 1:10 by mass, as well as a method of stripping photoresists using the solution. The stripping solution of the invention assures effective protection of Al, Cu and other wiring metal conductors against corroding as well as efficient stripping of the photoresist film, post-ashing residues such as modified photoresist film and metal depositions. It also assures efficient stripping of Si-based residues and effective protection of the substrate (particularly the reverse side of a Si substrate) from corroding.Type: GrantFiled: April 1, 2010Date of Patent: April 15, 2014Assignee: Tokyo Ohka Kogyo Co., Ltd.Inventors: Kazumasa Wakiya, Shigeru Yokoi
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Patent number: 8652750Abstract: A silicon-containing film is formed from a heat curable composition comprising (A) a silicon-containing compound obtained through hydrolytic condensation of a hydrolyzable silicon compound in the presence of an acid catalyst, (B) a hydroxide or organic acid salt of Li, Na, K, Rb or Ce, or a sulfonium, iodonium or ammonium compound, (C) an organic acid, (D) a cyclic ether-substituted alcohol, and (E) an organic solvent. The silicon-containing film ensures effective pattern formation, effective transfer of a photoresist pattern, and accurate processing of a substrate.Type: GrantFiled: June 27, 2008Date of Patent: February 18, 2014Assignee: Shin-Etsu Chemical Co., Ltd.Inventors: Tsutomu Ogihara, Toshiharu Yano, Koji Hasegawa
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Patent number: 8603732Abstract: There is disclosed a resist underlayer film-forming composition comprising, at least: a resin (A) obtained by condensing a compound represented by the following general formula (1) with a compound represented by the following general formula (2) by the aid of an acid catalyst; a compound (B) represented by the general formula (1); a fullerene compound (C); and an organic solvent. There can be a resist underlayer film composition in a multi-layer resist film to be used in lithography, which underlayer film is excellent in property for filling up a height difference of a substrate, possesses a solvent resistance, and is not only capable of preventing occurrence of twisting during etching of a substrate, but also capable of providing an excellently decreased pattern roughness; a process for forming a resist underlayer film by using the composition; and a patterning process.Type: GrantFiled: December 27, 2010Date of Patent: December 10, 2013Assignee: Shin-Etsu Chemical Co., Ltd.Inventors: Tsutomu Ogihara, Takeru Watanabe, Takeshi Kinsho, Katsuya Takemura, Toshihiko Fujii, Daisuke Kori
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Patent number: 8563225Abstract: A method of forming a hard mask in a semiconductor device which is self-aligned with a MTJ formed in the device is provided. The method includes the steps of: forming a hard mask material layer on an upper surface of a magnetic stack in the MTJ; forming an anti-reflective coating (ARC) layer on at least a portion of an upper surface of the hard mask material layer, the ARC layer being selected to be removable by a wet etch; forming a photoresist layer on at least a portion of an upper surface of the ARC layer; removing at least a portion of the photoresist layer and the ARC layer to thereby expose at least a portion of the hard mask material layer; etching the hard mask material layer to remove the exposed portion of the hard mask material layer; and performing a wet strip to remove remaining portions of the ARC layer and photoresist layer in a same processing step without interference to the magnetic stack.Type: GrantFiled: May 23, 2008Date of Patent: October 22, 2013Assignee: International Business Machines CorporationInventors: Solomon Assefa, Sivananda K. Kanakasabapathy
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Patent number: 8563227Abstract: The present disclosure provides a method of making a mask. The method includes providing a substrate having a first attenuating layer on the substrate and a first imaging layer on the first attenuating layer; performing a first exposure to the first imaging layer using a first radiation energy in writing mode; performing a first etching to the first attenuating layer; performing a second etching to the substrate; forming a second imaging layer on the first attenuating layer and the substrate; performing a second exposure to the second imaging layer using a light energy and another mask; and performing a third etching to the first attenuating layer after the second exposure.Type: GrantFiled: October 15, 2012Date of Patent: October 22, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Ming Chen, Ya-Ping Tseng, Ming-Tao Ho
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Patent number: 8450048Abstract: There is disclosed a method for forming a resist underlayer film of a multilayer resist film having at least three layers used in a lithography, comprising at least; a step of coating a composition for resist underlayer film containing a novolak resin represented by the following general formula (1) obtained by treating a compound having a bisnaphthol group on a substrate; and a step of curing the coated composition for the resist underlayer film by a heat treatment at a temperature above 300° C. and 600° C. or lower for 10 to 600 seconds. There can be provided a method for forming a resist underlayer film, and a patterning process using the method to form a resist underlayer film in a multilayer resist film having at least three layers used in a lithography, gives a resist underlayer film having a lowered reflectance, a high etching resistance, and a high heat and solvent resistances, especially without wiggling during substrate etching.Type: GrantFiled: September 14, 2009Date of Patent: May 28, 2013Assignee: Shin-Etsu Chemical Co., Ltd.Inventors: Jun Hatakeyama, Toshihiko Fujii, Tsutomu Ogihara
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Patent number: 8435724Abstract: In a fabricating method of a touch screen panel, a conductive layer and an insulating layer are sequentially formed on a same surface of a transparent substrate. The conductive layer and the insulating layer are co-patterned using a halftone mask to form first connection patterns having separated patterns and the insulating layer being patterned on the first connection patterns to expose regions of the first connection patterns. A transparent electrode layer is formed on the transparent substrate having the first connection patterns and the insulating layer. The transparent electrode layer is patterned to form first sensing patterns connected to the first connection patterns through the exposed regions of the first connection patterns and connected along a first direction, and to form second sensing patterns disposed between the first sensing patterns, wherein the second sensing patterns are insulated from the first sensing patterns and connected along a second direction.Type: GrantFiled: December 1, 2010Date of Patent: May 7, 2013Assignee: Samsung Display Co., Ltd.Inventors: Woo-Sik Jun, Do-Youb Kim, Ung-Soo Lee
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Patent number: 8377631Abstract: Molecular glass based planarizing compositions for lithographic processing are disclosed. The processes generally include casting the planarizing composition onto a surface comprised of lithographic features, the planarizing composition comprising at least one molecular glass and at least one solvent; and heating the planarizing composition to a temperature greater than a glass transition temperature of the at least one molecular glass. Exemplary molecular glasses include polyhedral oligomeric silsesquioxane derivatives, calixarenes, cyclodextrin derivatives, and other non-polymeric large molecules.Type: GrantFiled: October 6, 2009Date of Patent: February 19, 2013Assignee: International Business Machines CorporationInventors: Robert D. Allen, Mark W. Hart, Ratnam Sooriyakumaran
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Patent number: 8361337Abstract: Nanopatterned substrates can be prepared by a method that includes forming a block copolymer film on a substrate, annealing the block copolymer film, surface reconstructing the annealed block copolymer film, coating an etch-resistant layer on the surface reconstructed block copolymer film, etching the resist-coated block copolymer film to create an etched article comprising a nanopatterned substrate, and separating the etch-resistant layer and the block copolymer film from the nanopatterned substrate. The method is applicable to a wide variety of substrate materials, avoids any requirement for complicated procedures to produce long-range order in the block copolymer film, and avoids any requirement for metal functionalization of the block copolymer.Type: GrantFiled: March 17, 2008Date of Patent: January 29, 2013Assignee: The University of MassachusettsInventors: Soojin Park, Thomas P. Russell, Jia-Yu Wang, Bokyung Kim
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Patent number: 8288074Abstract: There is herein described a method and apparatus for photoimaging. In particular, there is described a method and apparatus for photoimaging a substrate covered with a wet curable photopolymer, wherein the photoimaged substrate is used to form images such as electrical circuits.Type: GrantFiled: July 8, 2009Date of Patent: October 16, 2012Assignee: Rainbow Technology Systems LimitedInventors: Sheila Hamilton, Charles Jonathan Kennett
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Patent number: 8288082Abstract: Example embodiments provide a method of fabricating a triode-structure field-emission device. A cathode, an insulating layer, and a gate metal layer may be sequentially formed on a substrate. A first resist pattern having a first opening and a second resist pattern having a second opening smaller than the first opening may be formed to be sequentially laminated on the gate metal layer. Then, the gate metal layer and the insulating layer may be etched using the first resist pattern to form a gate electrode and an insulating layer having a first hole and a second hole corresponding to the first opening. A catalyst layer may be formed on the cathode exposed through the first and second holes using the second resist pattern. After the first resist pattern, second resist pattern, and the catalyst layer on the second resist pattern are removed, an emitter may be formed on the catalyst layer in the second hole.Type: GrantFiled: November 10, 2008Date of Patent: October 16, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Chan Wook Baik, Junhee Choi, Seog Woo Hong, Joo Ho Lee
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Patent number: 8288081Abstract: The present disclosure provides a method of making a mask. The method includes providing a substrate having a first attenuating layer on the substrate and a first imaging layer on the first attenuating layer; performing a first exposure to the first imaging layer using a first radiation energy in writing mode; performing a first etching to the first attenuating layer; performing a second etching to the substrate; forming a second imaging layer on the first attenuating layer and the substrate; performing a second exposure to the second imaging layer using a light energy and another mask; and performing a third etching to the first attenuating layer after the second exposure.Type: GrantFiled: April 2, 2007Date of Patent: October 16, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Ming Chen, Ya-Ping Tseng, Ming-Tao Ho
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Patent number: 8273519Abstract: A hardmask composition includes a solvent and an organosilicon copolymer. The organosilicon copolymer may be represented by Formula A: (SiO1.5—Y—SiO1.5)x(R3SiO1.5)y??(A) wherein x and y may satisfy the following relations: x is about 0.05 to about 0.9, y is about 0.05 to about 0.9, and x+y=1, R3 may be a C1-C12 alkyl group, and Y may be a linking group including a substituted or unsubstituted, linear or branched C1-C20 alkyl group, a C1-C20 group containing a chain that includes an aromatic ring, a heterocyclic ring, a urea group or an isocyanurate group, or a C2-C20 group containing one or more multiple bonds.Type: GrantFiled: November 21, 2007Date of Patent: September 25, 2012Assignee: Cheil Industries, Inc.Inventors: Mi Young Kim, Sang Kyun Kim, Sang Hak Lim, Sang Ran Koh, Hui Chan Yun, Do Hyeon Kim, Dong Seon Uh, Jong Seob Kim
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Patent number: 8257908Abstract: [Object] To provide a coating-type underlayer coating forming composition that is applied for multi-ply coating process by thin film resist in order to prevent collapse of resist pattern after development with miniaturization of resist pattern, and that shows a sufficient etching resistance against a semiconductor substrate to be processed on processing of the substrate by having a low dry etching rate compared with the photoresist and substrate. [Means for solving problems] A coating-type underlayer coating forming composition that is used for lithography process by multi-ply coating, comprising a polymer containing a vinylnaphthalene based structural unit and an acrylic acid based structural unit containing an aromatic hydroxy group or a hydroxy-containing ester. A coating-type underlayer coating forming composition further comprising an acrylic acid based structural unit containing an aliphatic cyclic compound-containing ester or an aromatic compound-containing ester.Type: GrantFiled: August 15, 2006Date of Patent: September 4, 2012Assignee: Nissan Chemical Industries, Ltd.Inventors: Takahiro Sakaguchi, Tomoyuki Enomoto
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Patent number: 8257905Abstract: A method of fabricating a thin film transistor substrate and a negative photoresist composition used therein are provided, which can reduce pattern inferiority. The method of fabricating a thin film transistor substrate includes forming a conductive film composed of a conductive material on a substrate, forming an etch pattern composed of a negative photoresist composition on the conductive film, and forming a conductive pattern by etching the conductive film using the etch pattern as an etching mask, wherein the negative photoresist composition includes 10-50 parts by weight of novolak resin including a hydroxyl group that is soluble in an alkali developing solution, 0.5-10 parts by weight of a first photo acid generator represented by the following formula (1), 0.Type: GrantFiled: January 11, 2010Date of Patent: September 4, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Yeong-Beom Lee, Hi-Kuk Lee, Byung-Uk Kim, Hyoc-Min Youn, Ki-Hyuk Koo
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Patent number: 8241837Abstract: Provided are a mask pattern including a silicon-containing self-assembled molecular layer, a method of forming the same, and a method of fabricating a semiconductor device. The mask pattern includes a resist pattern formed on a semiconductor substrate and the self-assembled molecular layer formed on the resist pattern. The self-assembled molecular layer has a silica network formed by a sol-gel reaction. To form the mask pattern, first, the resist pattern is formed with openings on an underlayer covering the substrate to expose the underlayer to a first width. Then, the self-assembled molecular layer is selectively formed only on a surface of the resist pattern to expose the underlayer to a second width smaller than the first width. The underlayer is etched by using the resist pattern and the self-assembled molecular layer as an etching mask to obtain a fine pattern.Type: GrantFiled: November 16, 2010Date of Patent: August 14, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Hwan Hah, Jin Hong, Hyun-Woo Kim, Hata Mitsuhiro, Kolake Mayya Subramanya, Sang-Gyun Woo
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Publication number: 20120186862Abstract: The present invention relates to a method for manufacturing a TAB tap. The method includes forming a circuit pattern region having input/output terminal pattern on a base film, and forming an exposing region at a convey region having a sprocket hole for exposing the base film. Accordingly, the present invention provides a TAB tape that improves reliability of a product by fundamentally preventing the generation of metal particles by forming exposing regions that expose a base film through selectively etching and removing a metal layer of a convey region formed at both side of a TAB tape and having a sprocket hole, and that prevents short-circuit by partially removing a base film at a predetermined region not having a circuit pattern formed thereon through etching.Type: ApplicationFiled: July 22, 2011Publication date: July 26, 2012Applicant: LG Innotek Co., Ltd.Inventors: Tae Ki Hong, Han Mo Koo, Jun Young Lim, Ki Tae Park, Sang Ki Cho, Dae Sung Yoo
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Patent number: RE45841Abstract: A thin-film transistor includes a substrate, and a gate including a double-layered structure having first and second metal layers provided on the substrate, the first metal layer being wider than the second metal layer by 1 to 4 ?m. A method of making such a thin-film transistor includes the steps of: depositing a first metal layer on a substrate, depositing a second metal layers directly on the first metal layer; forming a photoresist having a designated width on the second metal layer; patterning the second metal layer via isotropic etching using the photoresist as a mask; patterning the first metal layer by means of an anisotropic etching using the photoresist as a mask, the first metal layer being etched to have the designated width, thus forming a gate having a laminated structure of the first and second metal layers; and removing the photoresist.Type: GrantFiled: October 5, 2012Date of Patent: January 12, 2016Assignee: LG DISPLAY CO., LTD.Inventors: Byung-Chul Ahn, Hyun-Sik Seo