Metal Etched Patents (Class 430/318)
  • Patent number: 10451777
    Abstract: The present disclosure relates to the technical field of metal surface plasma and light emitting display, and provides an optical component for controlling a light emergent direction and a manufacturing method thereof. An optical component for controlling a light emergent direction includes: a transparent substrate; a plurality of metal film strips arranged in parallel at equal pitches on the surface of the transparent substrate along a first direction and extending in a second direction that is perpendicular to the first direction; and dielectric gratings formed respectively on the plurality of metal film strips, wherein slits of the dielectric gratings extend along the second direction.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: October 22, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Jinghai Liu
  • Patent number: 9820386
    Abstract: A method of forming an electronic assembly. The method includes covering a patterned conductive layer that is on a dielectric layer with a solder resist; depositing a metal layer on to the solder resist; depositing a photo resist onto the metal layer; patterning the photo resist; etching the metal layer that is exposed from the photo resist to form a metal mask; removing the photo resist; and plasma etching the solder resist that is exposed from the metal mask. An electronic assembly for securing for an electronic card. The electronic assembly includes a patterned conductive layer that is on a dielectric layer; and a solder resist covering the patterned conductive layer and the dielectric layer, wherein the solder resist includes openings that expose the patterned conductive layer, wherein the openings in the solder resist only have organic material on side walls of the respective openings.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: November 14, 2017
    Assignee: Intel Corporation
    Inventors: Kristof Darmawikarta, Rahul Jain, Robert Alan May, Sheng Li, Sri Ranga Sai Boyapati
  • Patent number: 9686867
    Abstract: Methods to systematize the development of machines using inexpensive, fast, and convenient fabrication processes are disclosed. In an embodiment, a folding pattern and corresponding circuit design can provide the blueprints for fabrication. The folding pattern may be provided (e.g. laser machined) on a flat sheet of substrate material, such as a polymer. The circuit pattern may be generated by etching or applying (e.g. sputtering) a copper foil layer onto the substrate. Circuit components and actuators may then be added at specified locations. The flat substrate may then be folded along the predefined locations to form the final machine. The machine may operate autonomously to perform a task.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: June 20, 2017
    Assignees: Massachussetts Institute of Technology, President and Fellows of Harvard College
    Inventors: Daniela Rus, Robert J. Wood, Cagdas Denizel Onal, Michael Tolley
  • Patent number: 9666609
    Abstract: This disclosure relates to an array substrate wiring and manufacturing and repairing method thereof. The array substrate wiring comprises a first wiring formed on the substrate for transmitting electric signals; an insulating layer formed on the first wiring; a second wiring formed on the insulating layer, being opposite to the first wiring, the second wiring being in a hanging state and not transmitting electric signals. By means of such a double layer wiring structure, the holes produced in the insulating layer are blocked using the second wiring in the upper layer, such that the outside moisture cannot reach the first wiring via the holes in the insulating layer, thereby protecting the first wiring for transmitting electric signals from corrosion and scratch.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: May 30, 2017
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Chao Liu, Yujun Zhang, Zengsheng He, Lei Chen
  • Patent number: 9404188
    Abstract: This invention relates to novel corrosion inhibitors which are capable of sequestering metal ions such as calcium and magnesium and are derived in part from renewable carbohydrate feedstocks. The corrosion inhibitors are mixtures containing one or more hydroxycarboxylic acid salts and one or more suitable oxoacid anion salts.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: August 2, 2016
    Assignee: Rivertop Renewables
    Inventors: Tyler N. Smith, Donald E. Kiely, Kylie Kramer-Presta
  • Patent number: 9337033
    Abstract: A process for patterning a hard mask material with line-space patterns below a 30 nm pitch and a 15 nm critical dimension by employing a spin-on titanium-silicon (TiSi) polymer or oligomer as a tone inversion material is provided. The spin-on TiSi material is spin-coated over a patterned OPL that includes a first pattern generated from a DSA based process. The spin-on TiSi material fill trenches within the patterned OPL to form a tone inverted pattern by removing the patterned OPL selective to the spin-on TiSi material. The inverted pattern is a complementary pattern to the first pattern, and is transferred into the underlying hard mask material by an anisotropic etch.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: May 10, 2016
    Assignee: International Business Machines Corporation
    Inventors: Martin Glodde, Wu-Song Huang, Hiroyuki Miyazoe, Ratnam Sooriyakumaran, Hsinyu Tsai
  • Patent number: 9293319
    Abstract: Methods of removing metal from a portion of a substrate are useful in integrated circuit fabrication. Methods include exposing the substrate to an oxidizing environment comprising at least one oxidizing agent and at least one reducing agent, and exposing the substrate to a reducing environment comprising at least one reducing agent and at least one oxidizing agent.
    Type: Grant
    Filed: March 9, 2011
    Date of Patent: March 22, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Brian Dolan, Robert J. Hanson, Chan Lim
  • Patent number: 9274432
    Abstract: A method for isolating microstructural regions or features on a surface for electrochemical experimentation comprising polishing a metal sample, coating the metal sample with a photoresist, selecting a region of interest of the metal sample, exposing the region of interest with light energy, developing the exposed photoresist and creating a developed region.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 1, 2016
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Farrel Martin, Alberto Píqué, Raymond C Y Auyeung, Steve Policastro
  • Patent number: 9253890
    Abstract: Provided is a patterned conductive film may include a conductive interconnected nano-structure film. The conductive interconnected nano-structure film may include a first region and a second region adjacent to the first region. A conductivity of the first region may be at least 1000 times a conductivity of the second region.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: February 2, 2016
    Assignee: Industrial Technology Research Institute
    Inventors: Yu-Pei Chang, Ming-Huan Yang, Chun-Yi Chiu
  • Patent number: 9150969
    Abstract: In a method of etching a metal layer of an object to be processed, the metal layer is etched by ion sputtering etching while forming a protective film containing carbon on a surface of a mask of the object. The object is exposed to an oxygen plasma after etching the metal layer. The object is exposed to hexafluoroacetylacetone after exposing the object to the oxygen plasma.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: October 6, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Eiichi Nishimura, Fumiko Yamashita, Koyumi Sasa
  • Patent number: 9040227
    Abstract: A microstructure manufacturing method includes forming a layer of a photosensitive resin on a substrate surface having an electrical conductivity, forming a structure of the photosensitive resin by exposing the layer of the photosensitive resin to light and developing the layer of the photosensitive resin to expose a part of the substrate surface, forming a first plated layer on the exposed part of the substrate surface by soaking the structure of the photosensitive resin in a first plating solution, curing the structure of the photosensitive resin after forming the first plated layer, removing at least part of the first plated layer after curing the structure of the photosensitive resin, and forming a second plated layer on a part where the first plated layer is removed, by soaking the structure of the photosensitive resin in a second plating solution different from the first plating solution.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: May 26, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takayuki Teshima, Yutaka Setomoto
  • Patent number: 8951425
    Abstract: A method of forming at least one curved plate having first and second layers, the first layer being formed of a first material and the second layer being formed of a second material, the method including forming one or more blocks of a fusible material on a surface of a substrate; baking the one or more blocks to deform their shape; and depositing the first and second materials over the one or more deformed blocks to form the first and second layers.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: February 10, 2015
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Stéphane Monfray, Thomas Skotnicki, Onoriu Puscasu, Christophe Maitre
  • Patent number: 8945820
    Abstract: The present invention is a silicon-containing resist underlayer film-forming composition containing a condensation product and/or a hydrolysis condensation product of a mixture comprising: one or more kinds of a compound (A) selected from the group consisting of an organic boron compound shown by the general formula (1) and a condensation product thereof and one or more kinds of a silicon compound (B) shown by the general formula (2). Thereby, there can be provided a silicon-containing resist underlayer film-forming composition being capable of forming a pattern having a good adhesion, forming a silicon-containing film which can be used as a dry-etching mask between a photoresist film which is the upperlayer film of the silicon-containing film and an organic film which is the underlayer film thereof, and suppressing deformation of the upperlayer resist during the time of dry etching of the silicon-containing film; and a patterning process.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: February 3, 2015
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Tsutomu Ogihara, Takafumi Ueda, Yoshinori Taneda
  • Patent number: 8927189
    Abstract: A photoresist composition including a binder resin including a novolac resin represented by Chemical Formula 1, a diazide photosensitive initiator, and a solvent including a base solvent and an auxiliary solvent, wherein the base solvent includes propylene glycol monomethyl ether acetate, and the auxiliary solvent includes dimethyl-2-methylglutarate and ethyl beta-ethoxypropionate, wherein in Chemical Formula 1, R1 to R9 are each independently a hydrogen atom or an alkyl group, “a” is an integer number from 0 through 10, “b” is an integer number from 0 through 100, and “c” is an integer number from 1 through 10.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: January 6, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Gwui-Hyun Park, Pil Soon Hong, Jinho Ju, Taegyun Kim, Jin-Su Byun, Dong Min Kim, Seung Ki Kim, Doo Youn Lee
  • Publication number: 20140377690
    Abstract: A manufacturing method of a mask plate and an array substrate is provided. The mask plate is for manufacturing fanout leads in a non-effective display area on an array substrate. The mask plate includes a fanout lead pattern having a plurality of fanout impression lines, wherein each fanout impression line has a predetermined line width, and each of some of the fanout impression lines has at least one curve portion, wherein for one fanout impression line, a line width of the at least one curve portion is smaller than the predetermined line width of the fanout impression line. A manufacturing method of an array substrate utilizes the foregoing mask plate to manufacture the array substrate.
    Type: Application
    Filed: July 1, 2013
    Publication date: December 25, 2014
    Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventor: Hua Zheng
  • Patent number: 8911932
    Abstract: Disclosed are the deactivation mechanism and chemistry platforms that make high-silicon hardmask films photo-imageable like positive-tone photoresist for microphotolithography. The deactivation mechanism requires a catalyst to promote crosslinking reactions, and a photoacid generator to deactivate the catalyst. The initial hardmask films are soluble in developers. If not radiated, films become insoluble in developers due to crosslinking reactions promoted by catalyst. If radiated, films remain soluble in developers due to deactivation of catalyst by photoacid generator. Compositions of positive-tone photo-imageable hardmask based on the chemistry of polysiloxane and polysilsesquioxanes are disclosed as well. Also disclosed is a method of modifying polysiloxane and polysilsesquioxane films for controlled diffusion of catalysts, photoacid generators, and quenchers.
    Type: Grant
    Filed: April 12, 2010
    Date of Patent: December 16, 2014
    Inventor: Sam Xunyun Sun
  • Patent number: 8906491
    Abstract: Described is a multi-layer body (1), in particular a transfer film, having a replication lacquer layer and a metallic layer which is arranged on the replication lacquer layer and which has a plurality of microscopically fine pattern regions (14m) and a background region (14d) completely surrounding each of the pattern regions (14m), wherein the pattern regions (14m) are arranged in a raster (14r) of the raster width D and the pattern regions are respectively arranged separated from each other at a spacing B by the background region. Also described is a process for the production of such a multi-layer body.
    Type: Grant
    Filed: August 9, 2006
    Date of Patent: December 9, 2014
    Assignee: Leonhard Kurz Stiftung & Co. KG
    Inventors: Rene Staub, Walter Kurz
  • Patent number: 8822138
    Abstract: There is provided a resist underlayer film having both heat resistance and etching selectivity. A composition for forming a resist underlayer film for lithography, comprising a reaction product (C) of an alicyclic epoxy polymer (A) with a condensed-ring aromatic carboxylic acid and monocyclic aromatic carboxylic acid (B). The alicyclic epoxy polymer (A) may include a repeating structural unit of Formula (1): (T is a repeating unit structure containing an alicyclic ring in the polymer main chain; and E is an epoxy group or an organic group containing an epoxy group). The condensed-ring aromatic carboxylic acid and monocyclic aromatic carboxylic acid (B) may include a condensed-ring aromatic carboxylic acid (B1) and a monocyclic aromatic carboxylic acid (B2) in a molar ratio of B1:B2=3:7 to 7:3. The condensed-ring aromatic carboxylic acid (B1) may be 9-anthracenecarboxylic acid and the monocyclic aromatic carboxylic acid (B2) may be benzoic acid.
    Type: Grant
    Filed: August 11, 2010
    Date of Patent: September 2, 2014
    Assignee: Nissan Chemical Industries, Ltd.
    Inventors: Tetsuya Shinjo, Hirokazu Nishimaki, Yasushi Sakaida, Keisuke Hashimoto
  • Patent number: 8778573
    Abstract: The present invention provides a manufacturing method of transparent electrode and mask thereof. The method includes: forming a film on a glass substrate, and coating photo-resist on film; irradiating photo-resist through mask, wherein the mask at corresponding active area of liquid crystal panel forming, from outer area to inner area, at least a first area and a second area, gap of pattern corresponding to transparent electrode in first area being first gap, gap of pattern in second area being second gap, first gap being greater than corresponding default gap, difference between first gap and corresponding default gap being greater than difference between second gap and corresponding default gap: and performing photolithography and etching processes on substrate after exposure to form transparent electrodes on substrate. As such, the present invention can reduce gap errors of formed transparent electrodes in entire active area to improve display effect.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: July 15, 2014
    Assignee: Shenzhen China Star Optoelectronics Technology co., Ltd.
    Inventors: Cheng-hung Chen, Zui Wang
  • Publication number: 20140186651
    Abstract: Disclosed herein are a printed circuit board having a copper plated layer with an anchor shaped surface and roughness by forming the copper plated layer having an anisotropic crystalline orientation structure using a plating inhibitor at the time of forming the copper plated layer serving as a circuit wiring and using composite gas plasma and a dilute acid solution, and a method of manufacturing the same.
    Type: Application
    Filed: December 24, 2013
    Publication date: July 3, 2014
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Sung Han, Yoon Su Kim, Doo Sung Jung, Eun Jung Lim, Kyoung Moo Harr, Kyung Suk Shim, Kyung Seob Oh
  • Patent number: 8758984
    Abstract: A method of forming gate conductor structures. A substrate having thereon a gate electrode layer is provided. A multi-layer hard mask is formed overlying the gate electrode layer. The multi-layer hard mask comprises a first hard mask, a second hard mask, and a third hard mask. A photoresist pattern is formed on the multi-layer hard mask. A first etching process is performed to etch the third hard mask, using the photoresist pattern as a first etch resist, thereby forming a patterned third hard mask. A second etching process is performed to etch the second hard mask and the first hard mask, using the patterned third hard mask as a second etch resist, thereby forming a patterned first hard mask. A third etching process is performed to etch a layer of the gate electrode layer, using the patterned first hard mask as a third etch resist.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: June 24, 2014
    Assignee: Nanya Technology Corp.
    Inventors: Chang-Ming Wu, Yi-Nan Chen, Hsien-Wen Liu
  • Publication number: 20140160373
    Abstract: A capacitive touch panel includes at least one first conductive series extending along a first direction and at least one second conductive series extending along a second direction on a substrate. The first conductive series includes a plurality of first electrodes disposed along the first direction and a plurality of first connecting electrodes respectively disposed between two adjacent first electrodes. The second conductive series includes a plurality of second electrodes disposed along the second direction and a plurality of second connecting electrodes respectively disposed between two adjacent second electrodes. The first direction intersects the second direction. At least one kind of elements of the first electrodes, the first connecting electrodes, the second electrodes, and the second connecting electrodes are formed from a metal mash layer, and the first conductive series and the second conductive series are electrically isolated from each other.
    Type: Application
    Filed: December 6, 2013
    Publication date: June 12, 2014
    Applicant: WINTEK CORPORATION
    Inventors: Chang-Hsuan Hsu, Wen-Chun Wang, Cheng-Yi Chou, Chong-Wei Li, Ching-Fu Hsu, Chih-Yuan Wang
  • Patent number: 8715913
    Abstract: The present invention is a silicon-containing resist underlayer film-forming composition containing at least any one of a condensation product and a hydrolysis condensation product or both of a mixture comprising: one or more kinds of a compound (A) selected from the group consisting of an organic boron compound shown by the following general formula (1) and a condensation product thereof and one or more kinds of a silicon compound (B) shown by the following general formula (2). Thereby, there can be provided a resist underlayer film applicable not only to the resist pattern formed of a hydrophilic organic compound obtained by the negative development but also to the resist pattern formed of a hydrophobic compound obtained by the conventional positive development.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: May 6, 2014
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Tsutomu Ogihara, Takafumi Ueda, Fujio Yagihashi
  • Publication number: 20140113386
    Abstract: Embodiments of the disclosure are directed to a device for molecule sensing. In some embodiments, the device includes a first electrode separated from a second electrode by a dielectric layer. The first electrode comprises a large area electrode and the second electrode comprises a small area electrode. At least one opening (e.g., trench) cut or otherwise created into the dielectric layer exposes a tunnel junction therebetween whereby target molecules in solution can bind across the tunnel junction.
    Type: Application
    Filed: October 10, 2013
    Publication date: April 24, 2014
    Applicant: ARIZONA BOARD OF REGENTS, acting for and on behalf of ARIZONA STATE UNIVERSITY
    Inventors: Brett Gyarfas, Stuart Lindsay, Pei Pang
  • Patent number: 8697345
    Abstract: A photoresist stripping solution comprising (a) a specified quaternary ammonium hydroxide, such as tetrabutylammonium hydroxide, tetrapropylammonium hydroxide, methyltributylammonium hydroxide or methyltripropylammonium hydroxide, (b) a water-soluble amine, (c) water, (d) a corrosion inhibitor and (e) a water-soluble organic solvent, the compounding ratio of component (a) to component (b) being in the range of from 1:3 to 1:10 by mass, as well as a method of stripping photoresists using the solution. The stripping solution of the invention assures effective protection of Al, Cu and other wiring metal conductors against corroding as well as efficient stripping of the photoresist film, post-ashing residues such as modified photoresist film and metal depositions. It also assures efficient stripping of Si-based residues and effective protection of the substrate (particularly the reverse side of a Si substrate) from corroding.
    Type: Grant
    Filed: April 1, 2010
    Date of Patent: April 15, 2014
    Assignee: Tokyo Ohka Kogyo Co., Ltd.
    Inventors: Kazumasa Wakiya, Shigeru Yokoi
  • Patent number: 8652750
    Abstract: A silicon-containing film is formed from a heat curable composition comprising (A) a silicon-containing compound obtained through hydrolytic condensation of a hydrolyzable silicon compound in the presence of an acid catalyst, (B) a hydroxide or organic acid salt of Li, Na, K, Rb or Ce, or a sulfonium, iodonium or ammonium compound, (C) an organic acid, (D) a cyclic ether-substituted alcohol, and (E) an organic solvent. The silicon-containing film ensures effective pattern formation, effective transfer of a photoresist pattern, and accurate processing of a substrate.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: February 18, 2014
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Tsutomu Ogihara, Toshiharu Yano, Koji Hasegawa
  • Patent number: 8603732
    Abstract: There is disclosed a resist underlayer film-forming composition comprising, at least: a resin (A) obtained by condensing a compound represented by the following general formula (1) with a compound represented by the following general formula (2) by the aid of an acid catalyst; a compound (B) represented by the general formula (1); a fullerene compound (C); and an organic solvent. There can be a resist underlayer film composition in a multi-layer resist film to be used in lithography, which underlayer film is excellent in property for filling up a height difference of a substrate, possesses a solvent resistance, and is not only capable of preventing occurrence of twisting during etching of a substrate, but also capable of providing an excellently decreased pattern roughness; a process for forming a resist underlayer film by using the composition; and a patterning process.
    Type: Grant
    Filed: December 27, 2010
    Date of Patent: December 10, 2013
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Tsutomu Ogihara, Takeru Watanabe, Takeshi Kinsho, Katsuya Takemura, Toshihiko Fujii, Daisuke Kori
  • Patent number: 8563225
    Abstract: A method of forming a hard mask in a semiconductor device which is self-aligned with a MTJ formed in the device is provided. The method includes the steps of: forming a hard mask material layer on an upper surface of a magnetic stack in the MTJ; forming an anti-reflective coating (ARC) layer on at least a portion of an upper surface of the hard mask material layer, the ARC layer being selected to be removable by a wet etch; forming a photoresist layer on at least a portion of an upper surface of the ARC layer; removing at least a portion of the photoresist layer and the ARC layer to thereby expose at least a portion of the hard mask material layer; etching the hard mask material layer to remove the exposed portion of the hard mask material layer; and performing a wet strip to remove remaining portions of the ARC layer and photoresist layer in a same processing step without interference to the magnetic stack.
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: October 22, 2013
    Assignee: International Business Machines Corporation
    Inventors: Solomon Assefa, Sivananda K. Kanakasabapathy
  • Patent number: 8563227
    Abstract: The present disclosure provides a method of making a mask. The method includes providing a substrate having a first attenuating layer on the substrate and a first imaging layer on the first attenuating layer; performing a first exposure to the first imaging layer using a first radiation energy in writing mode; performing a first etching to the first attenuating layer; performing a second etching to the substrate; forming a second imaging layer on the first attenuating layer and the substrate; performing a second exposure to the second imaging layer using a light energy and another mask; and performing a third etching to the first attenuating layer after the second exposure.
    Type: Grant
    Filed: October 15, 2012
    Date of Patent: October 22, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Ming Chen, Ya-Ping Tseng, Ming-Tao Ho
  • Patent number: 8450048
    Abstract: There is disclosed a method for forming a resist underlayer film of a multilayer resist film having at least three layers used in a lithography, comprising at least; a step of coating a composition for resist underlayer film containing a novolak resin represented by the following general formula (1) obtained by treating a compound having a bisnaphthol group on a substrate; and a step of curing the coated composition for the resist underlayer film by a heat treatment at a temperature above 300° C. and 600° C. or lower for 10 to 600 seconds. There can be provided a method for forming a resist underlayer film, and a patterning process using the method to form a resist underlayer film in a multilayer resist film having at least three layers used in a lithography, gives a resist underlayer film having a lowered reflectance, a high etching resistance, and a high heat and solvent resistances, especially without wiggling during substrate etching.
    Type: Grant
    Filed: September 14, 2009
    Date of Patent: May 28, 2013
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Jun Hatakeyama, Toshihiko Fujii, Tsutomu Ogihara
  • Patent number: 8435724
    Abstract: In a fabricating method of a touch screen panel, a conductive layer and an insulating layer are sequentially formed on a same surface of a transparent substrate. The conductive layer and the insulating layer are co-patterned using a halftone mask to form first connection patterns having separated patterns and the insulating layer being patterned on the first connection patterns to expose regions of the first connection patterns. A transparent electrode layer is formed on the transparent substrate having the first connection patterns and the insulating layer. The transparent electrode layer is patterned to form first sensing patterns connected to the first connection patterns through the exposed regions of the first connection patterns and connected along a first direction, and to form second sensing patterns disposed between the first sensing patterns, wherein the second sensing patterns are insulated from the first sensing patterns and connected along a second direction.
    Type: Grant
    Filed: December 1, 2010
    Date of Patent: May 7, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Woo-Sik Jun, Do-Youb Kim, Ung-Soo Lee
  • Patent number: 8377631
    Abstract: Molecular glass based planarizing compositions for lithographic processing are disclosed. The processes generally include casting the planarizing composition onto a surface comprised of lithographic features, the planarizing composition comprising at least one molecular glass and at least one solvent; and heating the planarizing composition to a temperature greater than a glass transition temperature of the at least one molecular glass. Exemplary molecular glasses include polyhedral oligomeric silsesquioxane derivatives, calixarenes, cyclodextrin derivatives, and other non-polymeric large molecules.
    Type: Grant
    Filed: October 6, 2009
    Date of Patent: February 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Robert D. Allen, Mark W. Hart, Ratnam Sooriyakumaran
  • Patent number: 8361337
    Abstract: Nanopatterned substrates can be prepared by a method that includes forming a block copolymer film on a substrate, annealing the block copolymer film, surface reconstructing the annealed block copolymer film, coating an etch-resistant layer on the surface reconstructed block copolymer film, etching the resist-coated block copolymer film to create an etched article comprising a nanopatterned substrate, and separating the etch-resistant layer and the block copolymer film from the nanopatterned substrate. The method is applicable to a wide variety of substrate materials, avoids any requirement for complicated procedures to produce long-range order in the block copolymer film, and avoids any requirement for metal functionalization of the block copolymer.
    Type: Grant
    Filed: March 17, 2008
    Date of Patent: January 29, 2013
    Assignee: The University of Massachusetts
    Inventors: Soojin Park, Thomas P. Russell, Jia-Yu Wang, Bokyung Kim
  • Patent number: 8288074
    Abstract: There is herein described a method and apparatus for photoimaging. In particular, there is described a method and apparatus for photoimaging a substrate covered with a wet curable photopolymer, wherein the photoimaged substrate is used to form images such as electrical circuits.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: October 16, 2012
    Assignee: Rainbow Technology Systems Limited
    Inventors: Sheila Hamilton, Charles Jonathan Kennett
  • Patent number: 8288081
    Abstract: The present disclosure provides a method of making a mask. The method includes providing a substrate having a first attenuating layer on the substrate and a first imaging layer on the first attenuating layer; performing a first exposure to the first imaging layer using a first radiation energy in writing mode; performing a first etching to the first attenuating layer; performing a second etching to the substrate; forming a second imaging layer on the first attenuating layer and the substrate; performing a second exposure to the second imaging layer using a light energy and another mask; and performing a third etching to the first attenuating layer after the second exposure.
    Type: Grant
    Filed: April 2, 2007
    Date of Patent: October 16, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Ming Chen, Ya-Ping Tseng, Ming-Tao Ho
  • Patent number: 8288082
    Abstract: Example embodiments provide a method of fabricating a triode-structure field-emission device. A cathode, an insulating layer, and a gate metal layer may be sequentially formed on a substrate. A first resist pattern having a first opening and a second resist pattern having a second opening smaller than the first opening may be formed to be sequentially laminated on the gate metal layer. Then, the gate metal layer and the insulating layer may be etched using the first resist pattern to form a gate electrode and an insulating layer having a first hole and a second hole corresponding to the first opening. A catalyst layer may be formed on the cathode exposed through the first and second holes using the second resist pattern. After the first resist pattern, second resist pattern, and the catalyst layer on the second resist pattern are removed, an emitter may be formed on the catalyst layer in the second hole.
    Type: Grant
    Filed: November 10, 2008
    Date of Patent: October 16, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chan Wook Baik, Junhee Choi, Seog Woo Hong, Joo Ho Lee
  • Patent number: 8273519
    Abstract: A hardmask composition includes a solvent and an organosilicon copolymer. The organosilicon copolymer may be represented by Formula A: (SiO1.5—Y—SiO1.5)x(R3SiO1.5)y??(A) wherein x and y may satisfy the following relations: x is about 0.05 to about 0.9, y is about 0.05 to about 0.9, and x+y=1, R3 may be a C1-C12 alkyl group, and Y may be a linking group including a substituted or unsubstituted, linear or branched C1-C20 alkyl group, a C1-C20 group containing a chain that includes an aromatic ring, a heterocyclic ring, a urea group or an isocyanurate group, or a C2-C20 group containing one or more multiple bonds.
    Type: Grant
    Filed: November 21, 2007
    Date of Patent: September 25, 2012
    Assignee: Cheil Industries, Inc.
    Inventors: Mi Young Kim, Sang Kyun Kim, Sang Hak Lim, Sang Ran Koh, Hui Chan Yun, Do Hyeon Kim, Dong Seon Uh, Jong Seob Kim
  • Patent number: 8257905
    Abstract: A method of fabricating a thin film transistor substrate and a negative photoresist composition used therein are provided, which can reduce pattern inferiority. The method of fabricating a thin film transistor substrate includes forming a conductive film composed of a conductive material on a substrate, forming an etch pattern composed of a negative photoresist composition on the conductive film, and forming a conductive pattern by etching the conductive film using the etch pattern as an etching mask, wherein the negative photoresist composition includes 10-50 parts by weight of novolak resin including a hydroxyl group that is soluble in an alkali developing solution, 0.5-10 parts by weight of a first photo acid generator represented by the following formula (1), 0.
    Type: Grant
    Filed: January 11, 2010
    Date of Patent: September 4, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yeong-Beom Lee, Hi-Kuk Lee, Byung-Uk Kim, Hyoc-Min Youn, Ki-Hyuk Koo
  • Patent number: 8257908
    Abstract: [Object] To provide a coating-type underlayer coating forming composition that is applied for multi-ply coating process by thin film resist in order to prevent collapse of resist pattern after development with miniaturization of resist pattern, and that shows a sufficient etching resistance against a semiconductor substrate to be processed on processing of the substrate by having a low dry etching rate compared with the photoresist and substrate. [Means for solving problems] A coating-type underlayer coating forming composition that is used for lithography process by multi-ply coating, comprising a polymer containing a vinylnaphthalene based structural unit and an acrylic acid based structural unit containing an aromatic hydroxy group or a hydroxy-containing ester. A coating-type underlayer coating forming composition further comprising an acrylic acid based structural unit containing an aliphatic cyclic compound-containing ester or an aromatic compound-containing ester.
    Type: Grant
    Filed: August 15, 2006
    Date of Patent: September 4, 2012
    Assignee: Nissan Chemical Industries, Ltd.
    Inventors: Takahiro Sakaguchi, Tomoyuki Enomoto
  • Patent number: 8241837
    Abstract: Provided are a mask pattern including a silicon-containing self-assembled molecular layer, a method of forming the same, and a method of fabricating a semiconductor device. The mask pattern includes a resist pattern formed on a semiconductor substrate and the self-assembled molecular layer formed on the resist pattern. The self-assembled molecular layer has a silica network formed by a sol-gel reaction. To form the mask pattern, first, the resist pattern is formed with openings on an underlayer covering the substrate to expose the underlayer to a first width. Then, the self-assembled molecular layer is selectively formed only on a surface of the resist pattern to expose the underlayer to a second width smaller than the first width. The underlayer is etched by using the resist pattern and the self-assembled molecular layer as an etching mask to obtain a fine pattern.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: August 14, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Hwan Hah, Jin Hong, Hyun-Woo Kim, Hata Mitsuhiro, Kolake Mayya Subramanya, Sang-Gyun Woo
  • Publication number: 20120186862
    Abstract: The present invention relates to a method for manufacturing a TAB tap. The method includes forming a circuit pattern region having input/output terminal pattern on a base film, and forming an exposing region at a convey region having a sprocket hole for exposing the base film. Accordingly, the present invention provides a TAB tape that improves reliability of a product by fundamentally preventing the generation of metal particles by forming exposing regions that expose a base film through selectively etching and removing a metal layer of a convey region formed at both side of a TAB tape and having a sprocket hole, and that prevents short-circuit by partially removing a base film at a predetermined region not having a circuit pattern formed thereon through etching.
    Type: Application
    Filed: July 22, 2011
    Publication date: July 26, 2012
    Applicant: LG Innotek Co., Ltd.
    Inventors: Tae Ki Hong, Han Mo Koo, Jun Young Lim, Ki Tae Park, Sang Ki Cho, Dae Sung Yoo
  • Patent number: 8227173
    Abstract: A method of manufacturing a multi-layer circuit layer is provided. One example method includes the steps of: preparing an upper substrate and a lower substrate, wherein each of the upper and lower substrates includes a carrier layer and a seed layer, which are detachably connected to each other; forming circuits including first circuit patterns on the upper substrate and second circuit patterns on the lower substrate by plating on the seed layer; preparing a core substrate, wherein circuit patterns comprising a conductive material are formed on the core substrate; coupling the upper substrate, the core substrate, and the lower substrate by interposing adhesive members; detaching the carrier layer from the seed layer; etching the seed layer, wherein the seed layer is removed; and electrically connecting the first circuit patterns and the second circuit patterns to the third circuit patterns, respectively.
    Type: Grant
    Filed: June 2, 2008
    Date of Patent: July 24, 2012
    Assignee: Samsung Techwin Co., Ltd.
    Inventor: Jae-chul Ryu
  • Patent number: 8211617
    Abstract: A printed mask derived from a composition comprised of at least one compound including at least one alkaline-hydrolyzable group, and at least one compound including at least one ethylene oxide group. The printed mask is removable using an alkaline solution in about 30 seconds or less.
    Type: Grant
    Filed: August 17, 2009
    Date of Patent: July 3, 2012
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Norine E. Chang, C. Wayne Jaeger, Scott Jong Ho Limb, Eric J. Shrader, Francisco E. Torres, Kris Schmidt
  • Publication number: 20120154800
    Abstract: A method for producing planar extended electrodes with nanoscale spacings that exhibit very large SERS signals, with each nanoscale gap having one well-defined hot spot. The resulting highly sensitive substrate has extended metal electrodes separated by a nanoscale gap. The electrodes act as optical antennas to enhance dramatically the local electromagnetic field for purposes of spectroscopy or nonlinear optics. SERS response is consistent with a very small number of molecules in the hotspot, showing blinking and wandering of Raman lines. Sensitivity is sufficiently high that SERS from physisorbed atmospheric contaminants may be detected after minutes of exposure to ambient conditions.
    Type: Application
    Filed: February 12, 2008
    Publication date: June 21, 2012
    Inventors: Douglas Natelson, Daniel Robert Ward, Zachary Kyle Keane
  • Patent number: 8197659
    Abstract: A method for manufacturing a multilayer printed circuit board including providing a core substrate having a penetrating-hole, forming an electroless plated film on a surface of the substrate and an inner wall surface of the penetrating-hole, electrolytically plating the substrate while moving with respect to the surface of the substrate an insulating member in contact with the surface of the substrate such that an electrolytic plated film is formed on the electroless plated film, an opening space inside the penetrating-hole is filled with an electrolytic material, and a through-hole conductor structure is formed in the penetrating-hole, forming an etching resist having an opening pattern on the electrolytic plated film, and removing an exposed pattern of the electrolytic plated film exposed by the opening pattern and a pattern of the electroless plated film under the exposed pattern such that a conductor circuit is formed on the surface of the substrate.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: June 12, 2012
    Assignee: IBIDEN Co., Ltd.
    Inventors: Toru Nakai, Satoru Kawai, Hiroshi Niwa, Yoshiyuki Iwata
  • Patent number: 8187795
    Abstract: Described herein are processing techniques for fabrication of stretchable and/or flexible electronic devices using laser ablation patterning methods. The laser ablation patterning methods utilized herein allow for efficient manufacture of large area (e.g., up to 1 mm2 or greater or 1 m2 or greater) stretchable and/or flexible electronic devices, for example manufacturing methods permitting a reduced number of steps. The techniques described herein further provide for improved heterogeneous integration of components within an electronic device, for example components having improved alignment and/or relative positioning within an electronic device. Also described herein are flexible and/or stretchable electronic devices, such as interconnects, sensors and actuators.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: May 29, 2012
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Kanti Jain, Kevin Lin
  • Patent number: 8168372
    Abstract: Novel, developer-soluble, hard mask compositions and methods of using those compositions to form microelectronic structures are provided. The composition comprises the compound a compound for controlling development rate, and a crosslinking agent in a solvent system. The methods involve applying the composition to a substrate and curing the composition. An imaging layer is applied to the composition, followed by light exposure and developing, during which the light-exposed portions of the imaging layer are removed, along with portions of the hard mask composition adjacent said light-exposed portions. The size of the hard mask composition structures are controlled by the development rate, and they yield feature sizes that are a fraction of the imaging layer feature sizes, to give a pattern that can ultimately be transferred to the substrate.
    Type: Grant
    Filed: September 20, 2007
    Date of Patent: May 1, 2012
    Assignee: Brewer Science Inc.
    Inventor: Sam X. Sun
  • Patent number: 8163611
    Abstract: A resist pattern (5) is formed in a dimension of a limitation of an exposure resolution over a hard mask material film (4) over a work film (3). The material film (4) is processed using the resist pattern (5) as a mask. A hard mask pattern (6) is thereby formed. Thereby a resist pattern (7), over a non-selected region (6b), having an opening (7a) through which a selection region (6a) in the mask pattern is exposed is formed. Only the mask pattern (6a) exposed through the opening (7a) is slimmed by performing a selection etching, the work film (3) is etched by using the mask pattern (6). A work film pattern (8) is thereby formed, which include a wide pattern section (8a) of a dimension width of the limitation of the exposure resolution and a slimmed pattern section (8a) of a dimension that is not more than the limitation of the exposure resolution.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: April 24, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Hashimoto, Soichi Inoue, Kazuhiro Takahata, Kei Yoshikawa
  • Patent number: 8153349
    Abstract: A polymer composition includes an aromatic ring-containing polymer represented by Formula 1: wherein m and n satisfy the relations 1?m<190, 0?n<190, and 1?m+n<190.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: April 10, 2012
    Assignee: Cheil Industries, Inc.
    Inventors: Hwan Sung Cheon, Jong Seob Kim, Kyong Ho Yoon, Min Soo Kim, Jin Kuk Lee, Jee Yun Song
  • Patent number: RE45841
    Abstract: A thin-film transistor includes a substrate, and a gate including a double-layered structure having first and second metal layers provided on the substrate, the first metal layer being wider than the second metal layer by 1 to 4 ?m. A method of making such a thin-film transistor includes the steps of: depositing a first metal layer on a substrate, depositing a second metal layers directly on the first metal layer; forming a photoresist having a designated width on the second metal layer; patterning the second metal layer via isotropic etching using the photoresist as a mask; patterning the first metal layer by means of an anisotropic etching using the photoresist as a mask, the first metal layer being etched to have the designated width, thus forming a gate having a laminated structure of the first and second metal layers; and removing the photoresist.
    Type: Grant
    Filed: October 5, 2012
    Date of Patent: January 12, 2016
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Byung-Chul Ahn, Hyun-Sik Seo