Abstract: A technique for etching with a single layered patterned photomask at wavelengths of 193 nanometers or less. Specifically, a method for etching a bottom anti-reflectant coating layer that utilizes a combination of CF4, CH2F2, and O2 to produce a stabilized pattern in the photoresist layer. The etching process results in a structure with a defined pattern having minimal defects and that maintains integrity through the remainder of the etching.

Abstract: A positive type, photosensitive epoxy resin composition comprising (a) an epoxy resin having two or more epoxy groups in one molecule, (b) a modified phenolic resin having a triazine ring, (c) a latent basic curing agent and (d) a photosensitive acid generator; and a preferably multilayered printed circuit board of buildup mode using said composition as an insulating layer.

Abstract: A method for developing a photo-exposed photoresist layer to improve a critical dimension uniformity (CDU) for a semiconductor device manufacturing process including providing a semiconductor process wafer having a process surface comprising a photoresist layer photo-exposed according to an exposure pattern; dispensing a predetermined amount of developer solution over a stationary semiconductor process wafer to form a film of developer solution covering the process surface; partially developing the exposed portions of the photoresist layer comprising maintaining the semiconductor process wafer in a stationary position for a predetermined time period; rotating the semiconductor process wafer for a predetermined period of time to remove a portion of the developer solution; and, repeating the steps of dispensing, partially developing, and rotating, for a predetermined number of repetition cycles to complete a photoresist development process.

Abstract: One example of a separation-material composition for a photo-resist according to the present invention comprises 5.0 weight % of sulfamic acid, 34.7 weight % of H2O, 0.3 weight % of ammonium 1-hydrogen difluoride, 30 weight % of N,N-dimethylacetamide and 30 weight % of diethylene glycol mono-n-buthyl ether. Another example of a separation-material composition for a photo-resist according to the present invention comprises 1-hydroxyethylidene-1, 3.0 weight % of 1-diphosphonic acid, 0.12 weight % of anmonium fluoride, 48.38 weight % of H2O and 48.5 weight % of diethylene glycol mono-n-buthl ether.

Abstract: A dual damascene process is provided on a semiconductor substrate, having a conductive structure and a low-k dielectric layer covering the conductive structure. A first hard mask and a second hard mask are sequentially formed on the low-k dielectric layer, in which at least the hard mask contacting the low-k dielectric layer is of metallic material. Next, a first opening is formed in the second hard mask over the conductive structure, and a second opening is then formed in the first hard mask under the first opening. Afterward, the low-k dielectric layer that is not covered by the first hard mask is removed, thus a via hole is formed. Thereafter, the first hard mask that is not covered by the second hard mask is removed, and then the exposed low-k dielectric layer is removed. Thereby, a trench is formed over the via hole.

Abstract: The invention refers to a procedure for etching of materials at the surface by focussed electron beam induced chemical reactions at said surface. The invention is characterized in that in a vacuum atmosphere the material which is to be etched is irradiated with at least one beam of molecules, at least one beam of photons and at least one beam of electrons, whereby the irradiated material and the molecules of the beam of molecules are excited in a way that a chemical reaction predetermined by said material and said molecules composition takes place and forms a reaction product and said reaction product is removed from the material surface —irradiation and removal step.

Abstract: Method of forming a magnetic memory device are disclosed. In one embodiment, a first plurality of conductive lines are formed over a semiconductor workpiece. A plurality of magnetic material lines are formed over corresponding ones of the first plurality of conductive lines and a second plurality of conductive lines are formed over the semiconductor workpiece. The second plurality of conductive lines cross over the first conductive lines and the magnetic material lines. These second lines can be used as a mask to while the magnetic material lines are patterned.

Abstract: The present subject matter allows non-orthogonal lines to be formed at the same thickness as the orthogonal lines so as to promote compact designs, to be formed with even line edges, and to be formed efficiently. One aspect of the present subject matter relates to a method for forming non-orthogonal images in a raster-based photolithographic system. According to various embodiments of the method, a first image corresponding to a first data set is formed on a reticle when the reticle is at a first rotational position &thgr;1. The reticle is adjusted to a second rotational position &thgr;2. A second image corresponding to a second data set is formed on the reticle when the reticle is at the second rotational position &thgr;2. The second image is non-orthogonal with respect to the first image. Other aspects are provided herein.

Abstract: A low temperature method for forming a microcavity on a substrate and article having same are provided which utilize electroplated films. The method is particularly useful to package microelectromechanical systems (MEMS) in vacuum on the wafer level and provide sealed feedthroughs to the outside world. The method may be performed in a batch process to substantially reduce cost and to form metal diaphragms. Furthermore, the method is performed at near room temperature, which provides more flexibility in the manufacturing process. The method enables substantial cost savings in the production of vacuum-sealed MEMS. Many feedthroughs can be incorporated into the package to transfer signals in and out of the package. One significant advantage of this method is that it does not require bonding of a second substrate, which reduces the system cost.

Abstract: A method for fabricating patterned layers of a desired material in a desired, design pattern upon a substrate, which method may be used in circumstances where the removal of photo-resist material may not be used to lift-off undesired portions of the material from the substrate. The method uses copper or some other conducting material instead of the photo-resist material, Which copper or other conducting material may be removed by chemical processes to lift-off the undesired portions of material deposited upon the conducting material and substrate. The copper or other conducting material is fabricated upon the substrate so as to have a lip that overhangs and shadows the boundary of photo-resist material previously fabricated upon the substrate in the desired pattern.

Abstract: A process of forming a high-definition pattern by etching is provided. A photosensitive resin layer is formed on a metal substrate material having a center line-average surface roughness Ra of up to 0.10 &mgr;m and a maximum surface roughness Rmax of up to 1.0 &mgr;m to form a resist pattern. Then, the photosensitive resin layer provided on the metal substrate material is exposed to light to form a resist pattern. Finally, etching is carried out to form a pattern on the metal substrate material.

Abstract: A method for creating a phase shift photomask which includes a layer of hard mask material, the inclusion of which improves the uniformity of critical dimensions on the photomask by minimizing the affect of macro and micro loading. The method for producing the phase shift photomask of the instant invention includes two etching processes. The first etching process etches the layer of hard mask, and the second etching process etches opaque material (and anti-reflective layer, if used) and phase shift layers.

Abstract: Provided is a projection optical system for forming an image of a pattern of a first object (R) on a second object (W). The projection optical system is made of an optical material having a refractive index of not more than 1.6 and is substantially telecentric both on the first object side and on the second object side. The projection optical system satisfies the condition of (&lgr;×L)/(NA×Y02)<1.5×10−3, where &lgr; is a wavelength of light, L a distance between the first object and the second object, MA a numerical aperture on the second object side, and Y0 a maximum image height on the second object.

Abstract: A method for forming a conductive trace on a substrate. The conductive trace is patterned with a photoresist mask and etched, thereby forming a polymer layer on a top surface and sidewalls of the photoresist mask and on sidewalls of the conductive trace. The polymer layer contains entrained chlorine gas. The substrate is heated on a chuck in a reaction chamber. A remote plasma is generated from ammonia gas and oxygen gas. The substrate is contacted with the ammonia and oxygen plasma, thereby withdrawing a substantial portion of the entrained chlorine gas from the polymer layer. A radio frequency potential is applied to the chuck on which the substrate resides, thereby creating a reactive ion etchant from the ammonia and oxygen plasma in the reaction chamber and removing the polymer layer from the top surface of the photoresist mask. The photoresist mask is thus exposed, and then removed in an ashing process.

Abstract: Provided is a process for creating a via through a substrate including the steps of (a) providing a substantially void-free film of a curable composition; (b) applying a resist onto the curable film; (c) imaging the resist in predetermined locations; (d) developing the resist to expose predetermined areas of the curable film; (e) removing the exposed areas of the curable film to form holes through the curable film; and (f) heating the curable film of step (e) to a temperature and for a time sufficient to cure the curable composition. Also disclosed is a process of fabricating a circuit assembly which includes building patterned circuit layers upon a substrate that has vias provided by the aformentioned process.

Abstract: Provided is a process for creating vias for a circuit assembly including the steps of (a) applying a curable coating composition to a substrate, some or all of which is electrically conductive, to form an uncured coating thereon; (b) applying a resist over the uncured coating; (c) imaging the resist in predetermined locations; (d) developing the resist to expose predetermined areas of the uncured coating; (e) removing the exposed areas of the uncured coating; and (f heating the coated substrate of step (e) to a temperature and for a time sufficient to cure the coating. Also disclosed is a process of fabricating a circuit assembly.

Abstract: After films composing a TFT are laminated on an insulating substrate, a resist mask having a plurality of regions with different film thicknesses is formed by patterning on the uppermost layer of the above-stated films. Then, a conductor film is formed by patterning with a liftoff method using this resist mask. Alternatively, using other resist mask having a plurality of regions with different film thicknesses as an etching mask, a plurality of material films among the laminated material films are processed in succession. By the above-stated new pattern forming method and the processing method, the liquid crystal display device, which has been manufactured by five photolitho processes in a conventional art is manufactured by two or three photolitho processes.

Abstract: A method for manufacturing a circuit board having a conductive via comprises the steps of providing a substrate having a first surface and a first conductive layer on at least one region of the first surface, forming an insulating layer on the first conductive layer, forming an opening in the insulating layer, so that the opening extending to the first conductive layer, forming a second conductive layer inside the opening and at least on the insulating layer near the opening, applying a positive photoresist on the second conductive layer, exposing the positive photoresist, developing the exposed positive photoresist, and removing the positive photoresist on the second conductive layer, except a portion of the second conductive layer that is inside the opening, etching the second conductive layer, to expose a surface of the second conductive layer, removing the positive photoresist from inside the opening, and forming a third conductive layer inside the opening.

Abstract: An etch barrier to be used in a photolithograph process is disclosed. A silicon rich etch barrier is deposited on a substrate using a low energy deposition technique. A diamond like carbon layer is deposited on the silicon rich etch barrier. Photoresist is then placed on this etch barrier DLC combination. To form photolithographic features, successive steps of oxygen and flourine reactive ion etching is used.

Abstract: A method of forming an opening in a wafer layer. At least two patterned photoresist layers are formed on a wafer layer. Using different photoresist layers, many openings are defined. The wafer layer is then etched to form the opening. Each photoresist layer has a parallel linear pattern such as parallel strips or an array of rectangular blocks. The photoresist layers are superposed in a way that spaces between the patterns for each photoresist layers overlapped with each other for form openings that expose the underlying wafer layers. The wafer layer exposed in the openings is then etched to form contact/via holes without rounded corners while the rounded profiles has been cancelled by the superposition of the photoresist layers.

Abstract: Provided is a method of manufacturing a printed wiring board which keeps a good etching factor of formed circuits, eliminates an etching residue and can effectively prevent the occurrence of surface layer migration.

Abstract: In a method of etching a substrate having a surface layer of conductive material, a circuit pattern is transferred to the surface layer in a central surface area portion of the substrate by electrochemical etching. To prevent excessive current densities from forming at the periphery of the central surface area portion during the etching step, a frame adapted to attract electrical field is provided adjacent to the central surface area portion. The frame can be part of a separate frame element which is placed on the substrate before the etching step, or be incorporated in a resist coating on the substrate. The frame can be transferred to the resist coating by any suitable means, for example by photolithographic exposure through a mask with a suitable frame pattern. Alternatively, the frame can be incorporated in a prefabricated substrate element, to which the circuit pattern is transferred in the etching step.

Abstract: A process is described for trimming photoresist patterns during the fabrication of integrated circuits for semiconductor devices and MEMS devices. A combination of a low temperature (<20° C.), high density oxygen and argon plasma and intense UV radiation is used to simultaneously trim and harden a photoresist linewidth in an ICP chamber. As an alternative, a UV hardening step can be performed in a flood exposure tool prior to the ICP plasma etch. Another option is to perform the argon plasma treatment first to harden the resist and then in a second step apply an oxygen plasma to trim the photoresist. Vertical and horizontal etch rates are decreased in a controllable manner which is useful for producing gate lengths in MOS transistors of less than 100 nm. The process can also be used to controllably increase a space width in a photoresist feature.

Abstract: Two sided printed circuit boards with very small rings surrounding the plated though holes can be produces by starting with a through-plated copper laminate, and coating it with a liquid negative electrodeposition photo-resist. The coated photo-resist is exposed to light through a mask set up so that the light does not shine on the through-platings. The non-crosslinked photo-resist is subsequently removed. A metal or a metal alloy resist is laid down by electrodeposition on those surfaces from which the non-crosslinked photo-resist has been removed. Finally, the crosslinked photoresist material is removed and the exposed copper laminate is treated with a copper-etching solution to completely remove the copper surface that has been uncovered.

Abstract: A desirable pattern is formed in a photoresist layer that overlies a semiconductor wafer using an attenuating phase shift reflective mask. This mask is formed by consecutively depositing an attenuating phase shift layer, a buffer layer and a repairable layer. The repairable layer is patterned according to the desirable pattern. The repairable layer is inspected to find areas in which the desirable pattern is not achieved. The repairable layer is then repaired to achieve the desirable pattern with the buffer layer protecting the attenuating phase shift layer. The desirable pattern is transferred to the buffer layer and then transferred to the attenuating phase shift layer to achieve the attenuating phase shift reflective mask. Radiation is reflected off the attenuating phase shift reflective mask to the photoresist layer to expose it with the desirable pattern.

Abstract: A thinner for rinsing photoresist including 50 to 80 wt. % of n-butyl acetate, propylene glycol alkyl ether, and propylene glycol alkyl ether acetate, is provided. The thinner is neither toxic to humans nor ecologically undesirable and has no unpleasant odor. The waste solutions thereof and associated waste water are easily handed so as to render this thinner environmental friendly. Additionally, the photoresist thinner of the present invention has excellent rinsing ability.

Abstract: Disclosed is disclosed a process for producing a printed wiring board which comprises the steps of: a) exposing a wiring board having at least one photoconductive layer in which its chargeability is changed by light exposure on at least one surface of a conductive support which comprises an insulating substrate and at least one metal conductive layer provided at least one surface thereof through a resist pattern; b) charging the photoconductive layer to form an electrostatic latent image; c) forming a toner image on the photoconductive layer by toner developing treatment; d) removing a portion of the photoconductive layer to which no toner is attached by dissolution to form a resist image; and e) removing a portion of the metal conductive layer other than a portion where the resist image is formed by etching.

Abstract: Disclosed is a method for fabricating a plate-type magnetic resistance sensor chip simply and easily. First, a characteristic membrane composed of NiCo and NiFe is deposited over a surface of a glass wafer, exposed to light, and etched in a predetermined pattern to establish sensing parts. Then, a protective film is formed atop each of the sensing parts by depositing a SiO2 membrane over the glass wafer, exposing the SiO2 membrane to light, and etching the SiO2 membrane in the same pattern as in the sensing part. The resulting structure is subjected to sand blasting to form through-holes at every corner of the sensing parts. A NiFe film is deposited around the through-holes on both sides of the glass wafer and within the through-holes to form conductors.

Abstract: The invention relates to a method for producing sequentially built-up printed circuit boards having a disparate number of conduction planes on both sides of the laminate core, which method comprises the following method steps: (A) coating both sides of a printed circuit board having conductor structures on only one side with a dielectric comprising a photopolymer or a thermally curable polymer; (B) structuring the plating holes (vias) on the side having the conductor structures by exposing the dielectric comprising a photopolymer to light and then developing with a solvent or by laser-drilling the plating holes (vias) into the dielectric comprising a thermally cured polymer; (C) depositing a copper layer on both sides of the board so obtained; (D) forming conductor structures on the front and completely etching away on the rear, if further asymmetric build-up is to be carried out, or on both sides of the printed circuit board if there is to be no further build-up or if further build-up is to be carried ou

Abstract: A method of fabricating a lead frame. The method includes providing an electrically conductive layer having a pair of opposing major surfaces. A pattern is etched in the layer extending partially through the layer to form cavities with sidewalls in the layer. A patterned mask is provided on the etched layer including masking of the sidewalls. The layer is again etched within the cavities. The patterned mask is preferably a liquid photo resist and the electrically conductive layer is preferably one of a copper or copper-based material or ALLOY 42. The etch can take place from both major surfaces.

Abstract: Nanolaminates are formed by alternating deposition, e.g., by combustion chemical vapor deposition (CCVD), layers of resistive material and layers of dielectric material. Outer resistive material layers are patterned to form discrete patches of resistive material. Electrical pathways between opposed patches of resistive material on opposite sides of the laminate act as capacitors. Electrical pathways horizontally through resistive material layers, which may be connected by via plated holes, act as resistors.

Abstract: An object of the present invention is to provide an elecroless copper plating solution using glyoxylic acid or a salt of glyoxylic acid as the reducing agent in which the amount of Cannizzaro reaction product is small, and the mechanical property of the obtained plated film is excellent, and to provide a supplementary solution for the electroless copper plating solution, a plating method capable of stably forming a plated film using the electroless copper plating solution, and a method of manufacturing a wiring board having an excellent connecting reliability of a through hole.

Abstract: A test structure pattern includes a first comb having a first set of tines, and a second comb having a second set of tines of the same width and spacing as the first set of tines. When the test structure pattern is stepped between fields on a wafer, the first comb and the second comb at least partially overlap on photoresist over a scribe lane between the fields. When the photoresist is developed, the overlap of the first comb and the second comb generates a metal comb. Electrical continuity is checked for the metal tines of the metal comb to determine the misalignment of the fields.

Abstract: A method for producing printed circuit boards having coarse conductor structures and at least one region having fine conductor structures. The coarse conductor structures and the fine conductor structures are etched out of a metal layer in a common etching process. An etching resist patterned by means of photolithography is used in the region of the coarse conductor structures, and an etching resist patterned with the aid of a laser beam is used in the region of the fine conductor structures.

Abstract: Antireflective structures according to the present invention comprise a metal silicon nitride composition in a layer that is superposed upon a layer to be patterned that would other wise cause destructive reflectivity during photoresist patterning. The antireflective structure has the ability to absorb light used during photoresist patterning. The antireflective structure also has the ability to scatter unabsorbed light into patterns and intensities that are ineffective to photoresist material exposed to the patterns and intensities. One preferred material for the antireflective layer includes metal silicon nitride ternary compounds of the general formula MxSiyNz, where M is at least one transition metal, x is less than y and z is greater than about 0 and less than about 5y.

Abstract: A high density printed wiring board is prepared by applying an essentially solid material into plated through holes such that the metallized layers within the through hole are unaffected by chemical metal etchants. In this manner, lateral surface metallized layers can exclusively be reduced in thickness by use of said chemical agents. These thinned lateral surface metallized layers are ultimately converted into fine pitch, 25 to 40 microns, circuitry, thereby providing high density boards. Since the through hole wall metallization is unaffected by the etching process, excellent electrical connection between the fine line circuitry is obtained. Various printed wiring board embodiments are also presented.

Abstract: Forming a protective layer such as chromium, chrome alloys, nickel or cobalt as a cap over an aluminum film protects an underlying ITO layer from corrosion during the fabrication of flat panel displays such as field emission devices and the like. The presence of the protective layer during fabrication processes such as photolithography prevents diffusion of solutions through the aluminum into the ITO. This protective layer is especially effective during the development and resist stripping stages of photolithography which use solutions or solvents that would otherwise cause reductive corrosion of ITO in contact with aluminum. The methods and apparatus described herein are particularly advantageous for the fabrication of flat panel displays such as field emission devices and other display devices, because ITO is often used in such devices in contact with aluminum while exposed to corrosion-inducing media.

Abstract: A process for forming a plurality of bumps on a wafer comprises forming a first UBM (under ball metallurgy) over an active surface of a wafer. A second UBM is formed over the first UBM. A part of the second UBM is removed to expose the first UBM. A plurality of solders are respectively formed to cover the second UBM and the first UBM not covered by the second UBM. The first UBM not covered by the second UBM and not covered by the solders is removed.

Abstract: A patterning method includes providing a first material (e.g., copper) and transforming at a least a surface region of the first material to a second material (e.g., copper oxide). One or more portions of the second material (e.g., copper oxide) are converted to one or more converted portions of first material. (e.g., copper) while one or more portions of the second material (e.g., copper oxide) remain. One or more portions of the remaining second material (e.g., copper oxide) are removed selectively relative to converted portions of first material (e.g., copper). Further, a thickness of the converted portions may be increased. Yet further, a diffusion barrier layer may be used for certain applications.

Abstract: A method for forming cells array of mask read only memory, at least includes: form numerous gate structures on substrate; form numerous doped regions in uncovered part of substrate; form first conductor layer on uncovered part of substrate with a thickness essentially equal to thickness of gate structures; form first dielectric layer on first conductor layer; form second conductor layer on both gate structures and first dielectric layer; perform a pattern transform process for transferring both second conductor layer and gate structures into conductor lines as word lines; form second dielectric layer on sidewalls of conductor lines to form spacer; form code photoresist on second conductor layer; and perform ions implantation process for implant numerous ions into partial substrate which is not covered by code photoresist.

Abstract: A method for protecting a semiconductor process wafer surface from contacting thermally degraded photoresist including providing a semiconductor process wafer having a process surface; forming a protective layer over selected areas of the process surface said protective layer including a resinous organic material having a glass transition temperature (Tg) that is about greater than a thermal treatment temperature; forming a photoresist layer over at least a portion of the protective layer to include a photolithographic patterning process; and subjecting the semiconductor process wafer to the thermal treatment temperature.

Abstract: There is provided a negative radiation-sensitive composition, which is suitable for exposure of a far ultraviolet light comprising a wavelength 193 nm of ArF excimer-laser, freed from causes of resolution deterioration such as swelling due to permeation of a developer and residual of a resist film between lines of the pattern, and capable of forming a high resolution pattern.

Abstract: A redistribution process is described. A wafer is provided, wherein a first titanium layer, a first copper layer and a second titanium are sequentially formed over the surface of the wafer. The second titanium layer, the first copper layer and the first titanium layer are then defined to form a patterned trace layer. A patterned benzocyclobutene layer is then formed to expose the second titanium layer. The exposed second titanium layer is further removed to expose the first copper layer. Thereafter, a plurality of contacts is formed over the patterned benzocyclobutene layer and to connect with the first copper layer. Further, the wafer comprises a plurality of bonding pads, wherein each bonding pad is connected with each contact through the patterned trace layer.

Abstract: A method of making a electrically operated programmable resistance memory element. A silylated photoresist sidewall spacer is used as a mask for form raised portions on an edge of a conductive layer. The modified conductive layer is used as an electrode for the memory element.

Abstract: Disclosed is a method for fabricating a gate of semiconductor device. The disclosed comprises the steps of: sequentially forming a gate oxide layer, a gate material layer and a mask oxide layer on a semiconductor substrate; coating photopolymer having compound accelerator including polar functional group which absorbs HF vapor and ionize at a predetermined high temperature on the mask oxide layer; exposing the photopolymer and cross-linking the portion of exposed photopolymer; performing DFVP process by passing over HF vapor on the resultant substrate at a predetermined high temperature, thereby developing the portion of exposed photopolymer and etching the portion of mask oxide layer exposed by development of photopolymer simultaneously; removing the residual photopolymer; and etching the gate material layer and the gate oxide layer using the etched mask oxide layer.

Abstract: A blank printed circuit board (10), for creating a circuit pattern thereon by direct imaging with infrared radiation. The blank printed circuit board (10) includes in sequence an insulating substrate (20), a metal layer (21), a resist layer (22) and a mask layer (23).

Abstract: A metal layer, an etching resist and a photoresist are successively applied to an electrically insulating substrate. Whereupon the photoresist is patterned by photolithography in such a way that it covers a pattern of the later coarse conductor structures and the entire region of the later fine conductor structures. After the uncovered etching resist has been stripped, the photoresist is removed, whereupon the etching resist is patterned with the aid of a laser beam in such a way that it has the pattern of the fine conductor structures. The coarse conductor structures and the fine conductor structures are then formed in a common etching process.

Abstract: A carbon-doped hard mask includes a dielectric material containing carbon which is released from the hard mask during a metal etching process. The released carbon is deposited on and bonds to sidewalls of the metal structure during the metal etching process to passivate the sidewalls of the metal structure and prevent lateral etching of the sidewalls during the metal etching process. The released carbon also prevents accumulation of metal residue in open fields.

Abstract: Through holes are formed at four peripheral edges of a plurality of semiconductor chip placement regions of an insulating substrate, except for coupling portions partially arranged thereat. A substrate sheet for semiconductor module is used in which connecting portions between inner lead portions and outer lead portions arranged on both surfaces of the substrate are formed in pattern on the side wall surface of the through hole. The semiconductor chip is mounted on each region, electrode terminals thereof and the inner lead portions are electrically connected to each other, the chip is sealed, and then the coupling portions are cut.

Abstract: A photomask including chromium patterns divided into two groups in such a fashion that the chromium patterns in one of the two chromium pattern groups alternate, one by one, with the chromium patterns in the other chromium pattern group, the chromium patterns being formed on two quartz substrate for the two chromium pattern groups, respectively, to prepare for the photomask, two separate photomasks each having an increased space defined between adjacent chromium patterns thereof so as to avoid a severe diffraction of light passing between the adjacent chromium patterns. A method for forming micro patterns of a semiconductor device using the photomask is also disclosed.