Abstract: A process in the fabrication of wiring patterns on ceramic or polymeric substrates precisely controls the cross-sectional dimensions of the metallization that constitute the wiring patterns. A single etch process defines thin film conductors on a substrate without loss to the conductor cross-section and provides enhanced thin film design flexibility. The zero undercut etch process uses photoresists defining the metal patterns to completely protect the metal patterns during the subetch.

Abstract: A multilayer interconnection system is formed on a multilayer ceramic (MLC), or glass ceramic body, by screening a blanket layer of etchable conductive paste on the body, drying and firing the resistant paste layer, and delineating the circuit pattern in the blanket layer with lithographic and etching techniques. A dielectric layer with via openings is formed over the circuit pattern, and the via openings filled. The steps are repeated until the desired circuitry is fabricated. A top circuit pattern is formed by screening an etchable conductive paste on the top surface, drying and firing the paste, and delineating the pattern using photolithographic and etching techniques.

Abstract: A new method of producing an anti-reflection coating is described. The reflective metal layer of an integrated circuit is covered with titanium. The titanium layer is oxidized. The resulting titanium oxide layer is the anti-reflection coating (ARC) of the present invention. This ARC layer is covered with photoresist. The photoresist layer is selectively exposed to light by directing light through a patterned mask to form a pattern on the photoresist layer. The metal layer is etched in accordance with the pattern. The remaining resist is stripped off. An inter-metal dielectric layer is deposited over the patterned first metal and titanium oxide layers. A second photoresist layer is deposited and selectively exposed to light through a second photomask. The titanium oxide layer again acts to limit the reflection of light off the first metal layer and through the transparent inter-metal dielectric. The exposed inter-metal layer is etched away to the underlying first metal layer.

Abstract: Disclosed are photo-masks for use in two exposure steps to be effected for forming a ground metal layer on the back surface of a substrate in manufacture of a two-layer: TAB in which a metal layer is formed on one surface or both surfaces of an insulating resin substrate without an adhesive, determined metal leads are formed on the top surface of the substrate, via holes are formed on the determined positions of the substrate, a ground metal layer is formed on the back surface of the substrate, and a part of the leads as formed on the top surface of the substrate are electrically connected with the ground metal layer as formed on the back surface of the same via the via holes; the photo-masks being characterized in that the photo-mask to be used in the first exposure step for forming the via holes to the back surface of the substrate is provided with alignment marks in the determined plural positions thereof and that the photo-mask to be used in the second exposure step for forming the ground metal layer on t

Abstract: A method for fabricating a metal interconnection pattern for an integrated circuit module is provided comprising the steps of: aligning only one face of the module, forming a metal layer on at least one other face of the module, applying a coating of photoresist to the metal layer, exposing predetermined portions of the photoresist to reflected radiation, and shaping the metal layer in accordance with the exposed photoresist portions.

Abstract: Assemblies of aligned tape automated bonding frames on a substrate, and a method of aligning a tape automated bonding frame to connection sites on the substrate. The method includes photolithographically patterning and etching metal to form a first pattern of signal leads and a second pattern of alignment leads. A semiconductor chip is bonded to the inner lead ends of the first pattern. Metal on a substrate is photolithographically patterned and etched to provide a third pattern of substrate connection sites and a fourth pattern of registration pads. The fourth pattern of registration pads has geometric and dimensional features which precisely correspond to those of the alignment leads. Moreover, the spatial relationship of the third and fourth patterns correspond to the spatial relationship of the first and second patterns. The corresponding geometric and dimensional features of the second and fourth patterns are aligned, whereafter the registration pads and the alignment leads are soldered together.

Abstract: A phase-shifting lithographic mask is made by a procedure involving only a single patterned electron, ion, or photon beam bombardment of a resist layer. The bombardment is arranged to produce three kinds of regions in the resist: no dosage, low dosage, and high dosage. These three regions in the resist are then utilized--in conjunction with an ordinary wet development step followed by either a silylation or an optical flooding technique, and thereafter by another ordinary wet development step--to pattern the resist layer and thereby to enable forming, by dry or wet etching, an underlying double layer consisting of a patterned opaque layer and a patterned transparent phase-shifting layer, the phase-shifting layer being located on, or being part of, a transparent substrate.

Abstract: Described herein is a liquid color composition containing a resin binder and a plasticizer which is compatible with the binder. The toner is very transparent and produces excellent quality images when used in xeroprinting processes.

Abstract: A method for manufacturing a semiconductor device having a via hole penetrating a semiconductor substrate and electrically and thermally connecting an electrode of an element disposed on a front surface of the substrate to a metal layer disposed on a back surface of the substrate includes forming on the front surface of the substrate a metal pattern having an opening at a region where the via hole is to be formed and connected to a part of the electrode of the element, forming a hole, and forming a metal film connected to the metal pattern on the inside surface of the hole. The metal pattern can be formed using a positive resist on a flat substrate whereby a highly precise pattern is obtained.

Abstract: A method for patterning a tape to which an integrated circuit may be bonded including providing a tape having a top layer of unexposed film which, when exposed in an interconnection pattern and developed, acts as a mask for processing a photoprocessable layer of the tape to provide conductive portions in an interconnection pattern on the tape.

Abstract: A multilayered board is formed by applying a photosensitive insulating resin layer on a laminated plate on which via holes and a circuit pattern are formed, followed by the formation of photoviaholes through the photoprinting method, plating and etching. Then, the multilayered board is adhered to another multilayered board prepared in the same manner through a prepreg layer and a conductive paste while applying heat and pressure to give a multilayer printed wiring board. According to this method, electrical connections between the conductive layer of the upper-most layer and the inner conductive layers, between the inner conductive layers, and between the lower-most conductive layer and the inner conductive layers can be achieved through the photoviaholes and the conductive paste. Therefore, it is not necessary to form through-holes for the electrical connection therebetween. The multilayer printed wiring boards can be substantially improved in the number of layers and wiring density thereof.

Abstract: The method involves a thick film paste that is screen printed over the circuit plane of the substrate in the desired circuit pattern. The thick film paste is dried and fired. A metallorganic conductive paste is screen printed on top of the thick film circuit pattern, then it is dried and fired. If the printed circuit covers the whole substrate, the metallorganic paste is screen printed over the whole substrate. Alternatively, if the printed circuit covers portions of the substrate, the metallorganic paste is screen printed only over those portions. If the linewidth of the desired circuits is less than 4 mils, then the circuits are defined by photolithography. Alternatively, if the desired linewidth is greater than 4 mils, the screen printing technology is sufficient to define the circuits.

Abstract: An electrophoretic positive working photosensitive composition for producing a photoresist pattern on metal base plate comprises a photosensitive compound, in which a photosensitive quinone diazide group is grafted on a polyester, and an acrylic copolymer containing carboxyl group, the composition forms a smooth photoresist film on the plate and has a good adhesion to the surface that no pinehole is found.

Abstract: An improved process for preparing a printed-circuit board, which successively comprises (I) a step of forming a positive photo-sensitive resist film onto a circuit board having a conductive film according to the electrodeposition coating process, (II) a step of irradiating a full dose of an actinic ray onto the positive photo-sensitive resist film through a photomask with which the actinic ray is cut off over a conductive circuit-forming area, (III) a step of developing the resulting resist film, (IV) a step of etching away a deposited copper-clad area, and (V) removing a remaining resist film on the conductive circuit-forming area, the improvement further comprising a step of imparting the resist film in the conductive circuit-forming area an increased alkali resistance prior to development so as to obtain the printed-circuit board having high resolution with good reproductivity without being affected by variations of the developing conditions.

Abstract: A process of patterning a conductive layer on a substrate avoiding webbing yet permitting high density patterning places two layers between the resist and the metal. The first layer is an antireflective coating such as titanium nitride applied to the metal. The second layer is a barrier comprising silicon such as sputtered silicon or SiO.sub.2. The barrier layer may also be a thin coating of spin-on glass. The barrier layer prevents interaction between the TiN and acid groups which are generated during exposure of the resist. With this structure in place the resist is applied, exposed and developed.

Abstract: A two-layer film carrier for TAB is made from a substrate prepared by forming a copper layer on a polyimide film by additive plating. A photoresist layer is formed on the copper layer, and another photoresist layer on the polyimide film. Both of the photoresist layers are simultaneously exposed to light through a mask applied to each of them to define a desired pattern. The exposed portions of the photoresist layer on the copper layer are subjected to development and postbaking, whereby selected portions of the copper layer are exposed. The exposed portions of the copper layer are additive plated with copper, whereby leads are formed. The exposed portions of the photoresist layer on the polyimide film are subjected to development and postbaking, whereby selected portions of the polyimide film are exposed. The remaining portions of the photoresist layer are removed from the copper layer and the underlying copper layer is etched.

Abstract: A thin film printed circuit inductive element exhibiting low Q wherein a conductive spiral is deposited on an insulating substrate and resistive links are connected between adjacent turns of the spiral. Inherent resonance is thereby damped out.

Abstract: The process of the invention produces tapes for automatic mounting of electronic components. These mounting tapes have metallic conductive tabs with metallic bumps on at least one of their ends. The metallic bumps can be thermally welded or soldered, have well-defined areas and heights, and adhere well to the conductive tabs.

Abstract: A process is disclosed for producing superconductor films on a variety of substrates, and more particularly a patterned superconductor film on a planar substrate. The basic process includes the steps of: 1) depositing a metal film of superconductor precursor elements on a substrate; 2) patterning the metal film; and 3) oxidizing the metal film to form a superconductor film. Because the process separates the metal precursor film formation, patterning, and oxidation steps, each of the steps can be individually optimized.

Abstract: In a method of manufacturing a semiconductor device, an Al wiring layer is formed on an interlevel insulator using a positive resist. The interlevel insulator has a recess portion formed on its surface corresponding to a position between two electrodes under the interlevel insulator. The Al wiring layer extends along the recess portion in the longitudinal direction and is formed to bridge the recess portion in a direction perpendicular to the logitudinal direction. The method includes the steps of arranging an Al layer on a region of the interlevel insulator including the recess portion, arranging the resist of the Al layer, exposing the resist to a light beam using a mask member having a light-shielding portion corresponding to the wiring layer, patterning the photoresist, and etching the Al layer using the patterned resist as a mask to form the wiring layer.

Abstract: An electrode pattern forming method comprising the steps of: forming a transparent conductive film on a substrate, covering said transparent conductive film with an aluminum film, forming a resist material film for etching on said aluminum film, exposing said resist material film followed by developing by immersing said substrate in an electrolyte to form a resist pattern, and patterning said aluminum film using said resist pattern as a mask;the formation of said resist pattern in said electrolyte being conducted with another transparent conductive film which is in direct contact with said electrolyte and electrically connected to said aluminum film.

Abstract: Lead frames for microchips and other integrated circuit dies are produced by a continuous manufacturing method and apparatus in which silver spot plating is done prior to etching away unwanted portions of the lead frame substrate. A flexible substrate of a metal alloy is fed continuously from a reel, then spot plated with silver, coated with a photosensitive material, and exposed to intensive light in an exposure chamber using a photoresist or masking tool of predetermined design. The exposed photosensitive material is developed chemically, etched in acid, and placed in a chemical solution to remove any remaining unwanted material. The strip is then dried, cut to predetermined lengths and boxed for shipment. If necessary, the strip is downset and taped before packaging. In a presently preferred process, the metal alloy substrate is 42 alloy (Fe+Ni), and the selective spot plating is silver 100 to 150 microinches thick.

Abstract: A method for the preparation a photo-mask used for photo-imaging selected areas on the surfaces of a three-dimensional printed circuit board substrate. The photo-mask comprises an opaque layer, opaque and degradation resistant to UV light, having at least one side with a contoured shape conforming to the surface irregularities on the surfaces of the three-dimensional substrate being photo-imaged. A membrane transparent and degradation resistant to UV light, having at least one side cemented to the side of the opaque layer not in contact with the surfaces of the three-dimensional substrate being photo-imaged. A pattern of grooves positioned on the opaque layer allow transmission of UV light during the photo-imaging of the surfaces of the three-dimensiional substrate. The pattern of grooves is in accordance with a conductive metal trace pattern desired on the surfaces of the three-dimensional printed circuit board substrate.

Abstract: Foil includes a first etch-resistant layer which at least partially covers the neighboring layer and has a weight per unit area of 0.5-20 g/m.sup.2, a first aluminum or aluminum alloy layer having a thickness of about 30 .mu.m to 150 .mu.m, a dielectric layer of plastic having a thickness of about 5 to 100 .mu.m, a second aluminum or aluminum alloy layer having a thickness of about 30 .mu.m to 150 .mu.m, and a second etch-resistant layer which at least partially covers the neighboring layer and has a weight per unit area of 0.5 to 20 g/m.sup.2.

Abstract: The invention provides an aqueous electrodeposition coating composition for a positive working resist and an image-forming method using the same. The coating composition is very stable under storage conditions and is capable of resulting in a positive working resist which is specifically useful in the preparation of a printed circuit board with mini-via-holes.

Abstract: Phase-shifting (two-optical-level) masks are manufactured by a self-aligned technique in which after first-level trenches in the mask have been formed, second-level trenches therein are formed by patterning an electron resist overlying the mask in such a manner that the edges of the patterned resist can be located anywhere within the first-level trenches, whereby the need for precise alignment of the resist patterning for the second-level trenches is avoided.

Abstract: A method is disclosed for fabricating patterned conductive lines which are self-aligned with underlying contacts windows. A layer of a photosensitive material such photoresist is formed over a dielectric layer. The photoresist layer is processed to have fully developed areas corresponding to contact windows, partially developed areas corresponding to the patterned conductive lines and undeveloped areas which correspond to field areas where the entire dielectric layer is maintained. The dielectric layer is preferably a compound dielectric layer to reduce interlevel shorts. Through the use of selective etch steps, the compound dielectric layers aid in the formation of the patterned conductive line and contact window structure. A series of reactive ion etch (RIE) steps are performed. The first RIE step, highly selective to dielectric material as compared to photoresist, etches the fully developed areas at least partially through the dielectric thickness.

Abstract: A method for manufacturing a circuit board on which electronic components and electrical circuits are to be mounted and connected together. The method comprises positioning mutually insulated and mutually intersecting electrical conductors in a layer of substrate material, preferably to form an x/y matrix, and treating the substrate material, with the conductors embedded therein, in a manner to establish interruptions in the various conductor paths at given locations therein, and to establish permanent electrical contact between the intersecting conductor paths at given locations of intersection. The substrate material used is sensitive to a given kind of radiation, and the material is irradiated, while screening those locations at which interruptions are to be established or at which the conductor paths are to be connected together.

Abstract: In conducting wiring by masking the portion other than the portion to be wired of a metallic laminate with a photoresist for plating and subjecting only the portion to be wired to pattern plating, the provision of a noble metal layer made of gold, platinum or the like, or a metallic layer made of a metal having a larger ionization tendency than that of a metal used in the pattern plating on the metallic layer constituting the undercoat of the photoresist for plating enables the peeling of the resist for plating to be prevented and excellent fine wiring to be conducted.

Abstract: A positive-type photosensitive electrodeposition coating composition comprising(A) a photosensitive compound having a molecular weight of less than 6,000 and containing at least one modified quinonediazidesulfone units represented by the following formula (I) ##STR1## wherein R.sub.1 represents ##STR2## R.sub.2 represents a hydrogen atom, an alkyl group, a cycloalkyl group or an alkyl ether group, andR.sub.3 represents an alkylene group, a cycloalkylene group or an alkylene ether group,in the molecule and(B) an acrylic resin having a salt-forming group.

Abstract: An antireflection coating (16) for use with a photolithographic process comprises a layer of organic material that planarizes the surface upon which a photoresist layer (21) is deposited, is highly absorptive of deep ultraviolet actinic light, and can be plasma etched along with an underlying metal layer (11), thereby obviating the need for a separate step to remove the exposed antireflection coating prior to metal etch.

Abstract: A process is disclosed for accurately forming an etch mask over the uneven surface of a semiconductor wafer using a multilayer photoresist. The process comprises forming a first or lower photoresist layer on the surface of a semiconductor wafer, forming one or more intermediate layers over the first photoresist layer, forming a second or upper photoresist layer over the one or more intermediate layers on the wafer, photolithographically forming a pattern in the second photoresist layer, reproducing the pattern in the intermediate layer below the second photoresist layer, removing the remainder of the upper photoresist layer, and then reproducing the pattern in the first photoresist layer using the pattern formed in the intermediate layer as a mask. In one embodiment a single intermediate layer is used in which the mask pattern is partially etched prior to removal of the upper photoresist.

Abstract: A thin film magnetic head including top and bottom pole tips having reversed trapezoidal cross sections. Mirror image symmetry across a gap region may be achieved. The top and bottom pole tips may be formed using a photolithographic process using positive photoresist including post bake and flood exposure steps.

Abstract: A method of photolithographically patterning a layer of a dielectric composition including a photosensitive polyimide provides patterned dielectric features that have vertical wall profiles that are free of distortions normally associated with high temperature production conditions and shrinkage of the dielectric composition. The method is useful in the production of integrated circuits and high density multiconnect structures.

Abstract: In a microbump flip-chip mounting method, microcircuit features such as conductors and microbumps are formed by a lift off process. A first refractory metal is employed to promote adhesion between a layer of aluminum deposited by physical vapor deposition and a second refractory metal is employed to promote adhesion between the aluminum and an overlying layer of gold.

Abstract: The present invention provides a method for making a metallic pattern on a substrate having a surface comprising bare metal in predetermined areas and metal coated by a resist in remaining areas which comprises (i) protecting the bare metal by coating with a film-forming resin, (ii) removing any film-forming resin from the resist, (iii) removing the resist from said remaining areas using a solvent which will not remove the film-forming resin, thereby exposing metal in said remaining areas, (iv) etching the metal exposed in (iii) using an etchant which does not remove the film-forming resin and (v) removing the film-forming resin with a suitable solvent.

Abstract: Disclosed is an improved process for preparing a printed-circuit board, which comprises successive steps of electrodeposition coating of a photosensitive resin on a printed-circuit base plate to form a photosensitive resist film, exposure to light through a pattern mask, development and etching, the improvement further comprising a step of dipping the photosensitive resist film formed by electrodeposition coating into an aqueous solution comprising water as a major component and applying a voltage to carry out electroendosmosis, whereby the tendency of the photosensitive resist film to stick to the pattern mask is reduced.

Abstract: There is disclosed a dyed, spin-on glass composition with a high carbon content for use in providing antireflective planarizing layers on substrates such as semiconductor silicon wafers. These layers can be used as hard masks by etching patterns therein. These hard masks can be used in multilayer resists and in making lithography masks. Methods for producing these hard-masks are also provided.

Abstract: Disclosed is a method of forming a fine pattern composed by repeating, at least once or more, a series of fine pattern forming process having the steps of coating a photoresist on a wafer, exposing a predetermined portion of the wafer through a reticle, carrying out a developing process after the exposure process, etching the wafer, and removing a resist remaining on the wafer, wherein different portions on the wafer are respectively exposed in the exposing process in the series of fine pattern forming process, and each portion once exposed in the process is not exposed again.

Abstract: A method for making lithographic masks using a soda lime glass substrate that is useful particularly in the manufacture of near submicron and submicron integrated circuits. The problem of "mouse nipping" at the edges of the chromium metal and chromium oxide mask lines is overcome by using a very thin high molecular weight coating under the standard resist layer and over the chromium oxide layer.

Abstract: An enhanced halogenated plasma for ion-assisted plasma etches to which silicon tetrabromide has been added to retard erosion, flowing and reticulation of photoresist, particularly during an etch of an aluminum or tungsten metal layer. The added resistance to erosion, flowing and reticulation is greater than that achieved through the addition of silicon tetrachloride to the same plasma. It is postulated that a silicon-containing layer is deposited on horizontal and vertical surfaces of photoresist at a faster rate than that possible for silicon tetrachloride. As with silicon tetrachloride, resist loss still occurs, but at a much reduced rate, with loss on the upper surfaces of the photoresist segments (these surfaces being perpendicular to the RF field of the reactor) occurring at a higher rate than loss on vertical surfaces (these surfaces being parallel to the RF field of the reactor).

Abstract: Disclosed is a cleaning process for use primarily in the fabrication of printed circuit boards. Cleaning is done in-line with the coating and development of a photoresist layer. The process includes a spray cleaning and micro-etch, followed by the application of an anti-tarnish so that the boards can be stored prior to plating.

Abstract: There is disclosed methods for fabricating electrophoretic displays. Essentially the methods employ selective materials such as different metals which are capable of being etched by different etchants. In this manner, a laminate is provided to form a grid matrix which is insulated from a cathode matrix which grid matrix is also insulated from a second anode matrix. The entire display utilizes a local or second anode and a remote anode to further control pigment particle migration. The display is fabricated by two methods both of which employ selective etching of the parallel line type of display electrodes which constitute a cathode, a grid and a local anode.

Abstract: A method of forming a photosetting film includes the steps of forming a photosensitive film containing(a) 100 parts by weight of a modified resin obtained by reacting an .alpha.,.beta.-unsaturated monocarboxylic acid derivative having an alcoholic hydroxyl group represented by formula: ##STR1## (wherein each of R.sub.1 and R.sub.2 independently represents a hydrogen atom or methyl and R.sub.3 represents a hydrocarbon residue which may contain nitrogen or oxygen) with an .alpha.,.beta.-unsaturated dicarboxylic acid anhydride adduct having a softening point (measured by a ring and ball softening point method of JIS K2531-60) of not less than 70.degree. C. of a conjugated diene polymer or copolymer having a number-average molecular weight of 500 to 5,000, and a vinyl group content of not less than 50 mol % such that at least 10 mol % of an acid anhydride group of the adduct are ring-opened, and(b) 0.

Abstract: A via (26) is formed through a dielectric layer (8) separating two conductive layers (16,28) by establishing a laterally erodible mask (18) over the dielectric (8), with a window (24) over the desired via location. The mask (18) and exposed dielectric material (8) are eroded simultaneously, preferably by reactive ion etching, producing a via (26) through the dielectric (8) which expands laterally as vertical erosion proceeds. The erosion conditions, the materials for the mask (18) and dielectric (8), and the initial window (24) taper are selected so that the final via (26) is tapered at an angle of less than about 45.degree. to the lower metal layer (6), and preferably about 30.degree.-45.degree., to enable a generally uniform width for the upper metallization (28) in the via (26).

Abstract: The present invention provide a process for producing printed circuit boards which comprises the steps of(a) roughening a surface of a copper layer formed on an insulating board.(b) coating the roughened surface of copper layer with a photo-resist layer containing a sublimable copper-corrosion inhibitor, exposing the resist layer selectively to actinic rays according to a circuit pattern to form, and developing the resulting resist layer, thereby forming plating-resist coats on circuit-negative pattern portions of the copper layer,(c) heat-treating the plating-resist coats,(d) plating chemically the circuit-corresponding portion with copper,(e) removing the plating-resist coats, and(f) removing the copper layer except the circuit-corresponding portion thereof.

Abstract: Each transistor or logic unit on an integrated circuit wafer is tested prior to interconnect metallization. By CAD means, the transistor or logic units placement net list is revised to substitute redundant defect-free logic units for defective ones. Then the interconnect metallization is laid down and patterned under control of a CAD means. Each die in the wafer thus has its own interconnect scheme, although each die is functionally equivalent, and yields are much higher than with conventional testing at the completed circuit level.The individual transistor or logic unit testing is accomplished by a specially fabricated flexible tester surface made in one embodiment of several layers of flexible silicon dioxide, each layer containing vias and conductive traces leading to thousands of microscopic metal probe points on one side of the test surface. The probe points electrically contact the contacts on the wafer under test by fluid pressure.

Abstract: In a multi-level circuit of the kind having two or more crossing conductive tracks (12, 14) on a substrate (16) separated at the region of the cross-over (21) by insulative material (20), for example for use in an active matrix display device requiring sets of mutually orthogonal conductors on a substrate for addressing switching elements (71) adjacent the cross-over regions connected to picture element electrodes (70) also carried on the substrate, at least one of the crossing tracks (12,14) is divided at the cross-over region into a plurality of mutually spaced conductive paths (24-26) connected electrically in parallel with one another.

Abstract: Disclosed is a method of improving semiconductor device yield by enhancing photoresist adherence to semiconductor substrates during device fabrication. The surface of a layer, such as silicon oxide of silicon nitride, on a semiconductor substrate is coated with a thin layer of oxygen-reactive metal prior to applying photoresist material thereto. The metal is selected from the group consisting of tungsten, titanium, chromium, and combinations thereof; the thickness of the layer of oxygen-reactive metal is of the order of 50-100 .ANG.. The metal coating facilitates the adhesion of the resist material and reduces undercutting of the layer to be etched.

Abstract: The projection of a planar distorted pattern onto a three dimensional surface provides a true or undistorted pattern on that surface. Complex patterns are applied to an irregular or curved surface by a method which includes the formation of a graphics display of the body on a computer graphics display and conversion to a two dimensional CADAM data base containing a planar projection of the pattern intended for application to the curved surface. This pattern information is translated into other forms, such as the form of a numerically controlled milling machine tape or photo mask, which is then used by ancillary method apparatus to form the desired pattern as a part of the method. The process describes the construction of a dichroic parabolic RF reflector.