Abstract: A process for formation of a metal pattern comprising the steps of forming a silicide metal film on an underlying substrate, forming an anti-reflection film on the underlying substrate on which the silicide metal film is formed, forming a resist film on the anti-reflection film, patterning the resist film by photolithography to form a predetermined pattern, and using the thus patterned resist film as a mask and etching the silicide metal film on the underlying substrate, wherein the optical constants and the thickness of the anti-reflection film are determined to give the smallest standing wave effect at the time of photolithography in accordance with the type of the silicide metal film.

Abstract: A pattern forming method having a step of forming an amorphous carbon film on a patterning layer formed on a substrate, a step of forming a photoresist film on the amorphous carbon film, a step of selectively exposing and developing the photoresist film to form a photoresist pattern, and a step of successively dry-etching the amorphous carbon film and the patterning layer by using the photoresist film as an etching mask. Desired optical constants of an amorphous carbon film formed by sputtering can be obtained by controlling a substrate temperature and other parameters.

Abstract: A method for fabricating a semiconductor capacitor having superior sidewall linearity and high capacitance in a small area wherein a titanate or tantalum barrier metal platform is deposited on the insulation layer of the semi conductor substrate. A capacitor structure comprising a first electrode layer of platinum or palladium, a dielectric layer preferably of a ferroelectric having a perovskite structure, and a second metal electrode layer is then constructed by sequential deposition of said layers. The subsequently deposited electrode metal of platinum or palladium will adhere to said barrier metal but delaminate from said insulation layer during high temperature cycling, yielding a high capacitance, small surface area structure.

Abstract: A method for fabricating a semiconductor device, including the steps of: coating an anti-reflective film over a lower layer to be patterned; coating a first photoresist film over the anti-reflective film and subjecting the first photoresist film to a light exposure process using a mask and a development process, thereby forming a first photoresist film pattern having a dimension slightly larger than a desired pattern dimension; etching an exposed portion of the anti-reflective film, thereby forming an anti-reflective film pattern; removing the first photoresist film pattern and coating a second photoresist film over the entire exposed surface of the resulting structure obtained after the removal of the first photoresist film pattern; subjecting the second photoresist film to a light exposure process using the mask and a development, thereby forming a second photoresist film pattern having the desired pattern dimension; and etching an exposed portion of the anti-reflective film pattern and then etching the low

Abstract: A method of fabricating a double level metal (DLM) anode plate for use in a field emission device comprises the steps of providing a transparent substrate 82 having an active region 58 and a bus region 62. Then providing electrically conductive regions 50 on the surface. The conductive regions 50 span the active region 58 and the bus region 62. Next, the surface is coated with an electrically insulating material 94 and then the electrically insulating material 94 is removed from selected portions of the bus region 62, the active region 58, and upper portions of the transparent substrate 82. A first bus 52 is provided for electrically connecting a first series of the conductive regions, a second bus 54 is provided for electrically connecting a second series of the conductive regions, and a third bus 56 is provided for electrically connecting a third series of the conductive regions. Luminescent material of a first color 88.sub.R is applied to the first series of conductive regions 50.sub.

Abstract: The surface of a copper layer in a circuit board is irradiated with a beam, and the degree of progress of oxidation of the surface of the copper layer is determined by taking advantage of the resultant reflected beam (for example, an intensity or a hue of a reflected beam). Then, the step of coating a resist is carried out only when the thickness of the copper oxide film is not more than about 10 nm. Alternatively, the step of coating a resist may be carried out after removal or reduction of the oxide film or cladding of the oxide film with copper.The present invention enables occurrence of peeling of the resist or dive of plating to be prevented in the step of effecting selective etching or plating of a copper layer in a circuit board using a resist pattern as a mask.

Abstract: Each transistor or logic unit on an integrated circuit wafer is tested prior to interconnect metallization. By means of CAD software, the transistor or logic units placement net list is revised to substitute redundant defect-free logic units for defective ones. Then the interconnect metallization is laid down and patterned under control of a CAD computer system. Each die in the wafer thus has its own interconnect scheme, although each die is functionally equivalent, and yields are much higher than with conventional testing at the completed circuit level.The individual transistor or logic unit testing is accomplished by a specially fabricated flexible tester surface made in one embodiment of several layers of flexible silicon dioxide, each layer containing vias and conductive traces leading to thousands of microscopic metal probe points on one side of the test surface. The probe points electrically contact the contacts on the wafer under test by fluid pressure.

Abstract: A permanent solder mask is applied to the surface of a printed circuit board using a copper foil carrier. The solder mask preferably is one or two layers of a thermosetting resin e.g. epoxy resin. Selected circuit features are exposed by etching away portions of the copper foil and removing the underlying thermosetting resin. Then, the remaining copper foil is removed, leaving the solder mask on the surface of the printed circuit board.

Abstract: A positive type anionic electrodeposition photoresist composition comprising, as a main component, a dispersion obtained by neutralizing, with a base, a mixture comprising:(A) an acrylic resin containing carboxyl group(s) and hydroxyl group(s),(B) a vinylphenol resin containing a hydroxystyrene unit in an amount of at least 25% by weight based on the resin, and(C) an ester between a polyhydroxybenzophenone and 1,2-naphthoquinone diazide sulfonic acid or benzoquinone diazide sulfonic acid, and dispersing the resulting neutralization product in water.This composition is superior in running stability during electrodeposition and is useful for formation of highly reliable resist pattern or conductor pattern.

Abstract: A method for fabricating an active matrix substrate for forming constituent elements such as a semiconductor layer, a passivation layer, an electrode material and other elements, uses a photoresist exposed from the reverse side of the substrate, using the gate electrode pattern made of opaque material on a transparent substrate as the mask. This method contributes to lowering the cost and improving the performance of semiconductor devices.

Abstract: A method is provided for fabricating a display cathode which includes forming a conductive line adjacent a face of a substrate. A region of amorphic diamond is formed adjacent a selected portion of the conductive line.

Abstract: A method for electrophoretically depositing a layer of photoresist on a non-planar silicon structure and a method for forming a non-planar silicon structure using electrophoretic deposition are provided. The method comprises forming a silicon substrate with a non-planar topography and forming a conductive layer on the substrate. The substrate is then submerged in an electrolytic bath containing a photoresist solution comprising a polymer and a charged carrier group. At the same time the conductive layer is connected to a voltage source and to a non-sacrificial electrode and electrically biased. The biased conductive layer attracts the carrier group and causes a layer of photoresist to uniformly deposit on the conductive layer. The layer of photoresist can then be exposed and developed to form a photomask for etching the conductive layer. In an illustrative embodiment the silicon structure is an interconnect for testing unpackaged semiconductor dice.

Abstract: A photomask used by photolithography and a process for producing same which allows a single exposure to make a photomask, thereby simplifying the photomask making process, and facilitating the inspection and correction of photomasks. In addition, the phase shifter using a slanting pattern prevents a pattern from being formed outside a predetermined area. The use of a phase shifter which does not resolve under an optical projection system shields a large size area against an irradiated light, thereby allowing the formation of fine, intricate patterns suitable for use in LSIs.

Abstract: A method is provided for fabricating a display cathode which includes forming a conductive line adjacent a face of a substrate. A region of amorphic diamond is formed adjacent a selected portion of the conductive line.

Abstract: A photosensitive insulation bonding layer is formed on a conducting layer. The photosensitive insulation bonding layer is subjected to exposure treatment to produce an exposed area and an unexposed area. Another conducting layer is formed on the outer surface of the photosensitive insulation bonding layer which has undergone the exposure treatment, then both conducting layers are photoetched to produce desired wiring patterns. In the next step, the unexposed area is removed from the photosensitive insulation bonding layer by development so as to form an access opening for connecting a circuit component to the wiring patterns. Then, the exposed area of the photosensitive insulation bonding layer is turned into an insulating layer by curing.

Abstract: A method of producing an aperture grill of a CRT display device is disclosed. The aperture grill is of a small thickness of the order of 20 to 100 .mu.m. To a metal plate with front and rear surface resin layers are applied front slit pattern mask with a single broad slit pattern and a rear slit pattern mask with two adjacent, narrow slit patterns. With these two masks disposed in opposition, the slit patterns are printed and developed on the resist layers. Thereafter, etching is carried out on the rear surface of the metal plate via the rear resist layer, and rear cavities are formed in the metal plate. Then, a reinforcing, etchant-proof film is attached to the rear resist layer to cover the rear cavities, and thereafter etching is carried out on the front surface of the metal plate via the front resist layer, to thereby form a front cavity.

Abstract: A printed circuit board and a method for making same is disclosed whereby a very high wiring density is provided in those regions of the printed circuit board in which external components (e.g., semiconductor chips) are to be attached directly. An automated registration routine permits very precise registration and positioning in said regions.

Abstract: The present invention provides a process for producing a high-density printed wiring board with plated throughholes, at high productivity and reliability by a direct drawing method.

Abstract: A method for fabricating a thin-film magnetic read/write head that eliminates contrast effects producing notching in a thin-film magnetic head coil caused by subsurface reflectivity at a reflective layer step during a photolithography step in the fabrication of the coil is provided. The method comprises the steps of forming a first permalloy yoke on a substrate, wherein the edges of the first yoke create steps from the top of the first yoke down to the substrate, forming a partial conformal layer of an electric insulation material over the first permalloy yoke and the substrate, forming a conformal copper seed layer over the electric insulation layer, forming a conductive coil on the electric insulation layer, wherein the copper coil is fabricated using a lithography process including placing a phase-shifting mask, formed in the image of the coil and containing non-printable openings covered by transparent material of a thickness that creates a 180.degree.

Abstract: A method for making a millimeter wave device having a dielectric substrate with a pair of substantially parallel planar surfaces with at least one predetermined millimeter wave circuit pattern formed in a conductive layer located on at least one of the substrate surfaces. A substantially planar conductive channel plate is mounted adjacent the conductive layer on one substrate surface with the channel plate having an aperture overlying each circuit pattern formed in the conductive layer. A substantially planar conductive cover plate is mounted adjacent one of the channel plates so as to form a first cavity in the region defined by the substrate surface, the channel plate aperture and the cover plate. The device may further include a second substantially planar conductive channel plate mounted adjacent the other one of the substrate surfaces with the second channel plate having an aperture corresponding to and aligned with the first channel plate aperture.

Abstract: A method for manufacturing a printed circuit board is to form on a top surface of an insulating substrate a layer of such plating ground as a metal film, to irradiate such electromagetic wave as a laser to a boundary edge zone of non-circuit parts with respect to circuit-printing parts on the insulating substrate in correspondence to a pattern of the non-circuit parts to remove the plating ground layer at the part irradiate by the electromagnetic wave with the plating ground layer at the non-irradiated part left as formed, and thereafter to form a plating on the surface of the plating ground layer at the non-irradiated parts, whereby it is enabled to allow the laser irradiation to be carried out only with respect to the boundary edge zone of the non-circuit parts, without irradiating all over the non-circuit parts.

Abstract: Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The printed circuit cards are mounted on or connected to a plurality of circuitized flexible substrates, with one printed circuit card at each end of the circuitized flexible circuit. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication.

Abstract: In a method for fabricating a printed circuit board on a doubly contoured or hemispherical substrate such as a radome, a coherent light source is used to form a plurality of elements of a predetermined pattern on the surface of the substrate. The substrate includes a bottom layer and a metallized layer. At least a first element of the pattern is formed by ablating the element into a resist coating or ablating the element into the metallized layer with the coherent light source. The coherent light source preferably includes an excimer laser. The substrate is then displaced relative to the coherent light source until all the elements of the predetermined pattern are formed over the entire surface of the substrate. When the pattern is ablated into the resist material, an etching technique is used to remove portions of the metallized layer from the substrate.

Abstract: A method for manufacturing a curved surface multi-layer wiring board having the through-holes and high accurate inner patters with a high reliability. A curved surface multi-layer wiring board is manufactured by processes for forming the inner pattern on the copper clad substrates, and for perforating the holes to the substrates and prepregs, and for laying-up these substrates and prepregs, then for pressing these substrates and prepregs in the formation mould. Then the outer pattern are formed by the laser exposure process after the through holes are connected between the layers. A method is also provided for repeating the laying-up processes in order to obtain a curved surface multi-layer wiring board of which is a three dimensional curved surface.

Abstract: Each transistor or logic unit on an integrated circuit wafer is tested prior to interconnect metallization. By means of CAD software, the transistor or logic units placement net list is revised to substitute redundant defect-free logic units for defective ones. Then the interconnect metallization is laid down and patterned under control of a CAD computer system. Each die in the wafer thus has its own interconnect scheme, although each die is functionally equivalent, and yields are much higher than with conventional testing at the completed circuit level.The individual transistor or logic unit testing is accomplished by a specially fabricated flexible tester surface made in one embodiment of several layers of flexible silicon dioxide, each layer containing vias and conductive traces leading to thousands of microscopic metal probe points on one side of the test surface. The probe points electrically contact the contacts on the wafer under test by fluid pressure.

Abstract: A method for manufacturing a curved surface multi-layer wiring board having highly accurate inner patterns with high reliability. A curved surface multi-layer wiring board is manufactured by providing and pressing a prepreg to form a curved surface, and by plating a copper film on the curved surface. Outer patterns are formed on the copper film. The outer patterns may be formed by a laser exposure process after through-holes are connected between the layers. A method is also provided for repeating the process to obtain a curved surface multi-layer wiring board which has a three dimensional curved surface.

Abstract: a thin film printed circuit inductive element exhibiting low Q wherein a conductive spiral is deposited on an insulating substrate and resistive links are connected between adjacent turns of the spiral. Inherent resonance is thereby damped out.

Abstract: Electrical charge accumulation caused by exposure to a charged particle beam during the formation of latent image pattern can be reduced and thus the positional deviation of the pattern by using a bottom-resist layer comprising a radiation-induced conductive composition. Highly integrated semiconductor device can be made easily and in high yields. The positional deviation can further be reduced by exposing a charge particle beam patterning apparatus substantially simultaneously with an actinic radiation such as ultraviolet light, X-ray, and infrared light.

Abstract: A method of manufacturing a semiconductor device is disclosed. The method comprises the steps of forming carbon layer on a light-reflective layer or a transparent layer formed on a light-reflective layer, forming a photosensitive resin layer on the carbon layer, selectively radiating light on the photosensitive resin layer, forming a photosensitive resin pattern by developing the photosensitive resin layer selectively irradiated with the light, forming a carbon pattern by etching the carbon layer using the photosensitive pattern as a mask, and forming a light-reflective pattern or a transparent layer pattern by etching the light-reflective layer using the photosensitive resin layer or the carbon pattern as a mask. When the light-reflective layer pattern is formed, the thickness of the carbon layer is set to be less than 100 nm. When the transparent layer pattern is formed, the thickness of the carbon layer is set to be 80 nm or more.

Abstract: A process for selective plating of a metal onto a substrate surface is provided. The process includes laminating a layer of conductive metal onto a dielectric substrate; and providing thru holes extending through said layer of conductive metal and said dielectric substrate.A thin layer of conductive metal is plated on the walls of the thru holes; and a photoresist layer is applied to the surface of the conductive metal and selectively exposed and developed to provide a mask corresponding to the negative of the desired circuit pattern.The exposed metal that is not covered by the photoresist is removed and then the remaining photoresist is removed to thereby provide the desired circuit pattern. A conductive metal is plated on the pattern up to the desired thickness.

Abstract: The solubility of tetramethylammonium hydroxide pentahydrate in dimethyl sulfoxide is significantly increased by adding to the solution a quantity of dipropyleneglycol monomethylether. This permits up to twelve percent of the tetramethylammonium hydroxide pentahydrate to be dissolved in dimethyl sulfoxide, rather than the maximum of two percent that would otherwise be the case, which enhances the capacity of the solution to strip photoresist. Particularly, if the concentration of dipropyleneglycol monomethylether is in the range of ten to thirty percent, one can obtain both a high stripping rate and a much higher stripping capacity. For example, stripping capacity may be increased from one hundred forty substrates per gallon to six hundred substrates per gallon.

Abstract: A method of providing selective silver plating to a lead frame structure 10 performs the silver plating operation prior to etching the lead frame, thereby avoiding mechanical damage to the lead frame during plating, and producing finished silver spots 24 on the top surface of the lead frame only, with no plating on the gauge. The disclosed method includes the steps of applying a layer of photoresist 42 to a surface of a sheet of lead frame material 40, exposing areas of the photoresist such as to define selected regions 44, developing the photoresist 42 to uncover the lead frame material 40 at the selected regions 44, and plating the surface of the sheet defined by the layer of photoresist 42 with an electrically conductive material 46.

Abstract: A process for forming interconnection lines on a printed circuit board is described. The surface of a circuit board substrate is covered with a photoresist layer, and the photoresist layer in turn is covered with a halide emulsion layer. The emulsion layer is then exposed to a predetermined pattern of white light, and the image developed. The board is then exposed to UV light through the imaged emulsion layer which acts as a pattern masking selected portions of the photoresist mask. The emulsion layer is then stripped and the photoresist processed in conventional manner.

Abstract: The surface of a metal foil to be used as an intermediate layer in printed circuit boards is chemically roughened. In one embodiment, fine depressions are etched out of the metal coating. In another embodiment, protuberances are plated thereon. The use of the method permits the use of the foil in the production of multilayer printed circuit boards with coatings having different thermal expansion characteristics and improves the adhesion with the next conductor layer applied thereto to a significant extent and prevents delamination.

Abstract: A method for patterning a tape to which an integrated circuit may be bonded including providing a tape having a top layer of unexposed film which, when exposed in an interconnection pattern and developed, acts as a mask for processing a photoprocessable layer of the tape to provide conductive portions in an interconnection pattern on the tape.

Abstract: The invention provides a trilayer structure and photolithographic method which permits use of high-resolution optics with a relatively small depth of focus for patterning a substrate. A trilayer lithographic structure in accordance with the invention comprises: (a) an out-gas resistant planarization layer deposited on a substrate; (b) a chemical-vapor-deposited interfacial film formed on the planarization layer; and (c) a photosensitive resist layer of a thickness equal to or less than one micron deposited on the interfacial film. A method in accordance with the invention comprises the steps of: (a) depositing an out-gas resistant planarization layer on a substrate; (b) chemical-vapor-depositing an interfacial film on the planarization layer; and (c) forming a photosensitive resist layer of a thickness equal to or less than one micron on the interfacial film.

Abstract: A method for simultaneously manufacturing metallized carriers from wafer-shaped substrates is described, wherein such wafer-shaped substrates permit the use of standard IC fabrication apparatus and methods. As a result, very thin and finely dimensioned traces can be deposited. Thin-film manufacturing techniques are used to create the high-density traces on the surface of the chip carriers, thereby permitting direct connections from the IC to the periphery of the carrier without the need for vias. A lid hermetically seals and protects the package. The traces are comprised of a plurality of metals to facilitate bonding, each of the metals homogeneous for a portion of the trace. One metal portion of the trace is of a type compatible with an IC chip placed in the carrier. Another metal portion of the trace is of a type compatible with a trace on a printed circuit board. A metal barrier is interposed between the metals to prevent metal diffusion from one metal to an adjoining portion of another metal.

Abstract: Method for producing printed circuit board using a photocurable resin laminate comprising a support and a photocurable resin layer disposed on one surface of said support, said photocurable resin layer having:(a) a viscosity of from 10.sup.4 to 5.times.10.sup.5 poises as measured at 90.degree. C.;(b) a thickness of from 30 to 150 .mu.m; and(c) an ultraviolet ray transmittance of from 40 to 95% with respect to ultraviolet rays having a wavelength of 365 nm.When this photocurable resin laminate is laminated under pressure on both surfaces of a metal-clad insulting base board having through-holes of an inner diameter smaller than 0.

Abstract: The present invention provides a process for rendering acrylic based negative photoresists resistant to hot alkaline permanganate etchant and the iron chloride etchant and for improving the adhesion of the photoresist to the substrate, yet does not require halogenated reagents to develop or strip the photoresist. It has been discovered that the degradation of acrylic based negative photoresists by the permanganate etchant may be overcome by exposing an imaged acrylic based negative photoresist to select wavelengths of actinic radiation either ultraviolet light that is rich in deep UV, about 254 nm wavelength; or infrared radiation from about 2.4 to about 8 microns. Where UV radiation is used, the photoresist is then baked to reduce undercutting of the photoresist. Thereafter, the photoresist is stripped using nonhalocarbon solvents.

Abstract: A "maskless" process is provided for the formation of a refractory metal layer (22b), such as titanium, in via holes (18) through GaAs wafers (12) to contact microwave monolithic integrated circuit (MMIC) devices (10) formed on the front surface (12a) thereof. The process of the invention, which prevents AuSn solder (28) from filling up the holes during a subsequent eutectic AuSn bonding of the device to a metal carrier (30), such as molybdenum, utilizes the difference of resist thickness on the GaAs backside surface (12b) and in the via holes, so that the resist (24b) remaining in the via holes after removing the resist (24a) over the GaAs back surface serves as a mask in etching the refractory metal layer (22a) over the GaAs back surface. The process of the invention does not require any masks, and results in self-alignment of the refractory metal to the via hole. The process is simple and results in high yield of the MMIC devices on GaAs chips (26).

Abstract: A positive-type photosensitive electrodeposition coating composition comprising(A) a resin component containing in a molecule at least one unit selected from the group consisting of an ortho-benzoquinonediazidesulfone unit represented by the general formula ##STR1## an ortho-naphthoquinonediazidesulfone unit represented by the general formula ##STR2## as a photosensitive group, and an anion-forming group; and (B) at least one of the specified particular nitrogen-containing compounds. The composition is useful for the production of a circuit plate.

Abstract: The present invention provides a method of forming a semiconductor device. A layer of photoresist is applied to a semiconductor wafer. A first mask is used to protect a first portion of the photoresist while a second portion of the photoresist is exposed. A second mask is used to expose a third portion of the photoresist wherein the third portion of the photoresist includes part of the first portion of the photoresist. The photoresist is developed to form a photoresist mask.

Abstract: The present invention provides a method of forming a pattern of conductive material on dielectric material with access openings or vias through said dielectric material and such a structure. A sheet of conductive material, which is to be circuitized, is provided with a layer of a first photoimageable dielectric material on one face thereof. A layer of a second photoimageable material, such as a conventional photoresist material, is provided on the opposite face of the conductive material. The layer of said first photoimageable material is selected such that it will not be developed by the developer that develops the layer of said second material. The two layers of photoimageable material are pattern-wise exposed to radiation. The second layer of material is developed and the revealed underlying conductive material is etched to form the desired circuit pattern.

Abstract: A process for forming a conductive region without photoresist-related reflective notching damage has a starting step (23) wherein a photoresist layer is formed over a conductive layer (34). The photoresist layer is used to mask the conductive layer. The photoresist layer is lithographically processed and chemically developed to form a masking photoresist region (38) overlying the conductive layer (34). The masking photoresist region has a sidewall and has a reflective notch which results from the lithographic processing. A hardening step, performed in-situ with a plurality of conductive layer etch steps, is used to form an etch-resistant polymer layer (40) on the photoresist sidewalls and on the reflective notch. The conductive layer (34) is etched after the formation of the polymer layer (40) to form a conductive region. The polymer layer (40) reduces an etch rate of the reflective notch and the photoresist sidewall so that the conductive region is formed having no reflective notching etch damage.

Abstract: Disclosed herein is a method for manufacturing edge emission type EL device arrays. A substrate carrying individually formed EL device arrays is coated with a transparent film. The film is etched to form terminals through exposure of the edges of block terminals and to make contact holes reaching an upper electrode layer of the EL devices. The contact holes are then covered with a conductive layer that is etched to form common electrodes conductive to predetermined edge emission type EL devices within each block.

Abstract: A method of printing an image on a substrate by applying to the substrate a film which is chemically activated by heat, and scanning the film by a beam of radiation according to the image to be printed, to chemically activate the film by heat and thereby to produce a pattern in the film according to the image scanned. The film includes a reagent capable of undergoing a redox reaction when heated in the presence of another reagent present with the film when scanned by the beam, to produce the redox reaction between the two reagents.

Abstract: A switching electrode especially for controlling image points in liquid crystal indicators has a ground electrode, a dielectric, and a counterlectrode. Parameters of the switching element are controllable in a broad region independently from one another. The production of the switching element can be easily integrated in production process of a liquid crystal indicator.

Abstract: A positive-type photoresist composition is disclosed, which comprises:(A) an o-quinonediazide compound;(B) an alkali-soluble phenol resin; and(C) at least one compound selected from a group consisting of urea compounds, thiourea compounds and arylamine compounds; A positive-type photoresist composition which comprises:(A) an o-quinonediazide compound;(B) an alkali-soluble phenol resin; and(C) at least one compound selected from a group consisting of urea compounds, thiourea compounds, and arylamine compounds represented by general formulae (I), (II) and (III), respectively, ##STR1## wherein R.sub.1, R.sub.2, R.sub.3, and R.sub.4 each represents a hydrogen atom, an alkyl group, an aryl group, or any two of R.sub.1, R.sub.2, R.sub.3, and R.sub.4 form at least one ring together, ##STR2## wherein R.sub.5, R.sub.6, and R.sub.

Abstract: Longitudinally fine striped type heat seal connector member having a layer of an anisotropic press heat bonding agent which has satisfactory connection and reliable electrical conductivity in height or length direction as well as reliable electrical insulative property in lateral direction is provided by the method of the present invention, which is relatively simple in producing the layer of the anisotropic press heat bonding and which can dispense with some strong alkali or the like etching agent.

Abstract: A process for preparing a printed circuit board. The process involves successive steps of coating a photosensitive electrodeposition coating composition onto a printed-circuit copper-clad, laminated base plate to form a photosensitive resist film, applying a pattern mask onto the photosensitive resist film, exposing to an active light, developing and etching. Also the printed-circuit copper-clad, laminated base plate is subjected to a corrosion preventing treatment after cladding or laminating and prior to the step of coating the electrodeposition coating composition thereonto with a nitrogen-containing heterocyclic compound as a corrosion inhibitor.