Metal Etched Patents (Class 430/318)
  • Patent number: 6268114
    Abstract: A method for forming solder balls that have larger spacings between them and electronic devices containing such solder balls are disclosed. In the method, an additional layer of a leachable metal such as gold or silver is used between an under bump metallurgy layer and a solder bump subsequently formed. This allows the formation of the under bump metallurgy layer prior to the deposition of the solder material into a window formed in a photoresist layer. The present invention allows the underfill of a solder window, instead of an overfill which is normally required in a conventional method.
    Type: Grant
    Filed: September 18, 1998
    Date of Patent: July 31, 2001
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd
    Inventors: Ying-Nan Wen, Ling-Chen Kung, Szu-Wei Lu, Ruoh-Huey Uang
  • Patent number: 6265134
    Abstract: Acid-catalyzed positive photoresist compositions having generally improved performance (especially photoresist compositions having improved contrast (solubility differential), shrinkage and processing kinetics on radiation exposure) are obtained by use of polymers containing pendant polar-functionalized aromatic groups and acid-labile light crosslinking. The photoresist compositions also may contain a photosensitive acid-generating component as well as a solvent and possibly other auxiliary components. The polymers may contain other functional groups or components designed to impart alkaline-solubility, to provide alkaline-solubility protection in the absence of generated acid, etc. The photoresist compositions can be used to create patterned photoresist structures and further to make conductive, semiconductive or insulative structures by photolithography.
    Type: Grant
    Filed: October 30, 2000
    Date of Patent: July 24, 2001
    Assignee: International Business Machines Corporation
    Inventors: Pushkara R. Varanasi, Ahmad D. Katnani, Mahmoud M. Khojasteh, Ranee W. Kwong
  • Publication number: 20010006765
    Abstract: Disclosed is a method for manufacturing a thin film transistor LCD device, in which a counter and a gate bus line are made in a single photolithography process, and a channel of a thin film transistor, a source electrode, a drain electrode, ohmic contacts for the source and drain electrodes are made in a single photolithography process.
    Type: Application
    Filed: December 19, 2000
    Publication date: July 5, 2001
    Inventors: Seok Lyul Lee, Jung Mok Jun, Seung Min Lee
  • Patent number: 6255039
    Abstract: High density built-up multilayer printed circuit boards are produced by constructing microvias with photoimageable dielectric materials. A photosensitive dielectric composition on a conductive foil is laminated to conductive lines on a core. After imaging the foil and imaging and curing the photosensitive dielectric composition, vias are formed to the conductive lines. Thereafter the conductive lines are connected through the vias to the conductive foil, and then the conductive foil is patterned.
    Type: Grant
    Filed: April 3, 1998
    Date of Patent: July 3, 2001
    Assignee: Isola Laminate Systems Corp.
    Inventors: Chengzeng Xu, James T. Yardley, David Haas, Michael Vallance, Jeffrey T. Gotro, Michael A. Petti
  • Patent number: 6251568
    Abstract: The present invention relates to method and apparatus for removing photoresist material from a wafer surface. In particular, the present invention employs a dry strip process to remove photoresist material that remains after conductive material has been etched to form conductive features. The inventive process includes a reactive ion strip process that includes fluorine, which forms salts with conductive material embedded in the photoresist material. The salts are then removed from the wafer surface by dissolving them in a solvent such as deionized water.
    Type: Grant
    Filed: February 9, 1999
    Date of Patent: June 26, 2001
    Assignee: Conexant Systems Inc.
    Inventors: Shao-Wen Hsia, Peter Y. Huang
  • Patent number: 6245490
    Abstract: A first method of manufacturing a printed circuit board includes steps of (a) preparing a board which has a chip mounting area and circuit patterns on an upper surface and metal pads to be electrically connected to the circuit patterns on a lower surface, (b) attaching a metal plate to the lower surface of the board, (c) forming metal patterns on the metal pads by etching the metal plate, and (d) forming metal bumps by plating the metal patterns.
    Type: Grant
    Filed: February 18, 2000
    Date of Patent: June 12, 2001
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin Hyun Yoon, Gi Bum Park, In Pyo Hong, Yong Kim, Myung Kee Chung
  • Patent number: 6238845
    Abstract: The invention is a method for making a lead frame (30) having fine pitched lead frame leads (32). A first side of the lead frame material is etched to for the lead frame and define the lead frame leads and die pad, but the etch process does not etch completely through the lead frame material. The partially etched first side is then covered with a tape (31) or layer of photoresist (71). The second side of the lead fame material is then etched to complete the lead frame. The lead frame may then be plated.
    Type: Grant
    Filed: November 13, 1998
    Date of Patent: May 29, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Paul R. Moehle, Harold T. Kelleher, Gijsbert Willem Lokhorst
  • Patent number: 6232047
    Abstract: The specification describes method for improving the edge acuity of conductive metal strips formed by thick film paste techniques. The advantages of the bulk properties of strips formed using thick film technology are realized while the drawback of poor edge definition is overcome using a thin film trim strip at the edge of the conductive strip.
    Type: Grant
    Filed: March 2, 1999
    Date of Patent: May 15, 2001
    Assignee: Agere Systems Inc.
    Inventors: Robert Charles Frye, Yee Leng Low, King Lien Tai
  • Patent number: 6214525
    Abstract: The invention relates to subtractive and additive processes for creating a circuitized cavity in a printed circuit board. Additionally, the invention includes a circuitized cavity and a printed circuit board with a circuitized cavity. The circuitized cavity provides for a variety of advantages over wire bonds.
    Type: Grant
    Filed: August 24, 1999
    Date of Patent: April 10, 2001
    Assignee: International Business Machines Corp.
    Inventors: Christina Marie Boyko, Donald Seton Farquhar, Robert Maynard Japp, Michael Joseph Klodowski
  • Patent number: 6194127
    Abstract: Pattern transfer process for manufacturing a patterned resistive sheet with reduced process steps, and the resulting article of manufacture.
    Type: Grant
    Filed: May 27, 1998
    Date of Patent: February 27, 2001
    Assignee: McDonnell Douglas Corporation
    Inventors: Richard D. Stolk, William J. Keyes
  • Patent number: 6171763
    Abstract: In one embodiment, the present invention relates to a method of forming a metal line, involving the steps of providing a semiconductor substrate comprising a metal layer, a silicon nitride layer over the metal layer, and an oxide layer over the silicon nitride layer; depositing an ultra-thin photoresist over the oxide layer, the ultra-thin photoresist having a thickness less than about 2,000 Å; irradiating the ultra-thin photoresist with electromagnetic radiation having a wavelength of about 250 nm or less; developing the ultra-thin photoresist exposing a portion of the oxide layer; etching the exposed portion of the oxide layer exposing a portion of the silicon nitride layer; etching the exposed portion of the silicon nitride layer exposing a portion of the metal layer; and etching the exposed portion of the metal layer thereby forming the metal line.
    Type: Grant
    Filed: December 2, 1998
    Date of Patent: January 9, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Fei Wang, Christopher F. Lyons, Khanh B. Nguyen, Scott A. Bell, Harry J. Levinson, Chih Yuh Yang
  • Patent number: 6171762
    Abstract: Polarizing glass having localized regions or patterns of non-polarizing glass is disclosed. The glass is formed by use of reducing gas-blocking material, by local thermal heating of the glass, or by an etching technique.
    Type: Grant
    Filed: May 21, 1999
    Date of Patent: January 9, 2001
    Assignee: Corning Incorporated
    Inventors: Nicholas F. Borrelli, Chad B. Moore, Paul A. Sachenik
  • Patent number: 6169029
    Abstract: A process for fabricating a sub-micron or deep sub-micron semiconductor device on a wafer surface with an improved anti-reflective coating is disclosed. It includes the steps of: (a) depositing an aluminum layer on a wafer surface; (b) depositing an inorganic anti-reflective layer TiN on top of the aluminum layer; (c) depositing a dielectric partitioning layer, typically a polymer layer, on top of the TiN layer; (d) depositing an organic anti-reflective layer on the dielectric partitioning layer; (e) depositing a photoresist on the organic anti-reflective layer; (f) performing a photolithography process to form a photoresist pattern using a deep UV technology in conjunction with a photomask; (g) removing the organic anti-reflective the and the dielectric partitioning layer not covered by the photoresist using an oxide etcher; and (h) removing the TiN layer and the metal layer also not covered by the photoresist using a metal etcher.
    Type: Grant
    Filed: May 3, 1999
    Date of Patent: January 2, 2001
    Assignee: Winband Electronics Corp.
    Inventor: Ching-Sheng Yang
  • Patent number: 6162587
    Abstract: A method of forming a via structure is provided. In the method, a dielectric layer is formed on an anti-reflective coating (ARC) layer covering a first metal layer; and a transition metal layer is formed on the dielectric layer. An ultra-thin photoresist layer is formed on the transition metal layer, and the ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for a via. The patterned ultra-thin photoresist layer is used as a mask during a first etch step to transfer the via pattern to the transition metal layer. The first etch step includes an etch chemistry that is selective to the transition metal layer over the ultra-thin photoresist layer and the dielectric layer. The transition metal layer is employed as a hard mask during a second etch step to form a contact hole corresponding to the via pattern by etching portions of the dielectric layer.
    Type: Grant
    Filed: December 1, 1998
    Date of Patent: December 19, 2000
    Assignee: Advanced Micro Devices
    Inventors: Chih Yuh Yang, Christopher F. Lyons, Harry J. Levinson, Khanh B. Nguyen, Fei Wang, Scott A. Bell
  • Patent number: 6162588
    Abstract: Disclosed are methods for forming a resist pattern which solve a problem (dimensional precision degradation) caused by halation and interference phenomena due to reflected light from the substrate, and which are fine and have high precision even with substrates having high reflectivity or substrates having a transparent film or substrates with an uneven surface. A first method forms between the substrate and resist film an anti-reflective film whose photoabsorbance of the exposure light is greater on the substrate surface side than on the resist surface side. A second method forms between the substrate and resist film a two-layer anti-reflective film made up of an upper-layer film which is an interference film for the exposure light and a lower-layer film which has higher exposure light absorbance than the upper-layer film and functions as a light shielding film.
    Type: Grant
    Filed: November 15, 1999
    Date of Patent: December 19, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Toshihiko Tanaka, Shoichi Uchino, Naoko Asai
  • Patent number: 6162586
    Abstract: Disclosed is a method for making a metallization layered stack over an oxide layer of a semiconductor substrate, and a metallization layered stack that assists in providing superior deep UV photolithography resolution. The method includes forming a bottom titanium nitride layer over the oxide layer, and forming an aluminum metallization layer over the bottom titanium nitride layer. The method further includes forming a top titanium nitride layer over the aluminum metallization layer, such that the forming of the top titanium nitride layer includes: (a) placing the semiconductor substrate in an ionized metal plasma chamber having an RF powered coil and a titanium target; (b) introducing an argon gas and a nitrogen gas into the ionized metal plasma chamber; (c) pressuring up the ionized metal plasma chamber to a pressure of between about 10 mTorr and about 50 mTorr, whereby the top titanium nitride layer is formed as a dense titanium nitride film.
    Type: Grant
    Filed: May 6, 1998
    Date of Patent: December 19, 2000
    Assignee: Philips Electronics North America Corp.
    Inventors: Samit S. Sengupta, Daniel C. Baker, Subhas Bothra
  • Patent number: 6162365
    Abstract: A process for making a printed circuit board is provided. The process employs a noble metal as an etch mask for subtractive circuitization and as a seed layer for secondary finishing. In a preferred embodiment of the invention, a dielectric is covered by a conductive layer of metal such as copper, a patterned photoresist is applied, additional copper is deposited on areas not covered by the photoresist, and a palladium etch mask/seed layer is deposited on the copper. The palladium layer remains sufficiently active for deposition of nickel or gold on the circuitry for purposes such as wire bonding.
    Type: Grant
    Filed: March 4, 1998
    Date of Patent: December 19, 2000
    Assignee: International Business Machines Corporation
    Inventors: Ashwinkumar C. Bhatt, John Gerard Gaudiello
  • Patent number: 6162590
    Abstract: A method for forming a novel head used in magneto-optic or optical disks comprises the steps of forming a diffractive lens on one side of a glass substrate and forming air bearing surface rails on a second side of said glass substrate. The glass substrate is then cut into separate heads. In this way, many magneto-optic or optical heads can be formed simultaneously without incurring the expense of bonding lenses onto a slider. In one embodiment, coils are deposited on the substrate to generate a magnetic field during magneto-optic write operations. In another embodiment, a glass wafer having diffractive lenses formed thereon is bonded to a silicon spacer structure.
    Type: Grant
    Filed: April 13, 1998
    Date of Patent: December 19, 2000
    Assignee: Aerial Imaging Corporation
    Inventors: Barry Block, Arnold Thornton, Walter Daschner
  • Patent number: 6159663
    Abstract: A method for creating a solderable metal layer on a ceramic, glass, or glass ceramic member is described. The described method deposits an aluminum containing mixture on the member by ion vapor deposition creating a metalized ceramic member. A photoresist is applied to the metalized ceramic member. A photomask is applied to the photoresist and the photoresist is exposed to light. After the photomask and exposed photoresist are stripped off, the underlying aluminum containing mixture is removed with an etchant. The remaining photoresist is removed and a metal corrosion inhibiting layer is deposited on the remaining aluminum containing mixture. A solderable layer is then deposited on the metal corrosion inhibiting layer.
    Type: Grant
    Filed: June 30, 1998
    Date of Patent: December 12, 2000
    Assignee: Intersil Corporation
    Inventors: James R. Murray, Sr., Burhan Osmat
  • Patent number: 6159660
    Abstract: A method of forming a number of closely spaced electrodes is described wherein covering the electrodes with a conformal layer of oxide or nitride deposited using plasma enhanced chemical vapor deposition does not result in the formation of restricted regions or keyholes between adjacent electrodes. The method uses de-focussing to form the electrode mask pattern in a layer of photoresist. The focal plane in which the electrode pattern is focussed is positioned a de-focus distance above the layer of photoresist. The de-focus method results in electrodes having a trapezoidal cross section wherein the bottom of the electrode is wider than the top of the electrode. The trapezoidal cross section avoids the formation of restricted regions or keyholes when the electrodes are covered with a conformal dielectric layer, such as a layer of oxide or nitride deposited using plasma enhanced chemical vapor deposition.
    Type: Grant
    Filed: February 3, 1997
    Date of Patent: December 12, 2000
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Hsin-Pai Chen, An-Min Chiang, Pei-Hung Chen
  • Patent number: 6156484
    Abstract: Disclosed is a sculpted probe pad and a gray scale etching process for making arrays of such probe pads on a thin flexible interposer for testing the electrical integrity of microelectronic devices at terminal metallurgy. Also used in the etching process is a novel fixture for holding the substrate and a novel mask for 1-step photolithographic exposure. The result of the invention is an array of test probes of preselected uniform topography, which make ohmic contact at all points to be tested simultaneously and nondestructively.
    Type: Grant
    Filed: February 11, 1998
    Date of Patent: December 5, 2000
    Assignee: International Business Machines Corporation
    Inventors: Ernest Bassous, Gobinda Das, Frank Daniel Egitto, Natalie Barbara Feilchenfeld, Elizabeth F. Foster, Stephen Joseph Fuerniss, James Steven Kamperman, Donald Joseph Mikalsen, Michael Roy Scheuermann, David Brian Stone
  • Patent number: 6156486
    Abstract: A negative pattern is formed to be transparent in the far ultraviolet region including the wavelength 193 nm of an ArF excimer laser and, despite its chemical structure having high dry etching, does not swell and has excellent resolution. An acid-catalyzed reaction is utilized wherein a .gamma.-hydroxy or .delta.-hydroxy carboxylic acid structure is partially or entirely converted to a .gamma.-lactone or .delta.-lactone structure. The negative pattern is developed with an aqueous alkali solution without swelling.
    Type: Grant
    Filed: November 3, 1999
    Date of Patent: December 5, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Hattori, Yuko Tsuchiya, Hiroshi Shiraishi
  • Patent number: 6146814
    Abstract: A polymeric tube for a medical catheter is provided with elongated metal stripes extending lengthwise along the tube by illuminating the exterior surface of the tube patternwise and treating metal responsive to the illumination. The tube may be covered with a photoresist and moved axially past a plurality of light beams while rotating the tube about its axis so as to form a helical pattern. After development of the photoresist, the metal is deposited or removed in a pattern corresponding to the pattern formed in the photoresist, so as to leave helical metallic stripes. The metallic stripes may have varying helical pitch, varying width or both along the length of the tube, and may serve as electrical connectors and physical reinforcements for the tube wall.
    Type: Grant
    Filed: December 24, 1997
    Date of Patent: November 14, 2000
    Inventor: Marcus J. Millet
  • Patent number: 6143476
    Abstract: The present disclosure pertains to a method of patterning a semiconductor device feature which provides for the easy removal of any residual masking layer which remains after completion of a pattern etching process. The method provides for a multi-layered masking structure which includes a layer of high-temperature organic-based masking material overlaid by either a layer of a high-temperature inorganic masking material which can be patterned to provide an inorganic hard mask, or by a layer of high-temperature imageable organic masking material which can be patterned to provide an organic hard mask. The hard masking material is used to transfer a pattern to the high-temperature organic-based masking material, and then the hard masking material is removed. The high-temperature organic-based masking material is used to transfer the pattern to an underlying semiconductor device feature.
    Type: Grant
    Filed: December 12, 1997
    Date of Patent: November 7, 2000
    Assignee: Applied Materials Inc
    Inventors: Yan Ye, Allen Zhao, Peter Chang-Lin Hsieh, Diana Xiaobing Ma
  • Patent number: 6143652
    Abstract: A method for forming a high-quality aluminum-copper alloy pattern over a semiconductor substrate. The method first forms an aluminum-copper alloy layer over a semiconductor substrate, and then performs a rapid thermal processing operation to remelt copper extracts into the alloy bulk. Subsequently, a photoresist layer is formed over the alloy layer. Finally, the alloy layer is etched to transfer the pattern from the photoresist layer to the metallic alloy layer. Unlike a conventional method that can lead to abnormal conduction due to the presence of extracts that are difficult to etch, this invention uses a thermal operation to remove the extracts before etching is conducted. Hence, the masking effect due to etching is mostly prevented.
    Type: Grant
    Filed: April 21, 1998
    Date of Patent: November 7, 2000
    Assignee: United Semiconductor Corporation
    Inventor: Chia-Chieh Yu
  • Patent number: 6143473
    Abstract: A film patterning method using resist as a mask, comprises the steps of forming a film 2 on a substrate 1, coating resist 3 on the film 2, exposing the resist 3, developing the resist 3 by a liquid phase developing solution 4, removing the liquid developing solution 4 from a surface of the film 2, irradiating ultraviolet rays onto the resist 3, which remains on the film 2 by the developing step, in an oxygen containing atmosphere, removing developed residue of the surface of the resist 3 by supplying an alkali aqueous solution 5 to the resist 3 which has remained on the film 2, and forming patterns of the film 2 by etching the film 2 exposed from the resist 3. Accordingly, the unnecessary residue of resist can be removed from the substrate in a short time after the development.
    Type: Grant
    Filed: February 26, 1999
    Date of Patent: November 7, 2000
    Assignee: Fujitsu Limited
    Inventors: Eiichi Hoshino, Masahiko Uraguchi, Toshikatsu Minagawa, Yuuichi Yamamoto, Yukihiro Sato
  • Patent number: 6136515
    Abstract: A method for removing photoresist in a metallization process according to the invention is able to completely remove a photoresist residue remaining on the surface of a metal layer and avoids corrosion of the metal layer. In the method, a heat treatment is performed after patterning the metal layer and before removing the photoresist layer, thereby removing materials which corrode the metal layer. Therefore, corrosion to the metal layer is prevented. Next, the photoresist layer is removed by a wet strip process instead of an oxygen plasma process. As a result, the photoresist residue remaining on the surface of the metal layer cannot be oxidized into an insoluble oxide and can be completely removed.
    Type: Grant
    Filed: August 19, 1998
    Date of Patent: October 24, 2000
    Assignee: United Integrated Circuits Corp.
    Inventor: Hui-Ming Chen
  • Patent number: 6136512
    Abstract: A method is disclosed for forming resistors that are low cost, easy to manufacture and substantially within 5 percent of their desired value. In one aspect of the method, an electrically resistive material, such as nickel, is deposited directly on an insulating layer, such as a substrate. In preferred embodiments a conductive material, such as copper, is then deposited on the resistive material only at a location where a signal trace is desired. Using photo-imaging, signal traces are formed in the conductive and resistive materials. A resistor is created by forming a gap in the conductive material at a location where the resistor is desired. Current is thereby forced to flow through the resistive material at the location of the gap.
    Type: Grant
    Filed: May 26, 1999
    Date of Patent: October 24, 2000
    Assignee: International Business Machines Corporation
    Inventor: Wallace Dean Doeling
  • Patent number: 6127069
    Abstract: Exposure masks and inspection masks for use in the electronics field may be made using laser beams wherein the mask comprises a substrate which is substantially unaffected by exposure to the laser beam and an opaque pattern forming layer on the substrate, which pattern forming layer absorbs the laser beam and is selectively etched when exposed to the laser beam. A preferred mask has an overcoat transparent layer. A cavity inspection mask is provided having a series of openings in the form of lines formed in the opaque pattern forming layer, the lines bounding the cavity walls, is the mask being used for determining if the cavity is centrally positioned on the substrate and/or that the cavity is of the desired size. Substrates containing identifying masks thereon which cannot be seen by the unaided eye for theft deterrence are also provided.
    Type: Grant
    Filed: October 20, 1998
    Date of Patent: October 3, 2000
    Assignee: International Business Machines Corporation
    Inventors: James Gregory Balz, Mark William Kapfhammer, Mark Joseph LaPlante, David C. Long
  • Patent number: 6120693
    Abstract: A metal-clad laminate product including a carrier film, a release agent layer, a semi-transparent metal layer and a photo dielectric layer deposited on the conductive metal layer and a method for using the metal-clad laminate product to form an interlayer via by exposing at least a portion of an circuit board intermediate prepared from the metal-clad laminate product to light through the semi-transparent metal layer for a period of time sufficient to form an exposed or an unexposed photo dielectric portion and thereafter removing the exposed or unexposed portion of the photo dielectric layer and a corresponding portion of the semi-transparent metal layer overlying the exposed or unexposed portion of the photo dielectric layer to form an interlayer via.
    Type: Grant
    Filed: November 6, 1998
    Date of Patent: September 19, 2000
    Assignee: AlliedSignal Inc.
    Inventors: Michael Petti, Gordon C. Smith
  • Patent number: 6114097
    Abstract: A process which vastly improves the 3-D patterning capability of laser pantography (computer controlled laser direct-write patterning). The process uses commercially available electrodeposited photoresist (EDPR) to pattern 3-D surfaces. The EDPR covers the surface of a metal layer conformally, coating the vertical as well as horizontal surfaces. A laser pantograph then patterns the EDPR, which is subsequently developed in a standard, commercially available developer, leaving patterned trench areas in the EDPR. The metal layer thereunder is now exposed in the trench areas and masked in others, and thereafter can be etched to form the desired pattern (subtractive process), or can be plated with metal (additive process), followed by a resist stripping, and removal of the remaining field metal (additive process). This improved laser pantograph process is simpler, faster, move manufacturable, and requires no micro-machining.
    Type: Grant
    Filed: February 13, 1995
    Date of Patent: September 5, 2000
    Assignee: The Regents of the University of California
    Inventors: Vincent Malba, Anthony F. Bernhardt
  • Patent number: 6110650
    Abstract: A method of making a circuitized substrate wherein a chip-accommodating cavity is formed along with a plurality of conductive elements (e.g., pads, lines, etc.) which form part of the substrate's circuitry. Metallization is facilitated by the use of a photoimageable member that allows for initial removal (peeling) of its sacrificial layer, followed by eventual removal of the photoimaging layer which also forms part of this member. Exposure of the photoimaging layer may occur either through the protective sacrificial layer or subsequent removal thereof.
    Type: Grant
    Filed: March 17, 1998
    Date of Patent: August 29, 2000
    Assignee: International Business Machines Corporation
    Inventors: Anilkumar Chinuprasad Bhatt, Thomas Richard Miller, Allen Frederick Moring, James Paul Walsh
  • Patent number: 6110648
    Abstract: A method is disclosed for enclosing copper conductors in a protective material with the use of a modified dual damascene process. This is accomplished in a first embodiment where the dual damascene structure is formed first by forming either a via or contact hole and then a line trench. In the second embodiment, dual damascene copper interconnect is structured by first forming line trench pattern followed by hole pattern thus forming a composite hole and trench structure which is lined with a barrier material to accept copper metal which in turn is capped with a second barrier material in a cavity that is formed by a critical etch-back of the copper metal. It is shown that the method disclosed is applicable and useful to other trenching techniques and that the problems of corrosion and delamination through diffusion of copper are eliminated.
    Type: Grant
    Filed: September 17, 1998
    Date of Patent: August 29, 2000
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Syun-Ming Jang
  • Patent number: 6107003
    Abstract: An alkaline refractory metal which is insoluble in alkaline etching solutions, is electrodeposited on the surface of copper foil, then a thermosetting resin is applied to the surface and semi-cured to obtain a coated copper foil. The coated copper foil is bonded to one or both faces of an inner layer board having wirings on one or both of its faces. Then, the copper foil on a surface of this laminate is removed by alkaline etching, while selectively leaving the alkaline refractory metal layer. A laser beam is used to form via holes in both the alkaline refractory metal layer and the thermosetting resin layer simultaneously. With the above method, via holes of the multi-layered printed wiring board can be easily formed using a laser, and adhesion between the outer wirings made from the plated copper and the insulating resin is improved.
    Type: Grant
    Filed: January 12, 1999
    Date of Patent: August 22, 2000
    Assignee: Mitsui Mining & Smelting Co., Ltd.
    Inventor: Fujio Kuwako
  • Patent number: 6103457
    Abstract: Disclosed is a method for reducing faceting of a photoresist layer during an etch process. The method includes depositing a metallization layer on a semiconductor substrate, and forming a photoresist layer over at least a portion of the metallization layer. The method also includes treating the photoresist layer with a first plasma so as to harden the photoresist layer against a metal etching plasma. The method further includes exposing the metallization layer and the photoresist layer to the metal etching plasma. The metal etching plasma etches the metallization layer at a substantially faster rate than the treated photoresist layer so that faceting on the photoresist layer is substantially reduced.
    Type: Grant
    Filed: May 28, 1998
    Date of Patent: August 15, 2000
    Assignee: Philips Electronics North America Corp.
    Inventor: Calvin T. Gabriel
  • Patent number: 6103134
    Abstract: A method for fabricating circuit board conductors with desirable processing and reduced self and mutual capacitance. The method generally entails forming a metal layer on a positive-acting photodielectric layer formed on a substrate, and then etching the metal layer to form at least two conductor traces that cover two separate regions of the photodielectric layer while exposing a third region of the photodielectric layer between the two regions. The third region of the photodielectric layer is then irradiated and developed using the two traces as a photomask, so that the third region of the photodielectric layer is removed. The two remaining regions of the photodielectric layer masked by the traces remain on the substrate and are separated by an opening formed by the removal of the third dielectric region.
    Type: Grant
    Filed: December 31, 1998
    Date of Patent: August 15, 2000
    Assignee: Motorola, Inc.
    Inventors: Gregory J. Dunn, Larry Lach, Jovica Savic, Allyson Beuhler, Everett Simons
  • Patent number: 6080529
    Abstract: A first embodiment of the present invention pertains to a method of patterning a semiconductor device conductive feature while permitting easy removal of any residual masking layer which remains after completion of the etching process. A multi-layered masking structure is used which includes a layer of high-temperature organic-based masking material overlaid by either a patterned layer of inorganic masking material or by a layer of patterned high-temperature imageable organic masking material. The inorganic masking material is used to transfer a pattern to the high-temperature organic-based masking material and is then removed. The high-temperature organic-based masking material is used to transfer the pattern and then may be removed if desired. This method is also useful in the pattern etching of aluminum, even though aluminum can be etched at lower temperatures.
    Type: Grant
    Filed: October 19, 1998
    Date of Patent: June 27, 2000
    Assignee: Applied Materials, Inc.
    Inventors: Yan Ye, Pavel Ionov, Allen Zhao, Peter Chang-Lin Hsieh, Diana Xiaobing Ma, Chun Yan, Jie Yuan
  • Patent number: 6048666
    Abstract: A radiation sensitive resin composition comprising an alkali-soluble resin such as a polyvinyl phenol or a phenol resin other than a polyvinyl phenol having a weight average molecular weight of 2,000 or higher, a cross-linking agent such as an amino resin having two or more active methylol groups in a molecule, a particulate rubbery material comprising a cross-linked polymer chemically modified with an epoxy compound, a liquid rubbery material having a number average molecular weight between 1,000 and 10,000 and a glass transition temperature of -20.degree. C. or lower, and a radiation polymerization initiator. The composition is best suited for use as a material for preparing an insulating layer interposed between two layers of conductive wiring that are arranged in an overlaying stack.
    Type: Grant
    Filed: June 3, 1998
    Date of Patent: April 11, 2000
    Assignee: JSR Corporation
    Inventors: Kazuaki Niwa, Masako Suzuki, Toshiyuki Ota, Hozumi Sato, Hideki Chiba
  • Patent number: 6045979
    Abstract: A description is given of a method of metallizing an electrically insulating plate, for example, of glass having a large number of holes. Said holes are internally provided with a metal layer and the plate is provided with metal tracks. The metal used is mainly aluminum. The aluminum is coated with a thin protective layer of chromium, cobalt, nickel, zirconium or titanium. Said protective layer makes it possible to use a photosensitve, cataphoretic lacquer for providing the metal layer with a structure. The method can very suitably be used for the manufacture of selection plates for thin electron displays.
    Type: Grant
    Filed: February 2, 1998
    Date of Patent: April 4, 2000
    Assignee: U.S. Philips Corporation
    Inventors: Gijsbertus A.C.M. Spierings, Willem L.C.M. Heijboer, Leo O. Remeeus
  • Patent number: 6042997
    Abstract: The present invention provides novel copolymers and photoresist compositions that contain such copolymers as a resin binder component. Preferred copolymers include three distinct repeating units: 1) units that contain acid-labile groups; 2) units that are free of both reactive and hydroxy moieties; and 3) units that contribute to aqueous developability of a photoresist containing the copolymer as a resin binder. Photoresists of the invention exhibit surprising lithographic improvements including substantially enhanced plasma etch resistance and isolated line performance as well as good dissolution rate control.
    Type: Grant
    Filed: January 23, 1998
    Date of Patent: March 28, 2000
    Assignees: IBM Corporation, Shipley Company, L.L.C.
    Inventors: George G Barclay, Michael F. Cronin, Ronald A. Dellaguardia, James W. Thackeray, Hiroshi Ito, Greg Breyta
  • Patent number: 6043000
    Abstract: A method for manufacturing a liquid crystal display, includes the steps of forming a first metal layer on a transparent substrate, forming a first photo-resist pattern on the first metal layer by using a first mask with a predetermined pattern, forming a gate electrode by etching the first metal layer using the first photo-resist pattern, forming a second metal layer over the gate electrode, forming a second photo-resist pattern on the second metal layer by using a second mask having a line-and-space pattern whose space width is smaller than a resolution of an exposure system, forming source and drain electrodes by etching the second metal layer using the second photo-resist pattern, and forming a transparent conductive material layer for electrically connecting the drain electrode with a pixel electrode.
    Type: Grant
    Filed: February 12, 1997
    Date of Patent: March 28, 2000
    Assignee: LG Electronics
    Inventors: Yong-Seok Park, Jong-Woo Son
  • Patent number: 6040114
    Abstract: A method of forming a pattern for a semiconductor device comprises the steps of forming a photosensitive film on a substrate and radiating the photosensitive film on the substrate with a beam of a predetermined shape consisting of one of a charged particle beam and an electromagnetic beam, thereby forming an exposed region of a desired shape, the latter step including the step of exposing each of unit regions by a single shot of the beam of the predetermined shape for a predetermined period of time, repeating the exposure a plurality of times, and butt-joining the exposed unit regions to thereby form the exposed region of the desired shape, wherein, in the step of forming the exposed region of the desired shape, butting portions of the unit regions are situated in a first area of a layer to be formed other than a second area in the layer in which predetermined characteristics of a function of the semiconductor device are determined by a pattern width of the exposed region in association with another pattern f
    Type: Grant
    Filed: April 23, 1997
    Date of Patent: March 21, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Soichi Inoue, Iwao Higashikawa, Yoji Ogawa, Shigehiro Hara, Kazuko Yamamoto
  • Patent number: 6027860
    Abstract: A method for forming a structure by redepositing a starting material on sidewalls of a foundation during an etch of the starting material.
    Type: Grant
    Filed: June 23, 1998
    Date of Patent: February 22, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Brent A. McClure, Daryl C. New
  • Patent number: 6027862
    Abstract: A description is given of a method of providing an adhesive silver layer on a glass substrate, in which method the glass surface is activated, whereafter a first silver layer is provided from an electroless silver bath and reinforced by means of a second silver layer which is electrodeposited thereon from a cyanide-free bath comprising ammonia as the complexing agent for silver ions. The method can very suitably be used for silver-plating glass plates, as used in thin gas-discharge displays or thin electron displays, for example selection plates or control plates.
    Type: Grant
    Filed: November 19, 1997
    Date of Patent: February 22, 2000
    Assignee: U.S. Philips Corporation
    Inventors: Martin H. Blees, Antonius A. M. Van Weert
  • Patent number: 6020111
    Abstract: In a method of manufacturing a semiconductor device, a first film essentially consisting of silicon is deposited on the surface of a semiconductor substrate. A second film essentially consisting of material having a proper etching selection ratio relative to tungsten is deposited on the first film. A third film essentially consisting of tungsten is deposited on the second film. A resist pattern is formed on the third film. The third film is etched and patterned to the surface of the second film, by using the resist pattern as a mask. The second film is etched to have the same shape as the third film. The first film is etched to have the same shape as the third film. After the step of patterning the third film and before the step of patterning the first film, the resist pattern is heated to a temperature of 80.degree. C. or higher, the semiconductor substrate is exposed in atmospheric air, and the resist pattern is removed.
    Type: Grant
    Filed: March 10, 1998
    Date of Patent: February 1, 2000
    Assignee: Fujitsu Limited
    Inventor: Satoru Mihara
  • Patent number: 6013417
    Abstract: Circuitry is formed on a substrate having at least one plated through-hole employing two different photoresist materials. A first photoresist is applied on a conductive layer located on a substrate and is developed to define a desired conductive circuit pattern. A second photoresist is laminated onto the structure and is developed so that the second photoresist material remains in the vicinity of the through-hole. The conductive layer is etched to provide the desired circuit pattern, and the remaining portions of the second and first photoresists are removed.
    Type: Grant
    Filed: April 2, 1998
    Date of Patent: January 11, 2000
    Assignee: International Business Machines Corporation
    Inventors: Robert David Sebesta, James Warren Wilson
  • Patent number: 5994225
    Abstract: A method for etching metal which can increase the metal-to-photoresist etching selectivity of a metal layer aimed to be etched with respect to a photoresist layer overlaying the metal layer. The method includes a first step of forming a cap oxide layer over the metal layer; a second step of forming a photoresist layer with a desired pattern over the cap oxide layer; a third step of conducting an ion implantation process on the photoresist layer; and a final step of conducting an etching process on the semiconductor wafer by using the photoresist layer as a mask so as to etch away exposed portions of the metal layer that are uncovered by the photoresist layer. Through experiments, it is found that the invention provides a significantly improved etching selectivity over the prior art.
    Type: Grant
    Filed: October 18, 1996
    Date of Patent: November 30, 1999
    Assignee: United Microelectronics Corp.
    Inventors: Ming-Tsung Liu, Tsung-Yuan Hung, Bill Hsu
  • Patent number: 5985521
    Abstract: A method for fabricating a chip carrier, such as a printed circuit board, which includes at least one through hole or via hole, is disclosed. In accordance with this method, an electrically conductive layer is formed on at least one of the major surfaces of the corresponding chip carrier substrate, as well as for the surface of the through hole or via hole. Significantly, the electrically conductive layer on the at least one major surface is relatively thin, which permits the formation of a relatively high density of circuit lines in this layer. On the other hand, the electrically conductive layer on the surface of the through hole or via hole is relatively thick, which prevents the formation of defects in this layer.
    Type: Grant
    Filed: December 30, 1996
    Date of Patent: November 16, 1999
    Assignee: International Business Machines Corporation
    Inventors: Yasuo Hirano, Yoshiyuki Naitoh, Shigeaki Yamashita
  • Patent number: 5985520
    Abstract: A method for forming a metal line structure comprising the steps of providing a semiconductor substrate, and then sequentially forming a metallic layer and an insulating layer over the substrate. Next, photolithographic and etching processes are performed to create a pattern on the insulating layer exposing portions of the metallic layer and forming insulating lines. Then, spacers are formed on the sidewalls of the insulating lines. Thereafter, the metal layer is etched using the insulating lines and the spacers as masks, and the substrate as an etching stop layer. The metal etching also removes the insulating lines. Thus, the top surface of the metallic layer is exposed and the metal line structure that has the characteristic sloping sidewalls of this invention is formed. These outward sloping sidewalls of the metal lines form slanted edges with the semiconductor substrate, and provide a good step coverage for subsequently deposited layer.
    Type: Grant
    Filed: December 29, 1997
    Date of Patent: November 16, 1999
    Assignee: Winbond Electronics Corp.
    Inventor: Ming-Lun Chang
  • Patent number: 5985518
    Abstract: A method for fabricating custom integrated circuits includes the steps of 1) patterning the layer to be customized with standard precision masking techniques to define all possible connections, vias or cut-points, and 2) using a non-precision targeting energy beam to select the desired connections, vias or cut-points for customization. Consequently, the present invention requires no custom mask so that application specific integrated circuits (ASICs) can be produced with lower lead-time and costs when compared to prior methods. In other embodiments, a non-precision configuration mask may replace the targeting energy beam, where the configuration mask can be made by conventional mask-making techniques or by applying an opaque layer to a mask blank and using a targeting energy beam to selectively remove the desired portions of the opaque areas.
    Type: Grant
    Filed: March 24, 1997
    Date of Patent: November 16, 1999
    Assignee: Clear Logic, Inc.
    Inventors: Alan H. Huggins, John MacPherson