Abstract: A first oxide insulating film is formed over a substrate. After a first oxide semiconductor film is formed over the first oxide insulating film, heat treatment is performed, so that hydrogen contained in the first oxide semiconductor film is released and part of oxygen contained in the first oxide insulating film is diffused into the first oxide semiconductor film. Thus, a second oxide semiconductor film with reduced hydrogen concentration and reduced oxygen defect is formed. Then, the second oxide semiconductor film is selectively etched to form a third oxide semiconductor film, and a second oxide insulating film is formed. The second oxide insulating film is selectively etched and a protective film covering an end portion of the third oxide semiconductor film is formed. Then, a pair of electrodes, a gate insulating film, and a gate electrode are formed over the third oxide semiconductor film and the protective film.

Abstract: When a transistor having bottom gate bottom contact structure is manufactured, for example, a conductive layer constituting a source and a drain has a three-layer structure and two-step etching is performed. In the first etching process, an etching method in which the etching rates for at least the second film and the third film are high is employed, and the first etching process is performed until at least the first film is exposed. In the second etching process, an etching method in which the etching rate for the first film is higher than that in the first etching process and the etching rate for a “layer provided below and in contact with the first film” is lower than that in the first etching process is employed. The side wall of the second film is slightly etched when a resist mask is removed after the second etching process.

Abstract: An object is to reduce to reduce variation in threshold voltage to stabilize electric characteristics of thin film transistors each using an oxide semiconductor layer. An object is to reduce an off current. The thin film transistor using an oxide semiconductor layer is formed by stacking an oxide semiconductor layer containing insulating oxide over the oxide semiconductor layer so that the oxide semiconductor layer and source and drain electrode layers are in contact with each other with the oxide semiconductor layer containing insulating oxide interposed therebetween; whereby, variation in threshold voltage of the thin film transistors can be reduced and thus the electric characteristics can be stabilized. Further, an off current can be reduced.

Abstract: A method of manufacturing silver (Ag)-doped zinc oxide (ZnO) nanowires and a method of manufacturing an energy conversion device are provided. In the method of manufacturing Ag-doped ZnO nanowires, the Ag-doped nanowires are grown by a low temperature hydrothermal synthesis method using a Ag-containing aqueous solution.

Abstract: A resistive random access memory (ReRAM) cell comprising a first conductive electrode and a dielectric storage material layer over the first conductive electrode. The dielectric storage material layer is conducive to the formation of conductive filaments during the application of a filament forming voltage to the cell. The cell includes a second conductive electrode over the dielectric storage material layer and a layer of conductive nanoclusters (911, 1211) including a plurality of nanoclusters in contact with the dielectric storage material layer and in contact with the first conductive electrode or the second conductive electrode.

Abstract: The present invention provides a highly reliable circuit board that includes TFTs a semiconductor layer of which is formed from an oxide semiconductor; and low-resistance aluminum wirings. The circuit board of the present invention includes an oxide semiconductor layer; source wirings; and drain wirings, wherein each of the source wirings and the drain wirings includes a portion in contact with the semiconductor layer, portions of the source wirings in contact with the semiconductor layer and respective portions of the drain wirings in contact with the semiconductor layer spacedly facing each other, and the source wirings and the drain wirings are formed by stacking a layer formed from a metal other than aluminum and a layer containing aluminum.

Abstract: An embodiment is a semiconductor device which includes a first oxide semiconductor layer over a substrate having an insulating surface and including a crystalline region formed by growth from a surface of the first oxide semiconductor layer toward an inside; a second oxide semiconductor layer over the first oxide semiconductor layer; a source electrode layer and a drain electrode layer which are in contact with the second oxide semiconductor layer; a gate insulating layer covering the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer; and a gate electrode layer over the gate insulating layer and in a region overlapping with the second oxide semiconductor layer. The second oxide semiconductor layer is a layer including a crystal formed by growth from the crystalline region.

Abstract: A nonvolatile memory element includes a first electrode, a second electrode, and a variable resistance layer positioned between the first electrode and the second electrode. The variable resistance layer has a resistance state which reversibly changes based on an electrical signal applied between the first electrode and the second electrode. The variable resistance layer includes a first variable resistance layer having a first metal oxide and a second variable resistance layer having a second metal oxide. The second variable resistance layer includes a metal-metal bonding region including a metal bond of metal atoms included in the second metal oxide, and the second metal oxide has a low degree of oxygen deficiency and a high resistance value compared to the first metal oxide.

Abstract: A semiconductor device in which a defect is suppressed and miniaturization is achieved is provided.

Abstract: An object of the invention is to provide a TFT substrate and a method for producing a TFT substrate which is capable of drastically reducing the production cost by decreasing the number of steps in the production process and improving production yield. A TFT substrate comprises: a substrate; a first oxide layer formed above the substrate; a second oxide layer formed above the first oxide layer with a channel part interposed therebetween; gate insulating film formed above the substrate, the first oxide layer and the second oxide layer; a gate electrode and a gate wire formed above the gate insulating film.

Abstract: A process for manufacturing indium tin oxide (ITO) sputtering targets as described. The process includes the precipitation of indium and tin hydroxides, sintering in the absence of chloride ions, using the resultant oxide powders to prepare an aqueous slip with dispersing agent, binder, special high density promoting agents and compacting the slip in a specially surface coated porous mold using the method of slip casting followed by sintering the resultant compacted target body to yield high density ITO target.

Abstract: Semiconductor structures including a zirconium oxide material and methods of forming the same are described herein. As an example, a semiconductor structure can include a zirconium oxide material, a perovskite structure material, and a noble metal material formed between the zirconium oxide material and the perovskite structure material.

Abstract: A thin film transistor includes a semiconductor layer disposed on a base substrate and including an oxide semiconductor material, a source electrode and a drain electrode, which respectively extend from opposing ends of the semiconductor layer, a plurality of low carrier concentration areas respectively disposed between the source electrode and the semiconductor layer and between the drain electrode and the semiconductor layer, a gate insulating layer disposed on the semiconductor layer, and a gate electrode disposed on the gate insulating layer.

Abstract: A larger substrate can be used, and a transistor having a desirably high field-effect mobility can be manufactured through formation of an oxide semiconductor layer having a high degree of crystallinity, whereby a large-sized display device, a high-performance semiconductor device, or the like can be put into practical use. A first multi-component oxide semiconductor layer is formed over a substrate and a single-component oxide semiconductor layer is formed thereover; then, crystal growth is carried out from a surface to an inside by performing heat treatment at 500° C. to 1000° C. inclusive, preferably 550° C. to 750° C. inclusive so that a first multi-component oxide semiconductor layer including single crystal regions and a single-component oxide semiconductor layer including single crystal regions are formed; and a second multi-component oxide semiconductor layer including single crystal regions is stacked over the single-component oxide semiconductor layer including single crystal regions.

Abstract: Oxygen vacancies in an oxide semiconductor film and the vicinity of the oxide semiconductor film are reduced and electric characteristics of a transistor including the oxide semiconductor film are improved. Further, a highly reliable semiconductor device including the transistor including the oxide semiconductor film is provided. In the transistor including the oxide semiconductor film, at least one insulating film in contact with the oxide semiconductor film contains excess oxygen. By the excess oxygen included in the insulating film in contact with the oxide semiconductor film, oxygen vacancies in the oxide semiconductor film and the vicinity of the oxide semiconductor film can be reduced. Note that the insulating film including the excess oxygen has a profile of the excess oxygen concentration having two or more local maximum values in the depth direction.

Abstract: Disclosed herein is an aqueous alkaline etching solution comprising water and an alkaline material being selected from the group consisting of ammonium hydroxide, ammonium phosphate, ammonium carbonate, quaternary ammonium hydroxide, quaternary ammonium phosphate, quaternary ammonium carbonate, an alkali metal hydroxide, an alkaline earth metal hydroxide, or a combination comprising at least one of the foregoing alkaline materials; the aqueous alkaline solution being operative to etch aluminum oxide at a rate greater than or equal to about 2:1 over a rate at which it etches a metal oxide semiconductor to be protected; wherein the aqueous etching solution has a pH of 8 to 13.

Abstract: The present invention provides for new ohmic contact materials and diffusion barriers for Group IBIIIAVIA based solar cell structures, which eliminate two way diffusion while preserving the efficient ohmic contacts between the substrate and the absorber layers.

Abstract: An object is to provide a semiconductor device having a structure in which parasitic capacitance between wirings can be efficiently reduced. In a bottom gate thin film transistor using an oxide semiconductor layer, an oxide insulating layer used as a channel protection layer is formed above and in contact with part of the oxide semiconductor layer overlapping with a gate electrode layer, and at the same time an oxide insulating layer covering a peripheral portion (including a side surface) of the stacked oxide semiconductor layer is formed. Further, a source electrode layer and a drain electrode layer are formed in a manner such that they do not overlap with the channel protection layer. Thus, a structure in which an insulating layer over the source electrode layer and the drain electrode layer is in contact with the oxide semiconductor layer is provided.

Abstract: Miniaturized transistors having high and stable electric characteristics using high precision microfabrication are provided with high yield. Further, high performance, high reliability, and high productivity also of a semiconductor device including the transistor are achieved. A semiconductor device includes a vertical transistor in which a first electrode layer, a first oxide film containing indium, gallium, zinc, and nitrogen as main components, an oxide semiconductor film containing indium, gallium, and zinc as main components, a second oxide film containing indium, gallium, zinc, and nitrogen as main components, and a second electrode layer are stacked in this order, and a first gate insulating film and a first gate electrode layer are provided at one side of the columnar oxide semiconductor film and a second gate insulating film and a second gate electrode layer are provided at the other side of the columnar oxide semiconductor film.

Abstract: A semiconductor device in which fluctuation in electric characteristics due to miniaturization is less likely to be caused is provided. The semiconductor device includes an oxide semiconductor film including a first region, a pair of second regions in contact with side surfaces of the first region, and a pair of third regions in contact with side surfaces of the pair of second regions; a gate insulating film provided over the oxide semiconductor film; and a first electrode that is over the gate insulating film and overlaps with the first region. The first region is a CAAC oxide semiconductor region. The pair of second regions and the pair of third regions are each an amorphous oxide semiconductor region containing a dopant. The dopant concentration of the pair of third regions is higher than the dopant concentration of the pair of second regions.

Abstract: To provide a miniaturized transistor having favorable electric characteristics. An oxide semiconductor layer is formed to cover a source electrode layer and a drain electrode layer, and then regions of the oxide semiconductor layer which overlap with the source electrode layer and the drain electrode layer are removed by polishing. Precise processing can be performed accurately because an etching step using a resist mask is not performed in the step of removing the regions of the oxide semiconductor layer overlapping with the source electrode layer and the drain electrode layer. Further, a sidewall layer having conductivity is provided on a side surface of a gate electrode layer in a channel length direction; thus, the sidewall layer having conductivity overlaps with the source electrode layer or the drain electrode layer with a gate insulating layer provided therebetween, and a transistor substantially including an Lov region is provided.

Abstract: Memory devices are described along with methods for manufacturing and methods for operating. A memory device as described herein includes a plurality of memory cells located between word lines and bit lines. Memory cells in the plurality of memory cells comprise a diode and a metal-oxide memory element programmable to a plurality of resistance states including a first and a second resistance state, the diode of the memory element arranged in electrical series along a current path between a corresponding word line and a corresponding bit line. The device further includes bias circuitry to apply bias arrangements across the series arrangement of the diode and the memory element of a selected memory cell in the plurality of memory cells.

Abstract: A highly reliable semiconductor device which is formed using an oxide semiconductor and has stable electric characteristics is provided. A semiconductor device which includes an amorphous oxide semiconductor layer including a region containing oxygen in a proportion higher than that in the stoichiometric composition, and an aluminum oxide film provided over the amorphous oxide semiconductor layer is provided. The amorphous oxide semiconductor layer is formed as follows: oxygen implantation treatment is performed on a crystalline or amorphous oxide semiconductor layer which has been subjected to dehydration or dehydrogenation treatment, and then thermal treatment is performed on the oxide semiconductor layer provided with an aluminum oxide film at a temperature lower than or equal to 450° C.

Abstract: An oxide thin film transistor structure includes a substrate, a drain electrode disposed on the substrate, and a first insulation layer disposed on the drain electrode and the substrate. The first insulation layer has a first opening to expose a part of the drain electrode. A gate electrode and a gate insulation layer are sequentially disposed on the first insulation layer and located around the first opening. A metal oxide channel layer is disposed on the gate insulation layer and located in the first opening. A source electrode is disposed on the metal oxide channel layer. An area of the metal oxide channel layer corresponding to the first opening is a channel region.

Abstract: A method for producing a p-type ZnO based compound semiconductor layer including the steps of (a) supplying (i) Zn, (ii) O, (iii) optional Mg, and (iv) a Group 11 element which is Cu and/or Ag to form a MgxZn1-xO (0?x?0.6) single crystal film doped with the Group 11 element; (b) supplying at least one Group 13 element selected from the group consisting of B, Ga, Al, and In on the MgxZn1-xO (0?x?0.6) single crystal film; (c) alternately carrying out the steps (a) and (b) to form a laminate structure; and (d) annealing the laminate structure to form a p-type MgxZn1-xO (0?x?0.6) layer co-doped with the Group 11 element and the Group 13 element.

Abstract: According to embodiments of the present invention, there are provided a TFT array substrate, a method for manufacturing the TFT array substrate and an electronic device.

Abstract: An object is to provide a display device with excellent display characteristics, where a pixel circuit and a driver circuit provided over one substrate are formed using transistors which have different structures corresponding to characteristics of the respective circuits. The driver circuit portion includes a driver circuit transistor in which a gate electrode layer, a source electrode layer, and a drain electrode layer are formed using a metal film, and a channel layer is formed using an oxide semiconductor. The pixel portion includes a pixel transistor in which a gate electrode layer, a source electrode layer, and a drain electrode layer are formed using an oxide conductor, and a semiconductor layer is formed using an oxide semiconductor. The pixel transistor is formed using a light-transmitting material, and thus, a display device with higher aperture ratio can be manufactured.

Abstract: The present invention makes it possible to increase the selectivity of a gate insulation film in an active element formed in a wiring layer. A semiconductor device according to the present invention has a bottom gate type transistor using an antireflection film formed over an Al wire in a wiring layer as a gate wire.

Abstract: A thin film transistor including a first insulating layer disposed on a substrate and having a first hole; a second insulating layer disposed on the substrate and having a second hole; a gate insulating layer disposed between the first and second insulating layers; a gate electrode formed in the first hole; a source electrode and second drain electrode formed at both sides of an inner portion of the second hole; and an activated layer formed between the source electrode and the second drain electrode of the inner portion of the second hole, and having a planarization layer.

Abstract: A thin film transistor array panel including a substrate; a channel region disposed on the substrate and including oxide semiconductor disposed on the substrate; a source electrode and a drain electrode connected to the oxide semiconductor and facing each other at both sides, centered on the oxide semiconductor; an insulating layer disposed on the oxide semiconductor; and a gate electrode disposed on the insulating layer. The drain electrode includes a first drain region and a second drain region; the charge mobility of the first drain region is greater than that of the second drain region, the source electrode includes a first source region and a second source region, and the charge mobility of the first source region is greater than that of the second source region.

Abstract: The present invention relates to an etchant and an etching process, which are preferred for use in etching of oxides containing at least indium and gallium, such as an oxide consisting of indium, gallium and oxygen or an oxide consisting of indium, gallium, zinc and oxygen. According to preferred embodiments of the present invention, an etchant comprising sulfuric acid or a salt thereof and a carboxylic acid (except for oxalic acid) or a salt thereof ensures a preferred etching rate, a good residue removal property and low corrosiveness to wiring materials when used in etching of oxides containing at least indium and gallium. Moreover, this etchant not only causes no precipitate but also retains a preferred etching rate even when the concentration of oxides dissolved in the etchant is elevated.

Abstract: A semiconductor device with high aperture ratio is provided. The semiconductor device includes a transistor and a capacitor having a pair of electrodes. An oxide semiconductor layer formed over the same insulating surface is used for a channel formation region of the transistor and one of the electrodes of the capacitor. The other electrode of the capacitor is a transparent conductive film. One electrode of the capacitor is electrically connected to a wiring formed over the insulating surface over which a source electrode or a drain electrode of the transistor is provided, and the other electrode of the capacitor is electrically connected to one of the source electrode and the drain electrode of the transistor.

Abstract: A semiconductor device with high aperture ratio is provided. The semiconductor device includes a nitride insulating film, a transistor over the nitride insulating film, and a capacitor including a pair of electrodes over the nitride insulating film. An oxide semiconductor layer is used for a channel formation region of the transistor and one of the electrodes of the capacitor. A transparent conductive film is used for the other electrode of the capacitor. One electrode of the capacitor is in contact with the nitride insulating film, and the other electrode of the capacitor is electrically connected to one of a source electrode and a drain electrode of the transistor.

Abstract: According to example embodiments, a variable resistance memory device include an ohmic pattern on a substrate; a first electrode pattern including a first portion that has a plate shape and contacts a top surface of the ohmic pattern and a second portion that extends from one end of the first portion to a top; a variable resistance pattern electrically connected to the first electrode pattern; and a second electrode pattern electrically connected to the variable resistance pattern, wherein one end of the ohmic pattern and the other end of the first portion are disposed on the same plane.

Abstract: One embodiment is a method for manufacturing a stacked oxide material, including the steps of forming a first oxide component over a base component, causing crystal growth which proceeds from a surface toward an inside of the first oxide component by first heat treatment to form a first oxide crystal component at least partly in contact with the base component, forming a second oxide component over the first oxide crystal component; and causing crystal growth by second heat treatment using the first oxide crystal component as a seed to form a second oxide crystal component.

Abstract: Dielectric layers containing a zirconium-doped tantalum oxide layer, where the zirconium-doped tantalum oxide layer can be formed of one or more monolayers of tantalum oxide doped with zirconium, provide an insulating layer in a variety of structures for use in a wide range of electronic devices.

Abstract: Improved chalcogenide solutions are provided. In one aspect, a method of forming an aqueous selenium-containing solution is provided. The method includes the following step. Water, ammonium hydroxide, elemental selenium, and elemental aluminum are contacted under conditions sufficient to form the aqueous selenium-containing solution. The conditions may include sonication for a period of time of from about 1 minute to about 10 minutes and/or stirring for a period of time of from about 10 minutes to about 72 hours at a temperature of from about 20° C. to about 25° C. A method of fabricating a photovoltaic device is also provided.

Abstract: A thin film transistor including an oxide semiconductor with favorable electrical characteristics is provided. The thin film transistor includes a gate electrode provided over a substrate, a gate insulating film provided over the gate electrode, an oxide semiconductor film provided over the gate electrode and on the gate insulating film, a metal oxide film provided on the oxide semiconductor film, and a metal film provided on the metal oxide film. The oxide semiconductor film is in contact with the metal oxide film, and includes a region whose concentration of metal is higher than that of any other region in the oxide semiconductor film (a high metal concentration region). In the high metal concentration region, the metal contained in the oxide semiconductor film may be present as a crystal grain or a microcrystal.

Abstract: Provided are resistive random access memory (ReRAM) cells that include thin resistive switching layers. In some embodiments, the resistive switching layers have a thickness of less than about 50 Angstroms and even less than about 30 Angstroms. The resistive switching characteristics of such thin layers are maintained by controlling their compositions and using particular fabrication techniques. Specifically, low oxygen vacancy metal oxides, such as tantalum oxide, may be used. The concentration of oxygen vacancies may be less than 5 atomic percent. In some embodiments, the resistive switching layers also include nitrogen and. For example, compositions of some specific resistive switching layers may be represented by Ta2O5-XNY, where Y<(X?0.01). The resistive switching layers may be formed using Atomic Layer Deposition (ALD).

Abstract: Anisotropic materials, such as rutile TiO2, can exhibit dielectric constant of 170 along the tetragonal axis of (001) direction, and dielectric constant of 86 along directions perpendicular to the tetragonal axis. Layer of anisotropic material nanorods, such as TiO2 nanorods, can form a seed layer to grow a dielectric layer that can exhibit the higher dielectric constant value in a direction parallel to the substrate surface. The anisotropic layer can then be patterned to expose a surface normal to the high dielectric constant direction. A conductive material can be formed in contact with the exposed surface to create an electrode/dielectric stack along the direction of high dielectric constant.

Abstract: A method for manufacturing an oxide semiconductor layer includes following steps: providing a substrate; forming an oxide semiconductor layer on the substrate by sputtering a first kind of metallic ions from a first metallic oxide sputtering target, and sputtering at least two second kinds of metallic ions from a second metallic oxide sputtering target. The at least two second kind of metallic ions are different from the first kind of metallic ions. A proportion of the first kind of metallic ions and the at least two second kind of metallic ions is adjustable by controlling a depositing speed of the oxide semiconductor layer and a period of using a baffle plate in sputtering. A method for manufacturing a thin film transistor is also provided.

Abstract: An object is to manufacture a semiconductor device including an oxide semiconductor at low cost with high productivity in such a manner that a photolithography process is simplified by reducing the number of light-exposure masks In a method for manufacturing a semiconductor device including a channel-etched inverted-staggered thin film transistor, an oxide semiconductor film and a conductive film are etched using a mask layer formed with the use of a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. In etching steps, a first etching step is performed by wet etching in which an etchant is used, and a second etching step is performed by dry etching in which an etching gas is used.

Abstract: Provided are resistive random access memory (ReRAM) cells including resistive switching layers and thermally isolating structures for limiting heat dissipation from the switching layers during operation. Thermally isolating structures may be positioned within a stack or adjacent to the stack. For example, a stack may include one or two thermally isolating structures. A thermally isolating structure may directly interface with a switching layer or may be separated by, for example, an electrode. Thermally isolating structures may be formed from materials having a thermal conductivity of less than 1 W/m*K, such as porous silica and mesoporous titanium oxide. A thermally isolating structure positioned in series with a switching layer generally has a resistance less than the low resistance state of the switching layer. A thermally isolating structure positioned adjacent to a switching layer may have a resistance greater than the high resistance state of the switching layer.

Abstract: Provided are radiation enhanced resistive switching layers, resistive random access memory (ReRAM) cells including these layers, as well as methods of forming these layers and cells. Radiation creates defects in resistive switching materials that allow forming and breaking conductive paths in these materials thereby improving their resistive switching characteristics. For example, ionizing radiation may break chemical bonds in various materials used for such a layer, while non-ionizing radiation may form electronic traps. Radiation power, dozing, and other processing characteristics can be controlled to generate a distribution of defects within the resistive switching layer. For example, an uneven distribution of defects through the thickness of a layer may help with lowering switching voltages and/or currents. Radiation may be performed before or after thermal annealing, which may be used to control distribution of radiation created defects and other types of defects in resistive switching layers.

Abstract: A thin film transistor array panel may include a channel layer including an oxide semiconductor and formed in a semiconductor layer, a source electrode formed in the semiconductor layer and connected to the channel layer at a first side, a drain electrode formed in the semiconductor layer and connected to the channel layer at an opposing second side, a pixel electrode formed in the semiconductor layer in a same portion of the semiconductor layer as the drain electrode, an insulating layer disposed on the channel layer, a gate line including a gate electrode disposed on the insulating layer, a passivation layer disposed on the source and drain electrodes, the pixel electrode, and the gate line, and a data line disposed on the passivation layer. A width of the channel layer may be substantially equal to a width of the pixel electrode in a direction parallel to the gate line.

Abstract: Some embodiments include methods of forming semiconductor constructions. Carbon-containing material is formed over oxygen-sensitive material. The carbon-containing material and oxygen-sensitive material together form a structure having a sidewall that extends along both the carbon-containing material and the oxygen-sensitive material. First protective material is formed along the sidewall. The first protective material extends across an interface of the carbon-containing material and the oxygen-sensitive material, and does not extend to a top region of the carbon-containing material. Second protective material is formed across the top of the carbon-containing material, with the second protective material having a common composition to the first protective material. The second protective material is etched to expose an upper surface of the carbon-containing material. Some embodiments include semiconductor constructions, memory arrays and methods of forming memory arrays.

Abstract: A ZnO-based semiconductor device includes an n type ZnO-based semiconductor layer, an aluminum oxide film formed on the n type ZnO-based semiconductor layer, and a palladium layer formed on the aluminum oxide film. With this configuration, the n type ZnO-based semiconductor layer and the palladium layer form a Schottky barrier structure.

Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

Abstract: A memristor includes a first electrode; a second electrode; and a switching layer interposed between the first electrode and the second electrode, wherein the switching layer includes an electrically semiconducting or nominally insulating and weak ionic switching mixed metal oxide phase for forming at least one switching channel in the switching layer. A method of forming the memristor is also provided.

Abstract: The present invention discloses a thin film transistor (TFT), an array substrate, and fabrication methods thereof, and a display device. The TFT includes a gate, an oxide active layer, a source, and a drain formed on a substrate, wherein a source and drain transition layer is provided between the oxide active layer and the source, the drain. One patterning process is reduced and one mask process is saved through forming the source and drain transition layer between the oxide active layer and the source, the drain, thus effectively simplifying the fabrication procedure. At the same time, the additionally provided source and drain transition layer may prevent the oxide active layer from being corroded during etching, also effectively reduce threshold voltage (Vth) drift of the TFT, improve Ion (on-state current)/Ioff (off-state current), and enhance thermal stability.