Having Metal Oxide Or Copper Sulfide Compound Semiconductor Component Patents (Class 438/104)
  • Publication number: 20140306220
    Abstract: To provide a novel semiconductor device in which a reduction in channel length is controlled. The semiconductor device includes an oxide semiconductor layer having a crystal part, and a source electrode layer and a drain electrode layer which are in contact with the oxide semiconductor layer. The oxide semiconductor layer includes a channel formation region and an n-type region in contact with the source electrode layer or the drain electrode layer. The crystal orientation of the crystal part is different between the channel formation region and the n-type region.
    Type: Application
    Filed: April 7, 2014
    Publication date: October 16, 2014
    Inventors: Junichi KOEZUKA, Kenichi OKAZAKI, Masahiro TAKAHASHI, Takuya MATSUO, Shigeyasu MORI, Yosuke KANZAKI, Hiroshi MATSUKIZONO
  • Publication number: 20140308777
    Abstract: A semiconductor device including an oxide semiconductor with stable electric characteristics and high reliability is provided. An island-shaped oxide semiconductor layer is formed by using a resist mask, the resist mask is removed, oxygen is introduced (added) to the oxide semiconductor layer, and heat treatment is performed. The removal of the resist mask, introduction of the oxygen, and heat treatment are performed successively without exposure to the air. Through the oxygen introduction and heat treatment, impurities such as hydrogen, moisture, a hydroxyl group, or hydride are intentionally removed from the oxide semiconductor layer, whereby the oxide semiconductor layer is highly purified. Chlorine may be introduced to an insulating layer over which the oxide semiconductor layer is formed before formation of the oxide semiconductor layer.
    Type: Application
    Filed: June 26, 2014
    Publication date: October 16, 2014
    Inventor: Shunpei YAMAZAKI
  • Publication number: 20140306216
    Abstract: A thin film transistor array panel includes an insulation substrate; a gate line and a data line on the insulation substrate; a first passivation layer on the gate line and the data line; an organic layer on the first passivation layer; a first electrode on the organic layer; a second passivation layer on the first electrode; and a second electrode on the second passivation layer. An edge of the organic layer is exposed by the first electrode.
    Type: Application
    Filed: March 19, 2014
    Publication date: October 16, 2014
    Applicant: Samsung Display Co., Ltd.
    Inventors: Seul-Ki KIM, Seung Jin KIM, Jae-Hyun PARK, Jeong Wook HEO
  • Patent number: 8859327
    Abstract: According to one embodiment, a non-volatile semiconductor memory device includes: a semiconductor substrate; a plurality of first lines; a plurality of second lines; and a plurality of non-volatile memory cells arranged at positions where the plurality of first lines intersect with the plurality of second lines, wherein each of the plurality of non-volatile memory cells includes a resistance change element and a rectifying element connected in series to the resistance change element, and a resistance change film continuously extending over the plurality of second lines is arranged between the plurality of first lines and the plurality of second lines, and the resistance change element includes a portion where the first line intersect with the second line in the resistance change film.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: October 14, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki Nansei
  • Patent number: 8859312
    Abstract: A method of manufacturing an integrated circuit (IC) for driving a flexible display includes depositing a pattern of spatially non-repetitive features in a first layer on a flexible substrate, said pattern of spatially non-repetitive features not substantially regularly repeating in both of two orthogonal directions (x,y) in the plane of the substrate; depositing a pattern of spatially repetitive features in a second layer on said first layer; aligning said second layer and said first layer so as to allow electrical coupling between said non-repetitive features and said repetitive features, wherein distortion compensation is applied during deposition of said repetitive features to enable said alignment.
    Type: Grant
    Filed: October 1, 2007
    Date of Patent: October 14, 2014
    Assignee: Plastic Logic Limited
    Inventors: Carl Hayton, Paul A. Cain
  • Patent number: 8859331
    Abstract: Methods of forming an oxide material layer are provided. The method includes mixing a precursor material with a peroxide material to form a precursor solution, coating the precursor solution on a substrate, and baking the coated precursor solution.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: October 14, 2014
    Assignee: Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Hyun Jae Kim, Dong Lim Kim, Joohye Jung, You Seung Rim
  • Patent number: 8860023
    Abstract: Reducing hydrogen concentration in a channel formation region of an oxide semiconductor is important in stabilizing threshold voltage of a transistor including an oxide semiconductor and improving reliability. Hence, hydrogen is attracted from the oxide semiconductor and trapped in a region of an insulating film which overlaps with a source region and a drain region of the oxide semiconductor. Impurities such as argon, nitrogen, carbon, phosphorus, or boron are added to the region of the insulating film which overlaps with the source region and the drain region of the oxide semiconductor, thereby generating a defect. Hydrogen in the oxide semiconductor is attracted to the defect in the insulating film. The defect in the insulating film is stabilized by the presence of hydrogen.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: October 14, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masashi Tsubuku, Yusuke Nonaka, Noritaka Ishihara, Masashi Oota, Hideyuki Kishida
  • Patent number: 8859437
    Abstract: Disclosed herein is an aqueous alkaline etching solution comprising water and an alkaline material being selected from the group consisting of ammonium hydroxide, ammonium phosphate, ammonium carbonate, quaternary ammonium hydroxide, quaternary ammonium phosphate, quaternary ammonium carbonate, an alkali metal hydroxide, an alkaline earth metal hydroxide, or a combination comprising at least one of the foregoing alkaline materials; the aqueous alkaline solution being operative to etch aluminum oxide at a rate greater than or equal to about 2:1 over a rate at which it etches a metal oxide semiconductor to be protected; wherein the aqueous etching solution has a pH of 8 to 13.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: October 14, 2014
    Assignee: The Penn State Research Foundation
    Inventors: Yuanyuan Li, Kaige Sun, Thomas N. Jackson
  • Patent number: 8859332
    Abstract: The present invention relates to a liquid phase process for producing indium oxide-containing layers, in which a coating composition preparable from a mixture comprising at least one indium oxide precursor and at least one solvent and/or dispersion medium, in the sequence of points a) to d), a) is applied to a substrate, and b) the composition applied to the substrate is irradiated with electromagnetic radiation, c) optionally dried and d) converted thermally into an indium oxide-containing layer, where the indium oxide precursor is an indium halogen alkoxide of the generic formula InX(OR)2 where R is an alkyl radical and/or alkoxyalkyl radical and X is F, Cl, Br or I and the irradiation is carried out with electromagnetic radiation having significant fractions of radiation in the range of 170-210 nm and of 250-258 nm, to the indium oxide-containing layers producible with the process, and the use thereof.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: October 14, 2014
    Assignee: Evonik Degussa GmbH
    Inventors: Juergen Steiger, Duy Vu Pham, Heiko Thiem, Alexey Merkulov, Arne Hoppe
  • Patent number: 8859329
    Abstract: Some embodiments include memory cells having programmable material between a pair of electrodes. The programmable material includes a material selected from the group consisting of a metal silicate with a ratio of metal to silicon within a range of from about 2 to about 6, and metal aluminate with a ratio of metal to aluminum within a range of from about 2 to about 6. Some embodiments include methods of forming memory cells. First electrode material is formed. Programmable material is formed over the first electrode material, with the programmable material including metal silicate and/or metal aluminate. Second electrode material is formed over the programmable material, and then an anneal is conducted at a temperature within a range of from about 300° C. to about 500° C. for a time of from about 1 minute to about 1 hour.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: October 14, 2014
    Assignee: Micron Technology, Inc.
    Inventors: D. V. Nirmal Ramaswamy, Murali Balakrishnan, Alessandro Torsi, Noel Rocklein
  • Patent number: 8859328
    Abstract: A nonvolatile memory element is disclosed comprising a first electrode, a near-stoichiometric metal oxide memory layer having bistable resistance, and a second electrode in contact with the near-stoichiometric metal oxide memory layer. At least one electrode is a resistive electrode comprising a sub-stoichiometric transition metal nitride or oxynitride, and has a resistivity between 0.1 and 10 ?cm. The resistive electrode provides the functionality of an embedded current-limiting resistor and also serves as a source and sink of oxygen vacancies for setting and resetting the resistance state of the metal oxide layer. Novel fabrication methods for the second electrode are also disclosed.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: October 14, 2014
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Hieu Pham, Vidyut Gopal, Imran Hashim, Tim Minvielle, Dipankar Pramanik, Yun Wang, Takeshi Yamaguchi, Hong Sheng Yang
  • Patent number: 8859330
    Abstract: A semiconductor device including an oxide semiconductor, which has stable electric characteristics and high reliability, is provided. In a method for manufacturing a transistor including an oxide semiconductor film, an implantation step where rare gas ions are implanted to the oxide semiconductor film is performed, and the oxide semiconductor film to which rare gas ions are implanted is subjected to a heating step under reduced pressure, in a nitrogen atmosphere, or in a rare gas atmosphere, whereby hydrogen or water contained in the oxide semiconductor film to which rare gas ions are implanted is released; thus, the oxide semiconductor film is highly purified.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: October 14, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Shinji Ohno, Yuichi Sato
  • Publication number: 20140299873
    Abstract: To provide a metal oxide film including a single-crystal region. An oxide semiconductor film including indium and zinc is formed by a sputtering method by using a c-axis-aligned polycrystalline sputtering target at a substrate temperature of 200° C. or higher and 500° C. or lower. In this case, the oxide semiconductor film is formed over a c-axis-aligned zinc oxide film with a thickness of 0.1 nm or more and 5 nm or less. Consequently, it is possible to form an island-shaped single crystal with an average thickness of 0.5 ?m or less, preferably 5 nm or more and 0.1 ?m or less and an area of 5 ?m2 or more, preferably 1000 ?m2 or more. The oxide semiconductor film is a thin film extremely close to a single crystal which includes such an island-shaped single crystal at 80% or more, preferably 95% or more in the film.
    Type: Application
    Filed: March 31, 2014
    Publication date: October 9, 2014
    Inventor: Shunpei YAMAZAKI
  • Publication number: 20140299877
    Abstract: A coating liquid for forming a metal oxide thin film includes: an inorganic indium compound; an inorganic calcium compound or an inorganic strontium compound, or both thereof; and an organic solvent.
    Type: Application
    Filed: November 28, 2012
    Publication date: October 9, 2014
    Applicant: RICOH COMPANY, LTD.
    Inventors: Yuki Nakamura, Naoyuki Ueda, Yukiko Abe, Yuji SONE, Shinji Matsumoto, Mikiko Takada, Ryoichi Saotome
  • Publication number: 20140302639
    Abstract: To reduce adverse effects on actual operation and to reduce adverse effects of noise. A structure including an electrode, a wiring electrically connected to the electrode, an oxide semiconductor layer overlapping with the electrode in a plane view, an insulating layer provided between the electrode and the oxide semiconductor layer in a cross-sectional view, and a functional circuit to which a signal is inputted from the electrode through the wiring and in which operation is controlled in accordance with the signal inputted. A capacitor is formed using an oxide semiconductor layer, an insulating layer, and a wiring or an electrode.
    Type: Application
    Filed: June 23, 2014
    Publication date: October 9, 2014
    Inventors: Hideki UOCHI, Daisuke KAWAE
  • Publication number: 20140302638
    Abstract: A semiconductor device having favorable electric characteristics and a manufacturing method thereof are provided. A transistor includes an oxide semiconductor layer formed over an insulating layer, a source electrode layer and a drain electrode layer which overlap with part of the oxide semiconductor layer, a gate insulating layer in contact with part of the oxide semiconductor layer, and a gate electrode layer over the gate insulating layer. In the transistor, a buffer layer having n-type conductivity is formed between the source electrode layer and the oxide semiconductor layer and between the drain electrode layer and the oxide semiconductor layer. Thus, parasitic resistance is reduced, resulting in improvement of on-state characteristics of the transistor.
    Type: Application
    Filed: June 19, 2014
    Publication date: October 9, 2014
    Inventor: Shunpei YAMAZAKI
  • Patent number: 8852996
    Abstract: Provided are carbon doped resistive switching layers, resistive random access memory (ReRAM) cells including these layers, as well as methods of forming thereof. Carbon doping of metal containing materials creates defects in these materials that allow forming and breaking conductive paths as evidenced by resistive switching. Relative to many conventional dopants, carbon has a lower diffusivity in many suitable base materials. As such, these carbon doped materials exhibit structural stability and consistent resistive switching over many operating cycles. Resistive switching layers may include as much as 30 atomic percent of carbon, making the dopant control relatively simple and flexible. Furthermore, carbon doping has acceptor characteristics resulting in a high resistivity and low switching currents, which are very desirable for ReRAM applications. Carbon doped metal containing layer may be formed from metalorganic precursors at temperatures below saturation ranges of atomic layer deposition.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: October 7, 2014
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Yun Wang, Tony P. Chiang, Tim Minvielle, Takeshi Yamaguchi
  • Patent number: 8852997
    Abstract: A method for purifying an n-type ZnO and/or ZnMgO substrate to reduce or eliminate the residual extrinsic impurities including introducing a reactive species having strong chemical affinity for at least one of the residual extrinsic impurities, and/or being capable of creating crystalline defects, is introduced in at least one region of the substrate, the reactive species being P, and whereby at least one getter region capable of trapping the said residual extrinsic impurities and/or in which the residual extrinsic impurities are trapped is created in the substrate; then annealing the substrate to cause diffusion of the residual extrinsic impurities towards the getter region and/or to outside the getter region. A method for preparing a p-doped ZnO and/or ZnMgO substrate comprising purifying an n-type ZnO and/or ZnMgO substrate using the above purification method in which one or more reactive species are used not limited to phosphorus alone.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: October 7, 2014
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventors: Isabelle Bisotto, Guy Feuillet
  • Patent number: 8853691
    Abstract: A transistor and a manufacturing method thereof are provided. The transistor includes a first gate, a second gate disposed on one side of the first gate, a first semiconductor layer, a second semiconductor layer, an oxide layer, a first insulation layer, a second insulation layer, a source, and a drain. The first semiconductor layer is disposed between the first and second gates; the second semiconductor layer is disposed between the first semiconductor layer and the second gate. The oxide layer is disposed between the first semiconductor layer and the second semiconductor layer. The first insulation layer is disposed between the first gate and the first semiconductor layer; the second insulation layer is disposed between the second gate and the second semiconductor layer. The source and the drain are disposed between the first insulation layer and the second insulation layer and respectively disposed on opposite sides of the oxide layer.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: October 7, 2014
    Assignee: E Ink Holdings Inc.
    Inventors: Chih-Hsiang Yang, Ted-Hong Shinn, Wei-Tsung Chen, Hsing-Yi Wu
  • Patent number: 8853660
    Abstract: Semiconductor devices include lower interconnections, upper interconnections crossing over the lower interconnections, selection components disposed at crossing points of the lower interconnections and the upper interconnections, respectively, and memory components disposed between the selection components and the upper interconnections. Each of the selection components may include a semiconductor pattern having a first sidewall and a second sidewall. The first sidewall of the semiconductor pattern may have a first upper width and a first lower width that is greater than the first upper width. The second sidewall of the semiconductor pattern may have a second upper width and a second lower width that is substantially equal to the second upper width.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: October 7, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: JaeJong Han, Sungun Kwon, Jinhye Bae, Kongsoo Lee, Seong Hoon Jeong, Yoongoo Kang, Ho-Kyun An
  • Patent number: 8853686
    Abstract: A flat panel display device with an oxide thin film transistor and a fabricating method thereof are disclosed. The fabricating method of the flat panel display device includes: preparing a substrate defined into a pixel region and a pad contact region; forming a gate electrode and a link line; forming a pixel electrode within the pixel region; forming an oxide layer on the substrate provided with the pixel electrode; forming a passivation layer on the substrate and performing a formation process of contact holes to expose the link line; and forming a second transparent conductive material film on the substrate.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: October 7, 2014
    Assignee: LG Display Co., Ltd.
    Inventors: Ji Eun Chae, Jung Eun Ahn, Tae Keun Lee
  • Patent number: 8853854
    Abstract: A semiconductor package may include a package substrate, a first semiconductor chip and a second semiconductor chip. The first semiconductor chip may be arranged on the package substrate. The first semiconductor chip may have a plug electrically connected to the package substrate and at least one insulating hole arranged around the plug. The second semiconductor chip may be arranged on the first semiconductor chip. The second semiconductor chip may be electrically connected to the plug. Thus, the insulating hole and the insulating member may ensure an electrical isolation between the plug and the first semiconductor chip, and between the plugs.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: October 7, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jong-Joo Lee
  • Patent number: 8853713
    Abstract: Resistive memory having confined filament formation is described herein. One or more method embodiments include forming an opening in a stack having a silicon material and an oxide material on the silicon material, and forming an oxide material in the opening adjacent the silicon material, wherein the oxide material formed in the opening confines filament formation in the resistive memory cell to an area enclosed by the oxide material formed in the opening.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: October 7, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Eugene P. Marsh, Jun Liu
  • Patent number: 8853046
    Abstract: A single TiON film is used to form a ReRAM device by varying the oxygen and nitrogen content throughout the device to form the electrodes and switching layer. A ReRAM device that can be formed in a single deposition chamber is also disclosed. The ReRAM device can be formed by forming a first titanium nitride layer, forming a titanium oxynitride-titanium oxide-titanium oxynitride layer, and then forming a second titanium nitride.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: October 7, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Nan Lu, Chien-Lan Hsueh
  • Publication number: 20140295617
    Abstract: A highly reliable semiconductor device which includes a transistor including an oxide semiconductor is provided. In the semiconductor device including a bottom-gate transistor including an oxide semiconductor layer, a stacked layer of an insulating layer and an aluminum film is provided in contact with the oxide semiconductor layer. Oxygen doping treatment is performed in such a manner that oxygen is introduced to the insulating layer and the aluminum film from a position above the aluminum film, whereby a region containing oxygen in excess of the stoichiometric composition is formed in the insulating layer, and the aluminum film is oxidized to form an aluminum oxide film.
    Type: Application
    Filed: June 17, 2014
    Publication date: October 2, 2014
    Inventor: Shunpei YAMAZAKI
  • Publication number: 20140295616
    Abstract: To provide a miniaturized transistor having favorable electric characteristics. An oxide semiconductor layer is formed to cover a source electrode layer and a drain electrode layer, and then regions of the oxide semiconductor layer which overlap with the source electrode layer and the drain electrode layer are removed by polishing. Precise processing can be performed accurately because an etching step using a resist mask is not performed in the step of removing the regions of the oxide semiconductor layer overlapping with the source electrode layer and the drain electrode layer. Further, a sidewall layer having conductivity is provided on a side surface of a gate electrode layer in a channel length direction; thus, the sidewall layer having conductivity overlaps with the source electrode layer or the drain electrode layer with a gate insulating layer provided therebetween, and a transistor substantially including an Lov region is provided.
    Type: Application
    Filed: June 12, 2014
    Publication date: October 2, 2014
    Inventor: Shunpei YAMAZAKI
  • Publication number: 20140291674
    Abstract: A substrate having an insulating surface is prepared; a stacked film including a first oxide semiconductor layer and a second oxide semiconductor layer is formed over the substrate; a mask layer is formed over part of the stacked film and then dry etching treatment is performed, so that the stacked film is removed, with a region provided with the mask layer remaining, and a reaction product is formed on a side surface of the remaining stacked film; the reaction product is removed by wet etching treatment after removal of the mask layer; a source electrode and a drain electrode are formed over the stacked film; and a third oxide semiconductor layer, a gate insulating film, and a gate electrode are stacked and formed in this order over the stacked film, and the source electrode and the drain electrode.
    Type: Application
    Filed: March 27, 2014
    Publication date: October 2, 2014
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Motomu KURATA, Shinya SASAGAWA, Taiga MURAOKA, Hiroaki HONDA, Takashi HAMADA
  • Publication number: 20140291671
    Abstract: A first source electrode is formed in contact with a semiconductor layer; a first drain electrode is formed in contact with the semiconductor layer; a second source electrode which extends beyond an end portion of the first source electrode to be in contact with the semiconductor layer is formed; a second drain electrode which extends beyond an end portion of the first drain electrode to be in contact with the semiconductor layer is formed; a first sidewall is formed in contact with a side surface of the second source electrode and the semiconductor layer; a second sidewall is formed in contact with a side surface of the second drain electrode and the semiconductor layer; and a gate electrode is formed to overlap the first sidewall, the second sidewall, and the semiconductor layer with a gate insulating layer provided therebetween.
    Type: Application
    Filed: March 20, 2014
    Publication date: October 2, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei YAMAZAKI, Daisuke MATSUBAYASHI
  • Publication number: 20140291673
    Abstract: A highly reliable semiconductor device with stable electrical characteristics and a method for manufacturing the semiconductor device are provided. A separation layer is formed between a source electrode and a drain electrode. The separation layer is formed using a material having a high insulating property. The separation layer between the source electrode and the drain electrode can reduce a difference in level of each of the source electrode and the drain electrode, which can improve coverage with a layer formed over the source electrode and the drain electrode. The separation layer between the source electrode and the drain electrode can prevent an unintended electrical short circuit of the source electrode and the drain electrode. The separation layer can be formed by introducing oxygen to a conductive layer.
    Type: Application
    Filed: March 24, 2014
    Publication date: October 2, 2014
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Shunpei Yamazaki
  • Publication number: 20140291676
    Abstract: A semiconductor device includes a substrate having an insulating surface; a light-transmitting first electrode provided over the substrate; a light-transmitting second electrode provided over the substrate; a light-transmitting semiconductor layer provided so as to be electrically connected to the first electrode and the second electrode; a first wiring electrically connected to the first electrode; an insulating layer provided so as to cover at least the semiconductor layer; a light-transmitting third electrode provided over the insulating layer in a region overlapping with the semiconductor layer; and a second wiring electrically connected to the third electrode.
    Type: Application
    Filed: June 18, 2014
    Publication date: October 2, 2014
    Inventor: Hajime KIMURA
  • Publication number: 20140291672
    Abstract: The stability of steps of processing a wiring formed using copper or the like is increased. The concentration of impurities in a semiconductor film is reduced. Electrical characteristics of a semiconductor device are improved. A semiconductor device includes a semiconductor film, a pair of first protective films in contact with the semiconductor film, a pair of conductive films containing copper or the like in contact with the pair of first protective films, a pair of second protective films in contact with the pair of conductive films on the side opposite the pair of first protective films, a gate insulating film in contact with the semiconductor film, and a gate electrode overlapping with the semiconductor film with the gate insulating film therebetween. In a cross section, side surfaces of the pair of second protective films are located on the outer side of side surfaces of the pair of conductive films.
    Type: Application
    Filed: March 20, 2014
    Publication date: October 2, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei YAMAZAKI, Masami JINTYOU, Yasutaka NAKAZAWA, Yukinori SHIMA
  • Publication number: 20140291635
    Abstract: A thin-film transistor, a method for manufacturing the same and a display device including the same are provided. The thin-film transistor may include a substrate, and an active layer formed on the substrate. The active layer may be made from an oxide semiconductor. A gate electrode may be formed above the active layer or below the active layer. A conductive layer may come in contact with the active layer, may be overlapped with at least a part of the gate electrode, and may be insulated from the gate electrode. A source electrode and a drain electrode may be electrically connected to the active layer. The conductive layer can reduce a channel length of the thin-film transistor and increase a capacitance between the source electrode and the gate electrode or between the drain electrode and the gate electrode.
    Type: Application
    Filed: December 3, 2013
    Publication date: October 2, 2014
    Applicant: LG Display Co., Ltd.
    Inventor: HyungNyuck CHO
  • Publication number: 20140291669
    Abstract: A thin-film transistor includes a substrate, a first gate electrode formed on the substrate, a first active layer that is formed on the substrate and includes a first oxide semiconductor layer and a first barrier layer, a second active layer that is formed on the first active layer and includes a second oxide semiconductor layer and an intermediate barrier layer, a gate insulating layer that is formed on the second active layer, a second gate electrode that is formed on the gate insulating layer and is electrically connected to the first gate electrode, an interlayer insulating film formed on the second gate electrode, the first active layer and the second active layer, and a source electrode and a drain electrode electrically connected to the first active layer and the second active layer.
    Type: Application
    Filed: March 19, 2014
    Publication date: October 2, 2014
    Applicant: LG Display Co., Ltd.
    Inventors: KwangHwan Ji, DaeHwan Kim, JunHyeon Bae
  • Publication number: 20140291665
    Abstract: A thin film transistor array panel includes: a gate electrode disposed on a substrate, an insulating layer disposed on the gate electrode, an oxide semiconductor disposed on the gate insulating layer, source electrode overlapping a portion of the oxide semiconductor, a drain electrode overlapping another portion of the oxide semiconductor; and a buffer layer disposed between the oxide semiconductor and the source electrode and between the oxide semiconductor and the drain electrode. The buffer layer comprises tin as a doping material. A weight percent of the doping material is greater than approximately 0% and less than or equal to approximately 20%.
    Type: Application
    Filed: February 13, 2014
    Publication date: October 2, 2014
    Applicant: Samsung Display Co., Ltd.
    Inventors: Gun Hee KIM, Jin Hyun PARK, Kyoung Won LEE, Byung Du AHN, Jee-Hun LIM, Jun Hyung LIM
  • Patent number: 8846537
    Abstract: A mold having an open interior volume is used to define patterns. The mold has a ceiling, floor and sidewalls that define the interior volume and inhibit deposition. One end of the mold is open and an opposite end has a sidewall that acts as a seed sidewall. A first material is deposited on the seed sidewall. A second material is deposited on the deposited first material. The deposition of the first and second materials is alternated, thereby forming alternating rows of the first and second materials in the interior volume. The mold and seed layer are subsequently selectively removed. In addition, one of the first or second materials is selectively removed, thereby forming a pattern including free-standing rows of the remaining material. The free-standing rows can be utilized as structures in a final product, e.g., an integrated circuit, or can be used as hard mask structures to pattern an underlying substrate. The mold and rows of material can be formed on multiple levels.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: September 30, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Gurtej S. Sandhu
  • Patent number: 8847187
    Abstract: Embodiments of the invention include a nonvolatile memory device that contains nonvolatile resistive random access memory device with improved device performance and lifetime. In some embodiments, nonvolatile resistive random access memory device includes a diode, a metal silicon nitride embedded resistor, and a resistive switching layer disposed between a first electrode layer and a second electrode layer. In some embodiments, the method of forming a resistive random access memory device includes forming a diode, forming a metal silicon nitride embedded resistor, forming a first electrode layer, forming a second electrode layer, and forming a resistive switching layer disposed between the first electrode layer and the second electrode layer.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: September 30, 2014
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Mihir Tendulkar, David Chi
  • Patent number: 8846443
    Abstract: Embodiments of the invention generally relate to nonvolatile memory devices and methods for manufacturing such memory devices. The methods for forming improved memory devices, such as a ReRAM cells, provide optimized, atomic layer deposition (ALD) processes for forming a metal oxide film stack which contains at least one hard metal oxide film (e.g., metal is completely oxidized or substantially oxidized) and at least one soft metal oxide film (e.g., metal is less oxidized than hard metal oxide). The soft metal oxide film is less electrically resistive than the hard metal oxide film since the soft metal oxide film is less oxidized or more metallic than the hard metal oxide film. In one example, the hard metal oxide film is formed by an ALD process utilizing ozone as the oxidizing agent while the soft metal oxide film is formed by another ALD process utilizing water vapor as the oxidizing agent.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: September 30, 2014
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Zhendong Hong, Hieu Pham, Randall Higuchi, Vidyut Gopal, Imran Hashim, Tim Minvielle, Takeshi Yamaguchi
  • Patent number: 8847189
    Abstract: A memory storage device including: a lower electrode formed to be separated for each of memory cells; a memory storage layer formed on the lower electrode and capable of recording information according to a change in resistance; and an upper electrode formed on the memory storage layer, wherein the memory storage device includes a first layer formed of metal or metal silicide and a second layer formed on the first layer and formed of a metal nitride, the lower electrode is formed by lamination of the first layer and the second layer and formed such that only the first layer is in contact with a lower layer and only the second layer is in contact with the memory storage layer, which is an upper layer, the memory storage layer is formed in common to plural memory cells, and the upper electrode is formed in common to the plural memory cells.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: September 30, 2014
    Assignee: Sony Corporation
    Inventor: Wataru Ootsuka
  • Publication number: 20140287552
    Abstract: A stable and minute processing method of a thin film is provided. Further, a miniaturized semiconductor device is provided. A method for processing a thin film includes the following steps: forming a film to be processed over a formation surface; forming an organic coating film over the film to be processed; forming a resist film over the organic coating film; exposing the resist film to light_or_an electron beam; removing part of the resist film by development to expose part of the organic coating film; depositing an organic material layer on the top surface and a side surface of the resist film by plasma treatment; etching part of the organic coating film using the resist film and the organic material layer as masks to expose part of the film to be processed; and etching part of the film to be processed using the resist film and the organic material layer as masks.
    Type: Application
    Filed: March 19, 2014
    Publication date: September 25, 2014
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Taiga Muraoka, Motomu Kurata, Shinya Sasagawa, Katsuaki Tochibayashi
  • Publication number: 20140284597
    Abstract: To improve crystallinity of an oxide semiconductor. To provide a crystalline oxide semiconductor film in which a crystallized region extends to the interface with a base or the vicinity of the interface, and to provide a method for forming the oxide semiconductor film. An oxide semiconductor film containing indium, gallium, and zinc is formed, and the oxide semiconductor film is irradiated with an energy beam, thereby being heated. Note that the oxide semiconductor film includes a c-axis aligned crystal region or microcrystal.
    Type: Application
    Filed: March 13, 2014
    Publication date: September 25, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihisa SHIMOMURA, Takahisa ISHIYAMA, Masaki KOYAMA, Erumu KIKUCHI, Takuya HIROHASHI, Masashi OOTA
  • Publication number: 20140284595
    Abstract: A semiconductor device for miniaturization is provided. The semiconductor device includes a semiconductor layer; a first electrode and a second electrode that are on the semiconductor layer and apart from each other over the semiconductor layer; a gate electrode over the semiconductor layer; and a gate insulating layer between the semiconductor layer and the gate electrode. The first and second electrodes comprise first conductive layers and second conductive layers. In a region overlapping with the semiconductor layer, the second conductive layers are positioned between the first conductive layers, and side surfaces of the second conductive layers are in contact with side surfaces of the first conductive layers. The second conductive layers have smaller thicknesses than those of the first conductive layers, and the top surface levels of the second conductive layers are lower than those of the first conductive layers.
    Type: Application
    Filed: March 11, 2014
    Publication date: September 25, 2014
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shinya SASAGAWA, Motomu KURATA, Taiga MURAOKA
  • Publication number: 20140284594
    Abstract: According to one embodiment, a display device includes a substrate unit, a thin film transistor, a pixel electrode and a display layer. The substrate unit includes a substrate, a first insulating layer provided on the substrate, and a second insulating layer provided on the first insulating layer. The thin film transistor is provided on the substrate unit and includes a gate electrode provided on the second insulating layer, a semiconductor layer of an oxide separated from the gate electrode, a gate insulation layer provided between the gate electrode and the semiconductor layer, a first conductive portion, a second conductive portion, and a third insulating layer. The pixel electrode is connected to one selected from the first and second conductive portions. The display layer is configured to have a light emission or a change of optical characteristic occurring according to a charge supplied to the pixel electrode.
    Type: Application
    Filed: February 7, 2014
    Publication date: September 25, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shintaro NAKANO, Tomomasa Ueda, Kentaro Miura, Nobuyoshi Saito, Tatsunori Sakano, Yuya Maeda, Hajime Yamaguchi
  • Publication number: 20140284593
    Abstract: According to one embodiment, a semiconductor device includes a substrate having an upper surface, a foundation insulating layer provided on the upper surface, and a thin film transistor. The thin film transistor includes a first gate electrode, first, second and third insulating layers, a semiconductor layer, and first and second conductive layers. The first gate electrode is provided on a portion of the foundation insulating layer. The first insulating layer covers the first gate electrode and the foundation insulating layer. The second insulating layer is provided on the first insulating layer, and has first, second and third portions. The semiconductor layer contacts the second insulating layer on the third portion, and has fourth, fifth portions and sixth portions. The first conductive layer contacts the fourth portion. The second conductive layer contacts the fifth portion. The third insulating layer covers a portion of the semiconductor layer.
    Type: Application
    Filed: February 5, 2014
    Publication date: September 25, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shintaro Nakano, Tomomasa Ueda, Ikuo Fujiwara, Hajime Yamaguchi
  • Patent number: 8841182
    Abstract: Methods of treating metal-containing thin films, such as films comprising titanium carbide, with a silane/borane agent are provided. In some embodiments a film including titanium carbide is deposited on a substrate by an atomic layer deposition (ALD) process. The process may include a plurality of deposition cycles involving alternating and sequential pulses of a first source chemical that includes titanium and at least one halide ligand, a second source chemical that includes metal and carbon, where the metal and the carbon from the second source chemical are incorporated into the thin film, and a third source chemical, where the third source chemical is a silane or borane that at least partially reduces oxidized portions of the titanium carbide layer formed by the first and second source chemicals. The treatment can form a capping layer on the metal carbide film.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 23, 2014
    Assignee: ASM IP Holding B.V.
    Inventors: Jerry Chen, Vladimir Machkaoutsan, Brennan Milligan, Jan Willem Maes, Suvi Haukka, Eric Shero, Tom E. Blomberg, Dong Li
  • Patent number: 8841165
    Abstract: A semiconductor device includes an oxide semiconductor film including a pair of first regions, a pair of second regions, and a third region; a pair of electrodes in contact with the oxide semiconductor film; a gate insulating film over the oxide semiconductor film; and a gate electrode provided between the pair of electrodes with the gate insulating film interposed therebetween. The pair of first regions overlap with the pair of electrodes, the third region overlaps with the gate electrode, and the pair of second regions are formed between the pair of first regions and the third region. The pair of second regions and the third region each contain nitrogen, phosphorus, or arsenic. The pair of second regions have a higher element concentration than the third region.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: September 23, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kosei Noda
  • Patent number: 8841664
    Abstract: Provided is a highly reliable semiconductor device by giving stable electric characteristics to a transistor in which a semiconductor film whose threshold voltage is difficult to control is used as an active layer. By using a silicon oxide film having a negative fixed charge as a film in contact with the active layer of the transistor or a film in the vicinity of the active layer, a negative electric field is always applied to the active layer due to the negative fixed charge and the threshold voltage of the transistor can be shifted in the positive direction. Thus, the highly reliable semiconductor device can be manufactured by giving stable electric characteristics to the transistor.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: September 23, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hitomi Sato, Takayuki Saito, Kosei Noda, Toru Takayama
  • Patent number: 8841164
    Abstract: The present invention relates to a liquid phase process for producing indium oxide-containing layers from nonaqueous solution, in which an anhydrous composition containing at least one indium halogen alkoxide of the generic formula InX(OR)2 where R=alkyl radical and/or alkoxyalkyl radical and X=F, Cl, Br or I and at least one solvent or dispersion medium is, in the sequence of points a) to d), in anhydrous atmosphere, a) applied to the substrate, b) the composition applied to the substrate is irradiated with electromagnetic radiation of wavelength ?360 nm and c) optionally dried, and then d) converted thermally to an indium oxide-containing layer, to the layers producible by the process and to the use thereof.
    Type: Grant
    Filed: November 25, 2010
    Date of Patent: September 23, 2014
    Assignee: Evonik Degussa GmbH
    Inventors: Jürgen Steiger, Duy Vu Pham, Heiko Thiem, Alexey Merkulov, Arne Hoppe
  • Patent number: 8841665
    Abstract: Disclosed is a method for manufacturing an oxide thin film transistor, including: forming a gate electrode on a substrate on which a buffer layer is formed; forming a gate insulation layer on an entire surface of the substrate on which the gate electrode is formed; forming an oxide semiconductor layer on the gate insulation layer; forming a first etch stop layer on the oxide semiconductor layer; forming a second etch stop layer on the first etch stop layer by an atomic layer deposition method; patterning the first etch stop layer and the second etch stop layer, or forming a contact hole, through which a part of the oxide semiconductor layer is exposed, in the first etch stop layer and the second etch stop layer; forming a source electrode and a drain electrode on the first etch stop layer and the second etch stop layer; and forming a passivation layer on the entire surface of the substrate on which the source electrode and the drain electrode are formed.
    Type: Grant
    Filed: March 22, 2013
    Date of Patent: September 23, 2014
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sang Hee Park, Min Ki Ryu, Him Chan Oh, Chi Sun Hwang
  • Patent number: 8841163
    Abstract: A semiconductor device for high power application in which a novel semiconductor material having high mass productivity is provided. An oxide semiconductor film is formed, and then, first heat treatment is performed on the exposed oxide semiconductor film in order to reduce impurities such as moisture or hydrogen in the oxide semiconductor film. Next, in order to further reduce impurities such as moisture or hydrogen in the oxide semiconductor film, oxygen is added to the oxide semiconductor film by an ion implantation method, an ion doping method, or the like, and after that, second heat treatment is performed on the exposed oxide semiconductor film.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: September 23, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichiro Sakata, Hiroki Ohara
  • Publication number: 20140264329
    Abstract: A protective circuit includes a non-linear element, which includes a gate electrode, a gate insulating layer covering the gate electrode, a pair of first and second wiring layers whose end portions overlap with the gate electrode over the gate insulating layer and in which a second oxide semiconductor layer and a conductive layer are stacked, and a first oxide semiconductor layer which overlaps with at least the gate electrode and which is in contact with the gate insulating layer, side face portions and part of top face portions of the conductive layer and side face portions of the second oxide semiconductor layer in the first wiring layer and the second wiring layer. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be decreased and the characteristics of the non-linear element can be improved.
    Type: Application
    Filed: May 29, 2014
    Publication date: September 18, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei YAMAZAKI, Kengo AKIMOTO, Shigeki KOMORI, Hideki UOCHI, Tomoya FUTAMURA, Takahiro KASAHARA