Having Metal Oxide Or Copper Sulfide Compound Semiconductor Component Patents (Class 438/104)
  • Publication number: 20140264319
    Abstract: An organic material with a porous interpenetrating network and an amount of inorganic material at least partially distributed within the porosity of the organic material is disclosed. A method of producing the organic-inorganic thin films and devices therefrom comprises seeding with nanoparticles and depositing an amorphous material on the nanoparticles.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: THE BOEING COMPANY
    Inventor: The Boeing Company
  • Publication number: 20140273340
    Abstract: Methods for HPC techniques are applied to the processing of site-isolated regions (SIR) on a substrate to form at least a portion of a TFT device used in display applications. The processing may be applied to at least one of gate electrode deposition, gate electrode patterning, gate dielectric deposition, gate dielectric patterning, metal-based semiconductor material (e.g. IGZO) deposition, metal-based semiconductor material (e.g. IGZO) patterning, etch stop deposition, etch stop patterning, source/drain deposition, source/drain patterning, passivation deposition, or passivation patterning. The SIRs may be defined during the deposition process with uniform deposition within each SIR or the SIRs may be defined subsequent to the deposition of layers wherein the layers are deposited with a gradient in one or more properties across the substrate.
    Type: Application
    Filed: December 2, 2013
    Publication date: September 18, 2014
    Applicant: Intermolecular, Inc.
    Inventors: Jeroen Van Duren, Sang Lee, Minh Huu Le, Sandeep Nijhawan, Teresa B. Sapirman
  • Publication number: 20140264323
    Abstract: When an oxide semiconductor film is microfabricated, with the use of a hard mask, unevenness of a side surface of the oxide semiconductor film can be suppressed. Specifically, a semiconductor device comprises an oxide semiconductor film over an insulating surface; a first hard mask and a second hard mask over the oxide semiconductor film; a source electrode over the oxide semiconductor film and the first hard mask; a drain electrode over the oxide semiconductor film and the second hard mask; a gate insulating film over the source electrode and the drain electrode; and a gate electrode overlapping with the gate insulating film and the oxide semiconductor film, and the first and second hard masks have conductivity.
    Type: Application
    Filed: March 5, 2014
    Publication date: September 18, 2014
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shinya Sasagawa, Motomu Kurata
  • Publication number: 20140273343
    Abstract: An object is to manufacture a semiconductor device including an oxide semiconductor at low cost with high productivity in such a manner that a photolithography process is simplified by reducing the number of light-exposure masks. In a method for manufacturing a semiconductor device including a channel-etched inverted-staggered thin film transistor, an oxide semiconductor film and a conductive film are etched using a mask layer formed with the use of a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. In etching steps, a first etching step is performed by dry etching in which an etching gas is used, and a second etching step is performed by wet etching in which an etchant is used.
    Type: Application
    Filed: May 27, 2014
    Publication date: September 18, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunichi ITO, Miyuki HOSOBA, Hideomi SUZAWA, Shinya SASAGAWA, Taiga MURAOKA
  • Publication number: 20140273342
    Abstract: The present invention generally relates to TFTs and methods for fabricating TFTs. When multiple layers are used for the semiconductor material in a TFT, a negative Vth shift may result. By exposing the semiconductor layer to an oxygen containing plasma and/or forming an etch stop layer thereover, the negative Vth shift may be negated.
    Type: Application
    Filed: March 7, 2014
    Publication date: September 18, 2014
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Dong-Kil YIM, Rodney Shunleong LIM, Evelyn SCHEER, Tae Kyung WON, Soo Young CHOI, Harvey YOU
  • Publication number: 20140264325
    Abstract: One aspect of the present invention is a double sided hybrid crystal structure including a trigonal Sapphire wafer containing a (0001) C-plane and having front and rear sides. The Sapphire wafer is substantially transparent to light in the visible and infrared spectra, and also provides insulation with respect to electromagnetic radio frequency noise. A layer of crystalline Si material having a cubic diamond structure aligned with the cubic <111> direction on the (0001) C-plane and strained as rhombohedron to thereby enable continuous integration of a selected (SiGe) device onto the rear side of the Sapphire wafer. The double sided hybrid crystal structure further includes an integrated III-Nitride crystalline layer on the front side of the Sapphire wafer that enables continuous integration of a selected III-Nitride device on the front side of the Sapphire wafer.
    Type: Application
    Filed: March 11, 2014
    Publication date: September 18, 2014
    Applicant: U.S.A. as represented by the Administrator of the National Aeronautics and Space Administration
    Inventors: Yeonjoon Park, Sang Hyouk Choi
  • Publication number: 20140273341
    Abstract: Embodiments described herein provide methods for forming indium-gallium-zinc oxide (IGZO) devices. A substrate is provided. An IGZO layer is formed above the substrate. A copper-containing layer is formed above the IGZO layer. A wet etch process is performed on the copper-containing layer to form a source region and a drain region above the IGZO layer. The performing of the wet etch process on the copper-containing layer includes exposing the copper-containing layer to an etching solution including a peroxide compound and one of citric acid, formic acid, malonic acid, lactic acid, etidronic acid, phosphonic acid, or a combination thereof.
    Type: Application
    Filed: December 18, 2013
    Publication date: September 18, 2014
    Applicant: Intermolecular, Inc.
    Inventors: Jeroen Van Duren, Sang Lee, Zhi-Wen Sun
  • Patent number: 8835215
    Abstract: A simple method is developed in the present invention for fabricating periodic ripple microstructures on the surface of an ITO film by using single-beam femtosecond laser pulses. The periodic ripple microstructures composed of self-organized nanodots can be directly fabricated through the irradiation of the femtosecond laser, without scanning. The ripple spacing of ˜800 nm, ˜400 nm and ˜200 nm observed in the periodic ripple microstructures can be attributed to the interference between the incident light and the scattering light of the femtosecond laser from the surface of the ITO film. In the present invention, the self-organized dots are formed by the constructive interference formed in the surface of the ITO film, where includes higher energy to break the In—O and Sn—O bonds and then form the In—In bonds. Therefore, the dots have higher surface current greater than other disconstructive regions of the ITO film.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: September 16, 2014
    Assignee: National Tsing Hua University
    Inventors: Jih-perng Leu, Chih-Wei Luo, Chih Wang, Jwo-Huei Jou
  • Patent number: 8835955
    Abstract: A silicon-on-insulator (SOI) substrate structure and method of fabrication including a single crystal silicon substrate, a layer of single crystal rare earth oxide formed on the substrate, a layer of engineered single crystal silicon formed on the layer of single crystal rare earth oxide, and a single crystal insulator layer of IIIOxNy formed on the engineered single crystal silicon layer. In some embodiments the III material in the insulator layer includes more than on III material. In a preferred embodiment the single crystal rare earth oxide includes Gd2O3 and the single crystal insulator layer of IIIOxNy includes one of AlOxNy and AlGaOxNy.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: September 16, 2014
    Assignee: Translucent, Inc.
    Inventors: Erdem Arkun, Rytis Dargis, Andrew Clark, Michael Lebby
  • Patent number: 8835236
    Abstract: A method for manufacturing an oxide semiconductor thin film transistor (TFT) is provided, which includes the steps below. A source electrode and a drain electrode are provided. A patterned insulating layer is formed to partially cover the source electrode and the drain electrode, and expose a portion of the source electrode and a portion of the drain electrode. An oxide semiconductor layer is formed to contact the portion of the source electrode and the portion of the drain electrode. A gate electrode is provided. A gate dielectric layer positioned between the oxide semiconductor layer and the gate electrode is provided. An oxide semiconductor TFT is also provided herein.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: September 16, 2014
    Assignee: Chunghwa Picture Tubes, Ltd.
    Inventor: Hsi-Ming Chang
  • Patent number: 8835890
    Abstract: Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. A ReRAM cell includes an embedded resistor and a resistive switching layer connected in series with this resistor. The resistor is configured to prevent over-programming of the cell by limiting electrical currents through the resistive switching layer. Unlike the resistive switching layer, which changes its resistance in order to store data, the embedded resistor maintains a substantially constant resistance during operation of the cell. The embedded resistor is formed from tantalum nitride and silicon nitride. The atomic ratio of tantalum and silicon may be specifically selected to yield resistors with desired densities and resistivities as well as ability to remain amorphous when subjected to various annealing conditions. The embedded resistor may also function as a diffusion barrier layer and prevent migration of components between one of the electrodes and the resistive switching layer.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: September 16, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Chien-Lan Hsueh, Randall J. Higuchi, Mihir Tendulkar
  • Patent number: 8835214
    Abstract: An object is to provide a deposition technique for depositing an oxide semiconductor film. Another object is to provide a method for manufacturing a highly reliable semiconductor element using the oxide semiconductor film. A novel sputtering target obtained by removing an alkali metal, an alkaline earth metal, and hydrogen that are impurities in a sputtering target used for deposition is used, whereby an oxide semiconductor film containing a small amount of those impurities can be deposited.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: September 16, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8835917
    Abstract: An object is to provide a semiconductor device having electrical characteristics such as high withstand voltage, low reverse saturation current, and high on-state current. In particular, an object is to provide a power diode and a rectifier which include non-linear elements. An embodiment of the present invention is a semiconductor device including a first electrode, a gate insulating layer covering the first electrode, an oxide semiconductor layer in contact with the gate insulating layer and overlapping with the first electrode, a pair of second electrodes covering end portions of the oxide semiconductor layer, an insulating layer covering the pair of second electrodes and the oxide semiconductor layer, and a third electrode in contact with the insulating layer and between the pair of second electrodes. The pair of second electrodes are in contact with end surfaces of the oxide semiconductor layer.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: September 16, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiromichi Godo, Satoshi Kobayashi
  • Patent number: 8835216
    Abstract: An oxide thin-film transistor (TFT) substrate that includes: a substrate, a gate line, a data line, an oxide TFT, and a pixel electrode. An oxide layer of the oxide TFT includes a first region that has semiconductor characteristics and a channel, and a second region that is conductive and surrounds the first region. A portion of the first region is electrically connected to the pixel electrode, and the second region is electrically connected to the data line.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: September 16, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Pil-Sang Yun, Young-Wook Lee, Woo-Geun Lee
  • Publication number: 20140252344
    Abstract: To provide an oxide composition, represented by: ZnO1-xSx+a (0<x?0.5, a>0), where part of O sites of ZnO is substituted with an S atom, and another S atom is provided to an interstitial site by doping, and wherein the oxide composition is p-type.
    Type: Application
    Filed: February 27, 2014
    Publication date: September 11, 2014
    Applicant: RICOH COMPANY, LTD.
    Inventors: Satomi Sabu, Kenkichiro Kobayashi
  • Publication number: 20140253183
    Abstract: A semi-metallic structure, comprising an LaAlO3—SrTiO3 heterostructure (19), said LaAlO3—SrTiO3 heterostructure comprising a two-dimensional hole gas (21) and a two-dimensional electron gas (23).
    Type: Application
    Filed: March 6, 2014
    Publication date: September 11, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Stuart N. HOLMES
  • Publication number: 20140252355
    Abstract: The semiconductor device (100A) according to the present invention has a thin film transistor (10A1) supported on a substrate; the thin film transistor (10A1) has an oxide semiconductor layer (5a1), a gate electrode (3a1), a source electrode (8a1), a drain electrode (9a1), and a metal oxide layer (6a, 7a) formed between the source electrode (8a1) and the oxide semiconductor layer (5a1) and/or between the drain electrode (9a1) and the oxide semiconductor layer (5a1); the metal oxide layer (6a, 7a) contains a metallic element included in the source electrode (8a1) and/or the drain electrode (9a1); and the thickness T1 of the oxide semiconductor layer, the thickness T2 of the metal oxide layer, and the distance D between the source electrode (8a1) and the drain electrode (9a1) satisfy the relationship D?1.56×(T2/T1)+0.75.
    Type: Application
    Filed: October 16, 2012
    Publication date: September 11, 2014
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Sumio Katoh, Makoto Nakazawa
  • Publication number: 20140252343
    Abstract: The present invention provides a thin-film transistor active device and a method for manufacturing the device. The thin-film transistor active device includes a substrate and a plurality of thin-film transistors formed on the substrate. Each of thin-film transistors includes a gate insulation layer and an oxide semiconductor active layer. The gate insulation layer is a silicon oxide layer having refractivity between 1.43-1.47. During the formation of the gate insulation layer, the flowrate ration between nitrous oxide and silicon tetrahydride in chemical vapor deposition is controlled to be greater than 30% so as to control the refractivity of the gate insulation layer so formed of silicon oxide to be between 1.43-1.47; meanwhile, the content of N—H bond in the gate insulation layer is reduced so as to effectively prevent the high interface trap density between the gate insulation layer and the oxide semiconductor layer caused by high content of N—H bond.
    Type: Application
    Filed: October 24, 2012
    Publication date: September 11, 2014
    Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventors: Chenglung Chiang, Polin Chen
  • Publication number: 20140256086
    Abstract: A transistor with superior electric characteristics is manufactured. An oxide insulating film is formed over a substrate, an oxide semiconductor film is formed over the oxide insulating film, heat treatment is then conducted at a temperature at which hydrogen contained in the oxide semiconductor film is desorbed and part of oxygen contained in the oxide insulating film is desorbed, then the heated oxide semiconductor film is etched into a predetermined shape to form an island-shaped oxide semiconductor film, a pair of electrodes is formed over the island-shaped oxide semiconductor film, a gate insulating film is formed over the pair of electrodes and the island-shaped oxide semiconductor film, and a gate electrode is formed over the gate insulating film.
    Type: Application
    Filed: May 22, 2014
    Publication date: September 11, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kosei NODA, Toshinari SASAKI
  • Patent number: 8829517
    Abstract: A TFT substrate (20a) includes: an insulating substrate (10a); a plurality of source terminals (15) located on the insulating substrate (10a); and a first terminal cover (24) covering part of each of the source terminals (15) and made of an oxide semiconductor. The first terminal cover (24) is removed in a region R between adjacent ones of the source terminals (15).
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: September 9, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshihito Hara, Yukinobu Nakata
  • Patent number: 8828794
    Abstract: In a manufacturing process of a transistor including an oxide semiconductor film, oxygen doping treatment is performed on the oxide semiconductor film, and then heat treatment is performed on the oxide semiconductor film and an aluminum oxide film provided over the oxide semiconductor film. Consequently, an oxide semiconductor film which includes a region containing more oxygen than a stoichiometric composition is formed. The transistor formed using the oxide semiconductor film can have high reliability because the amount of change in the threshold voltage of the transistor by a bias-temperature stress test (BT test) is reduced.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: September 9, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yuhei Sato, Keiji Sato, Tetsunori Maruyama, Junichi Koezuka
  • Patent number: 8829512
    Abstract: A miniaturized semiconductor device including a transistor in which a channel formation region is formed using an oxide semiconductor film and variation in electric characteristics due to a short-channel effect is suppressed is provided. In addition, a semiconductor device whose on-state current is improved is provided. A semiconductor device is provided with an oxide semiconductor film including a pair of second oxide semiconductor regions which are amorphous regions and a first oxide semiconductor region located between the pair of second oxide semiconductor regions, a gate insulating film, and a gate electrode provided over the first oxide semiconductor region with the gate insulating film interposed therebetween. Hydrogen or a rare gas is added to the second oxide semiconductor regions.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: September 9, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8829586
    Abstract: In a miniaturized transistor, a gate insulating layer is required to reduce its thickness; however, in the case where the gate insulating layer is a single layer of a silicon oxide film, a physical limit on thinning of the gate insulating layer might occur due to an increase in tunneling current, i.e. gate leakage current. With the use of a high-k film whose relative permittivity is higher than or equal to 10 is used for the gate insulating layer, gate leakage current of the miniaturized transistor is reduced. With the use of the high-k film as a first insulating layer whose relative permittivity is higher than that of a second insulating layer in contact with an oxide semiconductor layer, the thickness of the gate insulating layer can be thinner than a thickness of a gate insulating layer considered in terms of a silicon oxide film.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: September 9, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuta Endo, Takayuki Saito, Shunpei Yamazaki
  • Publication number: 20140246668
    Abstract: A miniaturized transistor having high electrical characteristics is provided with high yield. In a semiconductor device including the transistor, high performance, high reliability, and high productivity can be achieved. The semiconductor device includes a base insulating film, an oxide semiconductor film with a bottom surface and side surfaces in the base insulating film and a top surface exposed from the base insulating film, a source electrode and a drain electrode over the base insulating film and the oxide semiconductor film, a gate insulating film over the oxide semiconductor film, the source electrode, and the drain electrode, and a gate electrode over the gate insulating film and overlapping the oxide semiconductor film.
    Type: Application
    Filed: February 26, 2014
    Publication date: September 4, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihisa Shimomura, Tomoaki Moriwaka, Daigo Ito
  • Publication number: 20140246666
    Abstract: In general, according to one embodiment, a semiconductor device includes a first electrode, an oxide semiconductor film, an insulating film, a second electrode, a third electrode. The oxide semiconductor film is configured together with a first region, a second region, a third region, a fourth region, and a fifth region in one direction. The insulating film is provided between the first electrode and the oxide semiconductor film. The second electrode is provided on the second region and contacts the second region with an entire upper face of the second region as a contact face. The third electrode is provided on the fourth region and contacts the fourth region with an entire upper face of the fourth region as a contact face. The oxygen concentrations in the second region and in the fourth region are less than the oxygen concentration in the third region.
    Type: Application
    Filed: July 3, 2013
    Publication date: September 4, 2014
    Applicants: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tetsu MOROOKA, Tatsuya OHGURO, Hisayo MOMOSE, Kazuya FUKASE
  • Publication number: 20140248740
    Abstract: Memory devices and methods of forming include a mixed valent oxide located between a first electrode and a second electrode. Implantation of a metal below a surface of one of the electrodes allows formation of the mixed valent oxide with a direct interface to the electrode. An intermetallic oxide can be subsequently formed between the mixed valent oxide and the electrode by annealing the structure.
    Type: Application
    Filed: May 14, 2014
    Publication date: September 4, 2014
    Applicant: Micron Technology, Inc.
    Inventor: Gurtej S. Sandhu
  • Patent number: 8822263
    Abstract: It is provided a hetero epitaxial growth method, a hetero epitaxial crystal structure, a hetero epitaxial growth apparatus and a semiconductor device, the method includes forming a buffer layer formed with the orienting film of an oxide, or the orienting film of nitride on a heterogeneous substrate; and performing crystal growth of a zinc oxide based semiconductor layer on the buffer layer using a halogenated group II metal and an oxygen material. It is provided a homo epitaxial growth method, a homo epitaxial crystal structure, a homo epitaxial growth apparatus and a semiconductor device, the homo epitaxial growth method includes introducing reactant gas mixing zinc containing gas and oxygen containing gas on a zinc oxide substrate; and performing crystal growth of a zinc oxide based semiconductor layer on the zinc oxide substrate.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: September 2, 2014
    Assignees: National University Corporation Tokyo University of Agriculture and Technology, Rohm Co., Ltd., Tokyo Electron Limited
    Inventors: Akinori Koukitu, Yoshinao Kumagai, Tetsuo Fujii, Naoki Yoshii
  • Patent number: 8822265
    Abstract: Methods for producing RRAM resistive switching elements having reduced forming voltage include preventing formation of interfacial layers, and creating electronic defects in a dielectric film. Suppressing interfacial layers in an electrode reduces forming voltage. Electronic defects in a dielectric film foster formation of conductive pathways.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: September 2, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Prashant B Phatak, Ronald J. Kuse, Jinhong Tong
  • Patent number: 8822264
    Abstract: An object is to provide favorable interface characteristics of a thin film transistor including an oxide semiconductor layer without mixing of an impurity such as moisture. Another object is to provide a semiconductor device including a thin film transistor having excellent electric characteristics and high reliability, and a method by which a semiconductor device can be manufactured with high productivity. A main point is to perform oxygen radical treatment on a surface of a gate insulating layer. Accordingly, there is a peak of the oxygen concentration at an interface between the gate insulating layer and a semiconductor layer, and the oxygen concentration of the gate insulating layer has a concentration gradient. The oxygen concentration is increased toward the interface between the gate insulating layer and the semiconductor layer.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: September 2, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto
  • Patent number: 8822992
    Abstract: With a non-linear element (e.g., a diode) with small reverse saturation current, a power diode or rectifier is provided. A non-linear element includes a first electrode provided over a substrate, an oxide semiconductor film provided on and in contact with the first electrode and having a concentration of hydrogen of 5×1019 atoms/cm3 or less, a second electrode provided on and in contact with the oxide semiconductor film, a gate insulating film covering the first electrode, the oxide semiconductor film, and the second electrode, and third electrodes provided in contact with the gate insulating film and facing each other with the first electrode, the oxide semiconductor film, and the second electrode interposed therebetween or a third electrode provided in contact with the gate insulating film and surrounding the second electrode. The third electrodes are connected to the first electrode or the second electrode. With the non-linear element, a power diode or a rectifier is formed.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: September 2, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8822972
    Abstract: A non-volatile memory element including a first electrode; a second electrode; and a variable resistance layer. The variable resistance layer including, when a first metal is M and a second metal is N: a third metal oxide layer NOz; a second metal oxide layer NOy; and a first metal oxide layer MOx such that the third, second and first metal oxide layers are stacked in this order; wherein when an oxygen content atomic percentage of an oxide of the first metal M in a stoichiometric state is A, an oxygen content atomic percentage of an oxide of the second metal N in a stoichiometric state is B, an oxygen content atomic percentage of MOx is C, an oxygen content atomic percentage of NOy is D, and an oxygen content atomic percentage of NOz is E, (D/B)<(C/A), (E/B)<(C/A) and y<z are satisfied.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: September 2, 2014
    Assignee: Panasonic Corporation
    Inventors: Ryutaro Yasuhara, Takeki Ninomiya, Takeshi Takagi
  • Patent number: 8823082
    Abstract: The present invention is a semiconductor device including a first electrode over a substrate; a pair of oxide semiconductor films in contact with the first electrode; a second electrode in contact with the pair of oxide semiconductor films; a gate insulating film covering at least the first electrode and the pair of oxide semiconductor films; and a third electrode that is in contact with the gate insulating film and is formed at least between the pair of oxide semiconductor films. When the donor density of the oxide semiconductor films is 1.0×1013/cm3 or less, the thickness of the oxide semiconductor films is made larger than the in-plane length of each side of the oxide semiconductor films which is in contact with the first electrode.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: September 2, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Makoto Yanagisawa
  • Patent number: 8822989
    Abstract: Provided is a semiconductor device including a transistor with large on-state current even when it is miniaturized. The transistor includes a pair of first conductive films over an insulating surface; a semiconductor film over the pair of first conductive films; a pair of second conductive films, with one of the pair of second conductive films and the other of the pair of second conductive films being connected to one of the pair of first conductive films and the other of the pair of first conductive films, respectively; an insulating film over the semiconductor film; and a third conductive film provided in a position overlapping with the semiconductor film over the insulating film. Further, over the semiconductor film, the third conductive film is interposed between the pair of second conductive films and away from the pair of second conductive films.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: September 2, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Atsuo Isobe, Toshinari Sasaki
  • Patent number: 8822995
    Abstract: A display substrate includes a switching transistor electrically connected to a gate line and a data line, the data line extending in a first direction substantially perpendicular to the gate line extending in a second direction, the switching transistor including a switching active pattern comprising amorphous silicon, a driving transistor electrically connected to a driving voltage line and the switching transistor, the driving voltage line extended in the first direction, the driving transistor including a driving active pattern comprising a metal oxide; and a light-emitting element electrically connected to the driving transistor.
    Type: Grant
    Filed: June 17, 2009
    Date of Patent: September 2, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Chun-Gi You, Kap-Soo Yoon, Gug-Rae Jo, Sung-Hoon Yang, Ki-Hun Jeong, Seung-Hwan Shim, Jae-Ho Choi
  • Publication number: 20140239289
    Abstract: In general, according to one embodiment, a semiconductor device includes a first electrode, an oxide semiconductor film, an insulating film, a first protective film, second and third electrodes. The oxide semiconductor film is provided on the first electrode. The oxide semiconductor film includes a first face on the first electrodes side and a second face on a side opposite to the first face. The insulating film is provided between the first electrode and the oxide semiconductor film. The first protective film includes a first film provided between the insulating film and the first face and a second film provided on the second face. The first protective film suppresses substances including hydrogen from being introduced from an outer side of the oxide semiconductor film to an inner side of the oxide semiconductor film. The second electrode and the third electrode are electrically connected to the oxide semiconductor film.
    Type: Application
    Filed: June 25, 2013
    Publication date: August 28, 2014
    Applicants: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tetsu MOROOKA, Tatsuya OHGURO, Hisayo MOMOSE, Kazuya FUKASE
  • Publication number: 20140239299
    Abstract: The semiconductor device includes a first conductive layer over a substrate; an oxide semiconductor layer which covers the first conductive layer; a second conductive layer in a region which is not overlapped with the first conductive layer over the oxide semiconductor layer; an insulating layer which covers the oxide semiconductor layer and the second conductive layer; and a third conductive layer in a region including at least a region which is not overlapped with the first conductive layer or the second conductive layer over the insulating layer.
    Type: Application
    Filed: May 8, 2014
    Publication date: August 28, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kei Takashi, Yoshiaki Ito
  • Publication number: 20140242749
    Abstract: Electrical characteristics of transistors using an oxide semiconductor are greatly varied in a substrate, between substrates, and between lots, and the electrical characteristics are changed due to heat, bias, light, or the like in some cases. In view of the above, a semiconductor device using an oxide semiconductor with high reliability and small variation in electrical characteristics is manufactured. In a method for manufacturing a semiconductor device, hydrogen in a film and at an interface between films is removed in a transistor using an oxide semiconductor. In order to remove hydrogen at the interface between the films, the substrate is transferred under a vacuum between film formations. Further, as for a substrate having a surface exposed to the air, hydrogen on the surface of the substrate may be removed by heat treatment or plasma treatment.
    Type: Application
    Filed: May 6, 2014
    Publication date: August 28, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei YAMAZAKI
  • Publication number: 20140239296
    Abstract: A transistor or the like having high field-effect mobility is provided. A transistor or the like having stable electrical characteristics is provided. A semiconductor device including a first oxide semiconductor layer, a second oxide semiconductor layer, a gate insulating film, and a gate electrode which partly overlap with one another is provided. The second oxide semiconductor layer is positioned between the first oxide semiconductor layer and the gate insulating film. The gate insulating film is positioned between the second oxide semiconductor layer and the gate electrode. The first oxide semiconductor layer has fewer oxygen vacancies than those of the second oxide semiconductor layer.
    Type: Application
    Filed: February 26, 2014
    Publication date: August 28, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hajime Tokunaga, Takuya Handa, Kenichi Okazaki
  • Publication number: 20140239291
    Abstract: According to example embodiments a TFT includes: a substrate; a gate electrode on the substrate; a gate insulating layer on the gate electrode; a channel layer on the gate insulating layer, the channel layer including an indium-rich metal-oxide layer; a first electrode on one end of the channel layer; a second electrode on the other end of the channel layer; and a passivation layer on the channel layer between the first and second electrodes.
    Type: Application
    Filed: October 24, 2013
    Publication date: August 28, 2014
    Applicants: INHA-INDUSTRY PARTNERSHIP INSTITUTE, SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyoung-seok SON, Myung-kwan RYU, Jae-Kyeong JEONG
  • Publication number: 20140239298
    Abstract: A highly reliable semiconductor device is manufactured by giving stable electric characteristics to a transistor in which an oxide semiconductor film is used for a channel. An oxide semiconductor film which can have a first crystal structure by heat treatment and an oxide semiconductor film which can have a second crystal structure by heat treatment are formed so as to be stacked, and then heat treatment is performed; accordingly, crystal growth occurs with the use of an oxide semiconductor film having the second crystal structure as a seed, so that an oxide semiconductor film having the first crystal structure is formed. An oxide semiconductor film formed in this manner is used for an active layer of the transistor.
    Type: Application
    Filed: May 6, 2014
    Publication date: August 28, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei YAMAZAKI, Masahiro TAKAHASHI, Tetsunori MARUYAMA
  • Publication number: 20140239292
    Abstract: Provided are a method of forming an oxide thin film and an electrical device and thin film transistor using the method. The method includes forming an oxide thin film on a substrate by applying a precursor solution; and performing a thermal treatment process on the substrate under a pressurized atmosphere using a gas at about 100° C. to about 400° C.
    Type: Application
    Filed: November 22, 2011
    Publication date: August 28, 2014
    Applicant: Industry-Academic Cooperation Foundation Yonsei University
    Inventors: Hyun Jae Kim, Hyun Soo Shin, You Seung Rim
  • Publication number: 20140239290
    Abstract: The TFT substrate includes a gate electrode disposed on an insulating substrate; a gate insulating layer disposed on the gate electrode; a source/drain electrode disposed on the gate insulating layer; and an oxide semiconductor layer disposed between the gate insulating layer and the source/drain electrode. The oxide semiconductor layer includes a first portion that does not contact the source/drain electrode and in which a channel region is defined and a second portion in which a contact region that contacts the source/drain electrode is defined. The second portion includes a first oxide semiconductor layer and a second oxide semiconductor layer disposed on the first oxide semiconductor layer.
    Type: Application
    Filed: October 17, 2013
    Publication date: August 28, 2014
    Applicant: SAMSUNG DISPLAY CO., LTD.
    Inventor: Hyeon Sik KIM
  • Patent number: 8815619
    Abstract: A method of manufacturing a display unit includes: forming, on a substrate, a thin-film transistor having an oxide semiconductor layer; and forming, above the thin-film transistor, a display region that includes a plurality of display elements. The oxide semiconductor layer is formed using a sputtering method in which a target and the substrate are opposed to each other. The target is made of an oxide semiconductor and includes a plurality of divided portions that are jointed in a planar form. A spacing interval between two joints that are formed by the plurality of divided portions and are side-by-side with one another of the target is equal to or less than a width of a luminance distribution arising in the display region in a direction substantially orthogonal to the joints.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: August 26, 2014
    Assignee: Sony Corporation
    Inventors: Toshiaki Arai, Takashige Fujimori
  • Patent number: 8815640
    Abstract: A highly reliable semiconductor device and a method for manufacturing the semiconductor device are provided. In a semiconductor device including a bottom-gate transistor in which an insulating layer functioning as a channel protective film is provided over an oxide semiconductor film, elements contained in an etching gas can be prevented from remaining as impurities on a surface of the oxide semiconductor film by performing impurity-removing process after formation of an insulating layer provided over and in contact with the oxide semiconductor film and/or formation of source and drain electrode layers. The impurity concentration in the surface of the oxide semiconductor film is lower than or equal to 5×1018 atoms/cm3, preferably lower than or equal to 1×1018 atoms/cm3.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: August 26, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Katsuaki Tochibayashi, Satoshi Higano, Shunpei Yamazaki
  • Publication number: 20140231798
    Abstract: A thin film transistor includes a gate electrode; a gate insulating film which contacts the gate electrode; an oxide semiconductor layer which includes a first region represented by In(a) Ga(b) Zn(c) O(d), wherein 0<a?37/60, 3a/7?3/14?b?91a/74?17/40, b>0, 0<c<3/5, a+b+c=1, and d>0, and a second region represented by In(p) Ga(q) Zn(r) O(s), wherein q/(p+q)>0.250, p>0, q>0, r>0, and s>0, and located farther than the first region with respect to the gate electrode and which is arranged facing the gate electrode with the gate insulating film provided therebetween; and a source electrode and a drain electrode which are arranged so as to be apart from each other and are capable of being electrically conducted through the oxide semiconductor layer.
    Type: Application
    Filed: February 7, 2014
    Publication date: August 21, 2014
    Applicant: FUJIFILM CORPORATION
    Inventors: Masashi ONO, Masahiro Takata, Atsushi Tanaka, Masayuki Suzuki
  • Publication number: 20140235015
    Abstract: An object is to provide an oxide semiconductor having stable electric characteristics and a semiconductor device including the oxide semiconductor. A manufacturing method of a semiconductor film by a sputtering method includes the steps of holding a substrate in a treatment chamber which is kept in a reduced-pressure state; heating the substrate at lower than 400° C.; introducing a sputtering gas from which hydrogen and moisture are removed in the state where remaining moisture in the treatment chamber is removed; and forming an oxide semiconductor film over the substrate with use of a metal oxide which is provided in the treatment chamber as a target. When the oxide semiconductor film is formed, remaining moisture in a reaction atmosphere is removed; thus, the concentration of hydrogen and the concentration of hydride in the oxide semiconductor film can be reduced. Thus, the oxide semiconductor film can be stabilized.
    Type: Application
    Filed: April 24, 2014
    Publication date: August 21, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei YAMAZAKI, Junichiro SAKATA, Akiharu MIYANAGA, Masayuki SAKAKURA, Junichi KOEZUKA, Tetsunori MARUYAMA, Yuki IMOTO
  • Publication number: 20140235014
    Abstract: A method for manufacturing a structure comprising a substrate made of at least one n-type semiconducting metal oxide is disclosed. In one aspect, the method comprises providing a substrate made of at least one n-type semiconducting metal oxide selected from the group consisting of: ZnO, CdO, MgO, ZnMgO, and ZnCdO, wherein the doping rate of which is less than or equal to 1018/cm3. The method further comprises depositing a layer which is 1 to 10 nm thick, made of an electrically insulating metal or metalloid oxide, having a dielectric constant which is at least equal to 4, on the first main surface of the substrate. The method further comprises annealing of the electrically insulating metal or metalloid oxide layer in an oxygen atmosphere. The method further comprises depositing at least one layer made of an electrically conductive material on the electrically insulating metal or metalloid oxide layer.
    Type: Application
    Filed: December 18, 2013
    Publication date: August 21, 2014
    Applicant: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventor: Ivan-Christophe Robin
  • Patent number: 8809115
    Abstract: To provide a method for manufacturing a thin film transistor in which contact resistance between an oxide semiconductor layer and source and drain electrode layers is small, the surfaces of the source and drain electrode layers are subjected to sputtering treatment with plasma and an oxide semiconductor layer containing In, Ga, and Zn is formed successively over the source and drain electrode layers without exposure of the source and drain electrode layers to air.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: August 19, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Masashi Tsubuku
  • Patent number: 8809852
    Abstract: One of objects is to provide a semiconductor film having stable characteristics. Further, one of objects is to provide a semiconductor element having stable characteristics. Further, one of objects is to provide a semiconductor device having stable characteristics. Specifically, a structure which includes a seed crystal layer (seed layer) including crystals each having a first crystal structure, one of surfaces of which is in contact with an insulating surface, and an oxide semiconductor film including crystals growing anisotropically, which is on the other surface of the seed crystal layer (seed layer) may be provided. With such a heterostructure, electric characteristics of the semiconductor film can be stabilized.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: August 19, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiro Takahashi, Tetsunori Maruyama
  • Patent number: 8809114
    Abstract: A method of forming a memory cell is provided that includes forming a steering element above a substrate, forming a material layer on the substrate, patterning and etching the material layer, and oxidizing the patterned and etched material layer to form a reversible resistance-switching material. Numerous other aspects are provided.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: August 19, 2014
    Assignee: SanDisk 3D LLC
    Inventors: April D. Schricker, S. Brad Herner, Mark H. Clark