Including Contaminant Removal Or Mitigation Patents (Class 438/115)
  • Patent number: 10014234
    Abstract: The patterning technique used for forming sophisticated metallization systems of semiconductor devices may be monitored and evaluated more efficiently by incorporating at least one via line feature into the die seal. In this manner, high statistical significance may be obtained compared to conventional strategies, in which the respective test structures for evaluating patterning processes may be provided at specific sites in the frame region and/or die region. Moreover, by providing a “long” via line feature, superior sensitivity for variations of depth of focus may be achieved.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: July 3, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Dirk Breuer, Maik Liebau, Matthias Lehr
  • Patent number: 9499397
    Abstract: Microelectronic packages and methods for producing microelectronic packages are provided. In one embodiment, the method includes bonding a first Microelectromechanical Systems (MEMS) die having a first MEMS transducer structure thereon to a cap piece. The first MEMS die and cap piece are bonded such that a first hermetically-sealed cavity is formed enclosing the first MEMS transducer. A second MEMS die having a second MEMS transducer structure thereon is further bonded to one of the cap piece and the second MEMS die. The second MEMS die and the cap piece are bonded such that a second hermetically-sealed cavity is formed enclosing the second MEMS transducer. The second hermetically-sealed cavity contains a different internal pressure than does the first hermetically-sealed cavity.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: November 22, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Philip H. Bowles, Stephen R. Hooper
  • Patent number: 9416003
    Abstract: A semiconductor die includes a device structure having a micro-electronic device located at a surface of a substrate and a cap coupled to the device structure with the micro-electronic device positioned in a cavity located between the cap and the substrate. A sacrificial material is provided within the cavity, coupling the cap to the device structure. The sacrificial material is heated in the cavity to cause the sacrificial material to decompose to a gaseous species. The presence of the gaseous species in the cavity increases a pressure level in the cavity from an initial pressure to a final pressure.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: August 16, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventor: Matthieu Lagouge
  • Patent number: 9298109
    Abstract: An EUV lithography apparatus (1) includes: a light source (15) for generating radiation (17) for the illumination of particles (P) present in the gas phase and present in the EUV lithography apparatus (1) along a light area (18), and a detector, for detecting radiation (17a) from the light source (15) that is scattered at the illuminated particles (P) in a test region (19) captured by the detector. Also, a method for detecting particles (P) in an EUV lithography apparatus (1) includes: producing a light area (18) for illuminating the particles (P) present in the gas phase, detecting radiation (17a) scattered at the illuminated particles (P) in a test region (19), and determining a number (N) of particles in the test region (19) on the basis of the detected radiation (17a).
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: March 29, 2016
    Assignee: Carl Zeiss SMT GmbH
    Inventors: Vera Butscher, Dirk Heinrich Ehm
  • Patent number: 9230884
    Abstract: A substrate may include: a base material having a predetermined thickness; an electrode section formed on one side surface in a thickness direction of the base material, and having a plurality of electrodes; and a concave section formed on at least a part of the surface on which the electrode section is formed, on the base material.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: January 5, 2016
    Assignee: OLYMPUS CORPORATION
    Inventors: Yoshiaki Takemoto, Haruhisa Saito, Hiroshi Kikuchi
  • Patent number: 9122047
    Abstract: This disclosure provides systems, methods and apparatus for preventing particles from entering electromechanical systems (EMS) display devices. In one aspect, an apparatus includes a plate, a substrate supporting at least one EMS device, a seal joining the plate and the substrate to define a cavity therebetween and at least one port for receiving a fluid, and a filter disposed between the port and the EMS device. The filter includes elements formed on at least one of a surface of the substrate and a surface of the plate, defining a gap sized to allow the received fluid to pass and to inhibit non-fluidic particles carried in the fluid from the EMS device.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: September 1, 2015
    Assignee: Pixtronix, Inc.
    Inventors: Eugene E. Fike, III, Timothy J. Brosnihan
  • Patent number: 9105703
    Abstract: Disclosed is a III-nitride heterojunction device that includes a conduction channel having a two dimensional electron gas formed at an interface between a first III-nitride material and a second III-nitride material. A modification including a contact insulator, for example, a gate insulator formed under a gate contact, is disposed over the conduction channel, wherein the contact insulator includes aluminum to alter formation of the two dimensional electron gas at the interface. The contact insulator can include AlSiN, or can be SiN doped with aluminum. The modification results in programming the threshold voltage of the III-nitride heterojunction device to, for example, make the device an enhancement mode device. The modification can further include a recess, an ion implanted region, a diffused region, an oxidation region, and/or a nitridation region. In one embodiment, the first III-nitride material comprises GaN and the second III-nitride material comprises AlGaN.
    Type: Grant
    Filed: February 4, 2011
    Date of Patent: August 11, 2015
    Assignee: International Rectifier Corporation
    Inventor: Michael A. Briere
  • Patent number: 9023675
    Abstract: A process for encapsulating a microelectronic device, comprising the following steps: make the microelectronic device on a first substrate; make one portion of a first material not permeable to the ambient atmosphere and permeable to a noble gas in a second substrate comprising a second material not permeable to the ambient atmosphere and the noble gas; secure the second substrate to the first substrate, forming at least one cavity inside which the microelectronic device is encapsulated such that said portion of the first material forms part of a wall of the cavity; inject the noble gas into the cavity through the portion of the first material; hermetically seal the cavity towards the ambient atmosphere and the noble gas.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: May 5, 2015
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventor: Stephane Nicolas
  • Patent number: 9006036
    Abstract: To provide a semiconductor device having an improved quality. The semiconductor device of the invention has a tape substrate having a semiconductor chip thereon, a plurality of land pads placed around the semiconductor chip, a plurality of wires for electrically coupling the electrode pad of the semiconductor chip to the land pad, and a plurality of terminal portions provided on the lower surface of the tape substrate. An average distance between local peaks of the surface roughness of a first region between the land pad of the tape substrate and the semiconductor chip is smaller than an average distance of local peaks of the surface roughness of a second region between the land pad of the tape substrate and the first region.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: April 14, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Tomoko Higashino, Yuichi Morinaga, Kazuya Tsuboi, Tamaki Wada
  • Patent number: 8987923
    Abstract: Among other things, a semiconductor seal ring and method for forming the same are provided. The semiconductor seal ring comprises a plurality of dielectric layers formed over a semiconductor substrate upon which a semiconductor device is formed. A plurality of conductive layers is arranged among at least some of the plurality of dielectric layers. An upper conductive layer is formed over the plurality of dielectric layers. An upper passivation layer is formed over the upper conductive layer to isolate the upper conductive layer from conductive debris resulting from a die saw process along a die saw cut line. In an example, a first columnar region comprising a first portion of the conductive layers is electrically isolated from the semiconductor device because the first columnar region is disposed relatively close to the die saw cut line and thus can be exposed to conductive debris which can cause undesired short circuits.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: March 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chien-Chih Chou, Huei-Ru Liou, Kong-Beng Thei
  • Patent number: 8957503
    Abstract: A package includes a semiconductor device including an active surface having a contact pad. A redistribution layer (RDL) structure includes a first post-passivation interconnection (PPI) line electrically connected to the contact pad and extending on the active surface of the semiconductor device. An under-bump metallurgy (UBM) layer is formed over and electrically connected to the first PPI line. A seal ring structure extends around the upper periphery of the semiconductor device. The seal ring structure includes a seal layer extending on the same level as at least one of the first PPI line and the UBM layer.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: February 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ying Yang, Hsien-Wei Chen, Tsung-Yuan Yu, Shih-Wei Liang
  • Patent number: 8951844
    Abstract: A semiconductor device production method includes: treating a wafer which contains a silicon substrate with dilute hydrofluoric acid in a bath; introducing water into the bath while discharging the dilute hydrofluoric acid from the bath; and introducing H2O2 and warm water warmer than the above-mentioned water into the bath after the discharge of dilute hydrofluoric acid from the bath in such a manner that the introduction of warm water is started simultaneously with the start of H2O2 supply or subsequently to the start of H2O2 supply.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: February 10, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Naomi Yanai, Yuka Kase, Hiroyuki Ogawa
  • Patent number: 8912025
    Abstract: A method of fabricating LED devices includes using a laser to form trenches between the LEDs and then using a chemical solution to remove slag creating by the laser.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: December 16, 2014
    Assignee: Soraa, Inc.
    Inventors: Andrew J. Felker, Rafael L. Aldaz, Max Batres
  • Publication number: 20140346657
    Abstract: A method for sealing cavities in micro-electronic/-mechanical system (MEMS) devices to provide a controlled atmosphere within the sealed cavity includes providing a semiconductor substrate on which a template is provided on a localized area of the substrate. The template defines the interior shape of the cavity. Holes are made so as to enable venting of the cavity to provide a desired atmosphere to enter into the cavity through the hole. Finally, a sealing material is provided in the hole to seal the cavity. The sealing can be made by compression and/or melting of the sealing material.
    Type: Application
    Filed: December 17, 2012
    Publication date: November 27, 2014
    Applicant: SILEX MICROSYSTEMS AB
    Inventors: Thorbjorn Ebefors, Niklas Svedin
  • Publication number: 20140342487
    Abstract: A process for encapsulating a microelectronic device, comprising the following steps: make the microelectronic device on a first substrate; make one portion of a first material not permeable to the ambient atmosphere and permeable to a noble gas in a second substrate comprising a second material not permeable to the ambient atmosphere and the noble gas; secure the second substrate to the first substrate, forming at least one cavity inside which the microelectronic device is encapsulated such that said portion of the first material forms part of a wall of the cavity; inject the noble gas into the cavity through the portion of the first material; hermetically seal the cavity towards the ambient atmosphere and the noble gas.
    Type: Application
    Filed: April 29, 2014
    Publication date: November 20, 2014
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT
    Inventor: Stephane NICOLAS
  • Patent number: 8878355
    Abstract: A system and method for bonding semiconductor devices is provided. An embodiment comprises halting the flow of a eutectic bonding material by providing additional material of one of the reactants in a grid pattern, such that, as the eutectic material flows into the additional material, the additional material will change the composition of the flowing eutectic material and solidify the material, thereby stopping the flow. Other embodiments provide for additional layouts to put the additional material into the path of the flowing eutectic material.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: November 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Sung Chang, Nien-Tsung Tsai, Ting-Hau Wu, Yi Heng Tsai
  • Publication number: 20140306312
    Abstract: A micro electro mechanical systems (MEMS sensor packaging includes a first wafer having a readout integrated circuit (ROIC) formed thereon., a second wafer disposed corresponding to the first wafer and having a concave portion on one side thereof and a MEMS sensor prepared on the concave portion, joint solders formed along a surrounding of the MEMS sensor and sealing the MEMS sensor jointing the first and second wafers, and pad solders formed to electrically connect the ROIC circuit of the first wafer and the MEMS sensor of the second wafer. According to the present disclosure, in joining and packaging a wafer having the ROIC formed thereon and a wafer having the MEMS sensor formed thereon, the size of a package can be reduced and an electric signal can be stably provided by forming internally pad solders for electrically connecting the ROIC and the MEMS sensor.
    Type: Application
    Filed: November 9, 2012
    Publication date: October 16, 2014
    Inventors: Yong Hee Han, Hyung Won Kim, Mi Sook Ahn
  • Publication number: 20140175405
    Abstract: A package structure of an electronic device is provided. The substrate of such package structure has at least one embedded gas barrier structure, which protects the electronic device mounted thereon and offers good gas barrier capability so as to extend the life of the electronic device.
    Type: Application
    Filed: November 27, 2013
    Publication date: June 26, 2014
    Applicant: Industrial Technology Research Institute
    Inventors: Shu-Tang Yeh, Jia-Chong Ho
  • Patent number: 8741175
    Abstract: A desiccant composition containing a polymeric binder and a dispersion of powders of desiccant materials is described. The desiccant composition has desiccant powders that are dispersed at least in part in form of micro-aggregates of desiccant particles surrounded by a polymeric encapsulating material having a different composition with respect to the polymeric binder.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 3, 2014
    Assignee: Saes Getters S.p.A.
    Inventors: Giorgio Macchi, Alessandra Colombo, Paolo Vacca, Roberto Giannantonio
  • Patent number: 8716852
    Abstract: A device includes a capping substrate bonded with a substrate structure. The substrate structure includes an integrated circuit structure. The integrated circuit structure includes a top metallic layer disposed on an outgasing prevention structure. At least one micro-electro mechanical system (MEMS) device is disposed over the top metallic layer and the outgasing prevention structure.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: May 6, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Pao Shu, Chia-Ming Hung, Wen-Chuan Tai, Hung-Sen Wang, Hsiang-Fu Chen, Alex Kalnitsky
  • Patent number: 8624359
    Abstract: A wafer level chip scale package (WLCSP) includes a semiconductor device including an active surface having a contact pad, and side surfaces. A mold covers the side surfaces of the semiconductor device. A RDL structure includes a first PPI line electrically connected to the contact pad and extending on the active surface of the semiconductor device. A UBM layer is formed over and electrically connected to the first PPI line. A seal ring structure extends around the upper periphery of the semiconductor device on the mold. The seal ring structure includes a seal layer extending on the same level as at least one of the first PPI line and the UBM layer. A method of manufacturing a WLCSP includes forming a re-routing laminated structure by simultaneously forming an interconnection line and a seal layer on the molded semiconductor devices.
    Type: Grant
    Filed: October 5, 2011
    Date of Patent: January 7, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ying Yang, Hsien-Wei Chen, Tsung-Yuan Yu, Shih-Wei Liang
  • Patent number: 8597982
    Abstract: In an embodiment of the present invention, a method is provided for fabricating an electronics assembly having a substrate and a plurality of circuit elements. The method includes forming a liquid barrier on the substrate, placing a first circuit element on one side of the liquid barrier, and placing a second circuit element on the opposite side of the liquid barrier. A liquid is applied to the first circuit element. The method further includes using the liquid barrier to prevent the liquid applied to the first circuit element from contaminating the second circuit element so that the spacing between the first and second circuit elements can be minimized.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: December 3, 2013
    Assignee: Nordson Corporation
    Inventors: David K. Foote, James D. Getty, Jiangang Zhao
  • Patent number: 8592222
    Abstract: A method for analyzing molecular pollutants of a fluid. From a calibrated flow of fluid, a combination of a measurement of a total amount of molecular pollutants and a determination of chemical compositions and relative amounts of the molecular pollutants by adsorption on materials is carried out. The determination of the chemical compositions and relative amounts advantageously occur after a threshold value for the total measured amount is exceeded.
    Type: Grant
    Filed: October 9, 2009
    Date of Patent: November 26, 2013
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventor: Isabelle Tovena-Pecault
  • Patent number: 8586422
    Abstract: A semiconductor device is made by providing a semiconductor die having an optically active area, providing a leadframe or pre-molded laminated substrate having a plurality of contact pads and a light transmitting material disposed between the contact pads, attaching the semiconductor die to the leadframe so that the optically active area is aligned with the light transmitting material to provide a light transmission path to the optically active area, and disposing an underfill material between the semiconductor die and leadframe. The light transmitting material includes an elevated area to prevent the underfill material from blocking the light transmission path. The elevated area includes a dam surrounding the light transmission path, an adhesive ring, or the light transmission path itself can be the elevated area. An adhesive ring can be disposed on the dam. A filler material can be disposed between the light transmitting material and contact pads.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: November 19, 2013
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Zigmund R Camacho, Henry D Bathan, Lionel Chien Hui Tay, Amel Senosa Trasporto
  • Patent number: 8569877
    Abstract: Embodiments of the present invention are directed to metallic solderability preservation coating on connectors of semiconductor package to prevent oxide. Singulated semiconductor packages can have contaminants, such as oxides, on exposed metal areas of the connectors. Oxidation typically occurs on the exposed metal areas when the semiconductor packages are not stored in appropriate environments. Copper oxides prevent the connectors from soldering well. An anti-tarnish solution of the present invention is used to coat the connectors during sawing, after sawing, or both of a semiconductor array to preserve metallic solderability. The anti-tarnish solution is a metallic solution, which advantageously allows the semiconductor packages to not need be assembled immediately after fabrication.
    Type: Grant
    Filed: October 15, 2009
    Date of Patent: October 29, 2013
    Assignee: UTAC Thai Limited
    Inventors: Woraya Benjavasukul, Thipyaporn Somrubpornpinan, Panikan Charapaka
  • Patent number: 8546928
    Abstract: The present application relates to a multiple component which is to be subsequently individualized by forming components containing active structures, in addition to a corresponding component which can be used in microsystem technology systems. The multiple component and/or component comprises a flat substrate and also a flat cap structure which are bound to each other such that they surround at least one first and one second cavity per component, which are sealed against each other and towards the outside. The first of the two cavities is provided with getter material and due to the getter material has a different internal pressure and/or a different gas composition than the second cavity. The present application also relates to a method for producing the type of component and/or components for which gas mixtures of various types of gas have a different absorption ratio in relation to the getter material.
    Type: Grant
    Filed: April 4, 2007
    Date of Patent: October 1, 2013
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e. V.
    Inventors: Peter Merz, Wolfgang Reinert, Marten Oldsen, Oliver Schwarzelbach
  • Patent number: 8536605
    Abstract: Using compression molding to form lenses over LED arrays on a metal core printed circuit board leaves a flash layer of silicone covering the contact pads that are later required to connect the arrays to power. A method for removing the flash layer involves blasting particles of sodium bicarbonate at the flash layer. A nozzle is positioned within thirty millimeters of the top surface of the flash layer. The stream of air that exits from the nozzle is directed towards the top surface at an angle between five and thirty degrees away from normal to the top surface. The particles of sodium bicarbonate are added to the stream of air and then collide into the top surface of the silicone flash layer until the flash layer laterally above the contact pads is removed. The edge of silicone around the cleaned contact pad thereafter contains a trace amount of sodium bicarbonate.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: September 17, 2013
    Assignee: Bridgelux, Inc.
    Inventors: R. Scott West, Tao Tong, Mike Kwon
  • Patent number: 8524538
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit over the substrate, the integrated circuit having an inactive side and a non-horizontal side; mounting a mold chase having a buffer layer over the integrated circuit; forming an encapsulation between the substrate and the buffer; and removing the mold chase, leaving the encapsulation having a recess exposing a portion of the non-horizontal side.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: September 3, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: JaeHyun Lee, Ki Youn Jang, DokOk Yu
  • Publication number: 20130214400
    Abstract: A device includes a capping substrate bonded with a substrate structure. The substrate structure includes an integrated circuit structure. The integrated circuit structure includes a top metallic layer disposed on an outgasing prevention structure. At least one micro-electro mechanical system (MEMS) device is disposed over the top metallic layer and the outgasing prevention structure.
    Type: Application
    Filed: February 17, 2012
    Publication date: August 22, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Pao SHU, Chia-Ming HUNG, Wen-Chuan TAI, Hung-Sen WANG, Hsiang-Fu CHEN, Alex KALNITSKY
  • Publication number: 20130207248
    Abstract: A device for a space application, the device including at least one electronic, electromechanical or electro-optical component encapsulated in a package, the package comprising a hydrogen getter guaranteeing resistance to ionizing radiation and in particular at a low dose rate, responsible for ELDRS behavior. In one embodiment, the package may include a cap that hermetically seals a package base. Advantageously, a process may be implemented in order to promote the migration of hydrogen molecules or H+ protons toward the getter and trap said molecules or protons in the getter for the useful lifetime of the component.
    Type: Application
    Filed: February 8, 2011
    Publication date: August 15, 2013
    Applicant: THALES
    Inventors: Alain Bensoussan, Ronan Marec
  • Patent number: 8497525
    Abstract: A high-quality light emitting device is provided which has a long-lasting light emitting element free from the problems of conventional ones because of a structure that allows less degradation, and a method of manufacturing the light emitting device is provided. After a bank is formed, an exposed anode surface is wiped using a PVA (polyvinyl alcohol)-based porous substance or the like to level the surface and remove dusts from the surface. An insulating film is formed between an interlayer insulating film on a TFT and the anode. Alternatively, plasma treatment is performed on the surface of the interlayer insulating film on the TFT for surface modification.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: July 30, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hirokazu Yamagata, Shunpei Yamazaki, Toru Takayama
  • Patent number: 8481342
    Abstract: A method for manufacturing a semiconductor device, includes: a step of etching a Si (111) substrate along a (111) plane of the Si (111) substrate to separate a Si (111) thin-film device having a separated surface along the (111) plane.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: July 9, 2013
    Assignee: Oki Data Corporation
    Inventors: Mitsuhiko Ogihara, Tomohiko Sagimori, Takahito Suzuki, Masataka Muto
  • Patent number: 8481364
    Abstract: A fabrication method for integrating chip(s) onto a flexible substrate in forming a flexible micro-system. The method includes a low-temperature flip-chip and a wafer-level fabrication process. Using the low-temperature flip-chip technique, the chip is bonded metallically onto the flexible substrate. To separate the flexible substrate from the substrate, etching is used to remove the sacrificial layer underneath the flexible substrate. The instant disclosure applies standardized micro-fabrication process for integrating chip(s) onto the flexible substrate. Without using special materials or fabrication procedures, the instant disclosure offers a cost-effective fabrication method for flexible micro-systems.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: July 9, 2013
    Assignee: National Chiao Tung University
    Inventors: Tzu-Yuan Chao, Chia-Wei Liang, Yu-Ting Cheng
  • Patent number: 8461681
    Abstract: The present invention is directed to an interconnect for an implantable medical device. The interconnect includes a first conductive layer, a second conductive layer introduced over the first conductive layer, and a third conductive layer introduced over the second conductive layer. One of the first conductive layer, the second conductive layer, and the third conductive layer comprises titanium-niobium (Ti—Nb).
    Type: Grant
    Filed: April 27, 2007
    Date of Patent: June 11, 2013
    Assignee: Medtronic, Inc.
    Inventor: David A. Ruben
  • Patent number: 8435838
    Abstract: A MEMS device may be package with a desiccant to provide a moisture-free environment. In order to avoid undesirable effects on the MEMS device, the desiccant may be selected or treated so as to be compatible with a particular MEMS device. This treatment may include baking of the desiccant to as to cause outgassing of moisture or other undesirable material. The structure of the MEMS device may also be altered to improve compatibility with particular desiccants.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: May 7, 2013
    Assignee: QUALCOMM MEMS Technologies, Inc.
    Inventors: Yen Hua Lin, Rihui He, Lingling Wu, Lauren Palmateer, David Heald
  • Publication number: 20130105959
    Abstract: An encapsulation structure comprising at least one hermetically sealed cavity in which at least the following are encapsulated: a device, an electronic component produced on a first substrate, and a getter material layer covering the electronic component in order to block the gases capable of being degassed by the electronic component, and in which the device is not covered by the getter material layer.
    Type: Application
    Filed: October 26, 2012
    Publication date: May 2, 2013
    Applicant: Commissariat a I'energie atomique et aux energies alternatives
    Inventor: Commissariat a I'energie atomique et aux energies alternatives
  • Publication number: 20130109136
    Abstract: In an embodiment of the present invention, a method is provided for fabricating an electronics assembly having a substrate and a plurality of circuit elements. The method includes forming a liquid barrier on the substrate, placing a first circuit element on one side of the liquid barrier, and placing a second circuit element on the opposite side of the liquid barrier. A liquid is applied to the first circuit element.
    Type: Application
    Filed: October 31, 2011
    Publication date: May 2, 2013
    Applicant: NORDSON CORPORATION
    Inventors: David K. Foote, James D. Getty, Jiangang Zhao
  • Patent number: 8431443
    Abstract: Embodiments of the present invention are directed to metallic solderability preservation coating on connectors of semiconductor package to prevent oxide. Singulated semiconductor packages can have contaminants, such as oxides, on exposed metal areas of the connectors. Oxidation typically occurs on the exposed metal areas when the semiconductor packages are not stored in appropriate environments. Copper oxides prevent the connectors from soldering well. An anti-tarnish solution of the present invention is used to coat the connectors during sawing, after sawing, or both of a semiconductor array to preserve metallic solderability. The anti-tarnish solution is a metallic solution, which advantageously allows the semiconductor packages to not need be assembled immediately after fabrication.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: April 30, 2013
    Assignee: Utac Thai Limited
    Inventors: Woraya Benjavasukul, Thipyaporn Somrubpornpinan, Panikan Charapaka
  • Publication number: 20130089955
    Abstract: Process for encapsulating a micro-device in a cavity formed between one first and one second substrate, comprising at least the steps of: producing the micro-device in and/or on the first substrate, attaching and securing the second substrate to the first substrate, forming the cavity in which the micro-device is placed, producing at least one hole through one of the two substrates, called the drilled substrate, and leading into the cavity opposite a portion of the other of the two substrates, called the receiving substrate, depositing at least one getter material portion on said portion of the receiving substrate through the hole, hermetically sealing the cavity by closing the hole.
    Type: Application
    Filed: October 5, 2012
    Publication date: April 11, 2013
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Commissariat A L'Energie Atomique Et Aux Energies Alternatives
  • Publication number: 20130087914
    Abstract: A wafer level chip scale package (WLCSP) includes a semiconductor device including an active surface having a contact pad, and side surfaces. A mold covers the side surfaces of the semiconductor device. A RDL structure includes a first PPI line electrically connected to the contact pad and extending on the active surface of the semiconductor device. A UBM layer is formed over and electrically connected to the first PPI line. A seal ring structure extends around the upper periphery of the semiconductor device on the mold. The seal ring structure includes a seal layer extending on the same level as at least one of the first PPI line and the UBM layer. A method of manufacturing a WLCSP includes forming a re-routing laminated structure by simultaneously forming an interconnection line and a seal layer on the molded semiconductor devices.
    Type: Application
    Filed: October 5, 2011
    Publication date: April 11, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Ying YANG, Hsien-Wei CHEN, Tsung-Yuan YU, Shih-Wei LIANG
  • Patent number: 8409919
    Abstract: According to a manufacturing method of one embodiment, a first solder bump and a second solder bump are aligned and placed in contact with each other, and thereafter, the first and second solder bumps are heated to a temperature equal or higher than a melting point of the solder bumps and melted, whereby a partially connection body of the first solder bump and the second solder bump is formed. The partially connection body is cooled. The cooled partially connection body is heated to a temperature equal to or higher than the melting point of the solder bump in a reducing atmosphere, thereby to form a permanent connection body by melting the partially connection body while removing an oxide film existing on a surface of the partially connection body.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: April 2, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideo Aoki, Masatoshi Fukuda, Kanako Sawada, Yasuhiro Koshio
  • Patent number: 8399299
    Abstract: A method for making a structure including at least the steps of: making at least one first portion of at least one getter material against a first substrate or a second substrate, making at least one second portion of at least one getter material against the second substrate when the first portion of getter material is placed against the first substrate, or against the first substrate when the first portion of getter material is placed against the second substrate, and attaching the second substrate to the first substrate by thermocompression of a first part of the first portion of getter material against at least one part of the second portion of getter material, forming at least one cavity delimited by the first substrate and the second substrate, a second part of the first portion of getter material being placed in the cavity.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: March 19, 2013
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventor: Xavier Baillin
  • Patent number: 8389331
    Abstract: Apparatus and methods to protect circuitry from moisture ingress, e.g., using a metallic structure as part of a moisture ingress barrier.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: March 5, 2013
    Assignee: Medtronic, Inc.
    Inventors: Tyler Mueller, Geoffrey Batchelder, Ralph B. Danzl, Paul F. Gerrish, Anna J. Malin, Trevor D. Marrott, Michael F. Mattes
  • Patent number: 8373069
    Abstract: An electronic component mounting substrate including a support layer made of resin with first and second surfaces, an organic insulation layer on the first surface of the support layer with a first surface on opposite side of the first surface of the support layer and a second surface in contact with the first surface of the support layer, an inorganic insulation layer on the first surface of the organic layer, a conductor on the second surface of the support layer, and a first conductive circuit on the second surface of the organic layer. The inorganic layer has a second conductive circuit and a pad for mounting an electronic component inside the inorganic layer. The organic layer has a via conductor inside the organic layer and connecting the first and second circuits. The support layer has a conductive post inside the support layer and connecting the first circuit and the conductor.
    Type: Grant
    Filed: December 24, 2009
    Date of Patent: February 12, 2013
    Assignee: Ibiden Co., Ltd.
    Inventors: Takashi Kariya, Daiki Komatsu
  • Patent number: 8367476
    Abstract: Embodiments of the present invention are directed to metallic solderability preservation coating on connectors of semiconductor package to prevent oxide. Singulated semiconductor packages can have contaminants, such as oxides, on exposed metal areas of the connectors. Oxidation typically occurs on the exposed metal areas when the semiconductor packages are not stored in appropriate environments. Copper oxides prevent the connectors from soldering well. An anti-tarnish solution of the present invention is used to coat the connectors during sawing, after sawing, or both of a semiconductor array to preserve metallic solderability. The anti-tarnish solution is a metallic solution, which advantageously allows the semiconductor packages to not need be assembled immediately after fabrication.
    Type: Grant
    Filed: October 15, 2009
    Date of Patent: February 5, 2013
    Assignee: UTAC Thai Limited
    Inventors: Woraya Benjavasukul, Thipyaporn Somrubpornpinan, Panikan Charapaka
  • Patent number: 8343806
    Abstract: A method for forming an integrated circuit includes transforming at least a portion of a first substrate layer to form a conductive region within the first substrate layer. An integrated circuit device is provided proximate an outer surface of the first substrate layer. The integrated circuit device transmits or receives electrical signals through the conductive region. A second substrate layer is disposed proximate to the outer surface of the first substrate layer to enclose the integrated circuit device in a hermetic environment.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: January 1, 2013
    Assignee: Raytheon Company
    Inventors: Premjeet Chahal, Francis J. Morris
  • Publication number: 20120319245
    Abstract: A substrate with a vent for a semiconductor device where the vent is integrated within the substrate itself. The integrated air vent forms a passageway or relief path for gas or air within a mold cavity to escape during a transfer molding packaging process. The vents integrated in the substrate reduce trapped gas and mold voids and limit vent flash to improve yield.
    Type: Application
    Filed: June 15, 2011
    Publication date: December 20, 2012
    Applicant: FREESCALE SEMICONDUCTOR, INC
    Inventor: Boon Yew LOW
  • Publication number: 20120276677
    Abstract: The present invention is related shielding integrated devices using CMOS fabrication techniques to form an encapsulation with cavity. The integrated circuits are completed first using standard IC processes. A wafer-level hermetic encapsulation is applied to form a cavity above the sensitive portion of the circuits using IC-foundry compatible processes. The encapsulation and cavity provide a hermetic inert environment that shields the sensitive circuits from EM interference, noise, moisture, gas, and corrosion from the outside environment.
    Type: Application
    Filed: July 5, 2012
    Publication date: November 1, 2012
    Applicant: MCube, Inc.
    Inventor: XIAO (CHARLES) YANG
  • Patent number: 8283193
    Abstract: A method of manufacture an integrated circuit system includes: forming an insulation region in a base layer; filling an insulator in the insulation region around a perimeter of a main chip region; forming a contact directly on and within planar extents of the insulator; and forming an upper layer over the contact to protect the main chip region.
    Type: Grant
    Filed: August 14, 2009
    Date of Patent: October 9, 2012
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Soon Yoeng Tan, Teck Jung Tang
  • Patent number: 8268675
    Abstract: Methods of protecting a surface of a copper layer or a copper bonding pad on a semiconductor device against oxidation. A surface of the layer or bonding pad is cleaned by removing an oxidation layer with a plasma. A polymer layer is formed on the cleaned surface of the layer using a plasma-enhanced deposition process to protect the cleaned surface of the layer against exposure to an oxidizing gas.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: September 18, 2012
    Assignee: Nordson Corporation
    Inventors: David Keating Foote, James Donald Getty