Possessing Thermal Dissipation Structure (i.e., Heat Sink) Patents (Class 438/122)
  • Publication number: 20150008574
    Abstract: A semiconductor device includes an insulating substrate; a semiconductor element mounted on the insulating substrate; and a cooler cooling the semiconductor element. The cooler includes a heat radiating substrate bonded to the insulating substrate; a plurality of fins provided on a surface opposite to a surface bonded with the insulating substrate of the heat radiating substrate; and a case accommodating the fins, and including an inlet and an outlet for a coolant. Upper end portions of side walls of the case include cutaways to arrange end portions of the heat radiating substrate. The heat radiating substrate is liquid-tightly bonded to the case.
    Type: Application
    Filed: September 22, 2014
    Publication date: January 8, 2015
    Inventors: Hiromichi GOHARA, Akira MOROZUMI, Takafumi YAMADA
  • Patent number: 8921994
    Abstract: A method and apparatus are provided for manufacturing a lead frame based thermally enhanced package (9) with exposed heat spreader lid array (96) designed to be optimized for compression mold encapsulation of an integrated circuit die (94) by including a perimeter reservoir regions (97r) in each heat spreader lid (96) for movement of mold compound (98) displaced during the mold compression process.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: December 30, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Leo M. Higgins, III
  • Patent number: 8921160
    Abstract: A package comprises a die stack having at least two stacked dies coupled for contactless communications with each other. At least one of the stacked dies has a substrate joined to its major face. The substrate has a plurality of conductive traces in or on the substrate for conducting power to the dies and for conducting heat from the dies. At least one conductive pillar is joined to at least one of the conductive traces on at least a first edge of the substrate, for conducting power to the at least one die and for conducting heat from the at least one die.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: December 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ping-Lin Yang, Sa-Lly Liu, Chien-Min Lin
  • Publication number: 20140374891
    Abstract: A semiconductor device includes a die pad and a semiconductor die having a mounting surface attached to the die pad and an opposite, active surface with die external terminals. The device has package external connectors, each having a bond region selectively electrically coupled to the die external terminals with a bond wire. A heat spreader has a first region that encloses an inner recessed region. A thermally conductive sheet is sandwiched between the inner recessed region of the heat spreader and the active surface of the die. At least the die, die external terminals, and the bond region are covered with an encapsulant.
    Type: Application
    Filed: June 24, 2013
    Publication date: December 25, 2014
    Inventors: Boon Yew Low, Burton J. Carpenter, Navas Khan Oratti Kalandar
  • Publication number: 20140374896
    Abstract: A semiconductor device is fastened to a heat dissipation member such that a force directed downward acts from a metal substrate onto the heat dissipation member, with a rim portion of a storage region as a fulcrum with respect to the heat dissipation member. As a result, a heat conductive material can be spread into a thinner layer between the metal substrate and the heat dissipation member, improving the heat dissipation between the metal substrate and the heat dissipation member.
    Type: Application
    Filed: September 11, 2014
    Publication date: December 25, 2014
    Inventors: Yuhei NISHIDA, Tatsuo NISHIZAWA
  • Publication number: 20140377911
    Abstract: An electronic component includes a high voltage switching transistor encased in a package. The high voltage switching transistor comprises a source electrode, a gate electrode, and a drain electrode all on a first side of the high voltage switching transistor. The source electrode is electrically connected to a conducting structural portion of the package. Assemblies using the abovementioned transistor with another transistor can be formed, where the source of one transistor can be electrically connected to a conducting structural portion of a package containing the transistor and a drain of the second transistor is electrically connected to the second conductive structural portion of a package that houses the second transistor. Alternatively, the source of the second transistor is electrically isolated from its conductive structural portion, and the drain of the second transistor is electrically isolated from its conductive structural portion.
    Type: Application
    Filed: September 9, 2014
    Publication date: December 25, 2014
    Inventor: Yifeng Wu
  • Publication number: 20140377910
    Abstract: A leadless semiconductor package includes a package body on a leadframe that includes a die paddle and a plurality of bond pads, none of which extend as far as a lateral face of the body. During manufacture of the package, molding compound is deposited over a face of the leadframe on which the die paddle and bond pads are positioned. After the molding compound is cured, a back side of the leadframe is etched to isolate the die paddle and bond pads, back surfaces of which remain exposed at a back face of the body. During manufacture of the leadframe, a parent substrate is etched to define the die paddle and a plurality of bond pads on one side of the substrate and a plurality of cavities on the opposite face.
    Type: Application
    Filed: September 5, 2014
    Publication date: December 25, 2014
    Inventors: Jerry Tan, William Cabreros
  • Patent number: 8916962
    Abstract: Disclosed are semiconductor devices and methods for manufacturing them. An example device may include a III-nitride stack having a front side surface and a back side surface. The III-nitride stack may be formed of at least a first layer and a second layer, between which a heterojunction may be formed, such that a two-dimensional electron gas layer is formed in the second layer. A source electrode, a drain electrode, and a gate electrode positioned between the source and drain electrodes may be formed on the front side surface, and an insulation layer may be formed over the electrodes on the front side surface. A carrier substrate may be attached to the insulation layer. An electrically conductive back plate may be formed on the back side surface. The back plate may directly face the source electrode and the gate electrode, but not the drain electrode.
    Type: Grant
    Filed: December 10, 2013
    Date of Patent: December 23, 2014
    Assignee: IMEC
    Inventors: Sylvia Lenci, Stefaan Decoutere
  • Patent number: 8916964
    Abstract: A semiconductor device and a method of producing the same, wherein a joining member and a joined member are bonded by means of brazing in a way such that no voids are left inside the joining layer. The semiconductor device comprises a joined member and a joining member which is joined to the joined member by means of brazing. The joined member is provided with a through hole which is open on the joining surface with the joining member, and a path communicating with the through hole is provided on at least one of the joining surface of the joining member with the joined member or the joining surface of the member with the joining member.
    Type: Grant
    Filed: November 27, 2009
    Date of Patent: December 23, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Yasuji Taketsuna, Eisaku Kakiuchi, Katsuhiko Tatebe, Masahiro Morino, Tomohiro Takenaga
  • Patent number: 8916963
    Abstract: The invention relates to a power module (10), preferably for a vehicle, in particular an electric vehicle, characterized in that said module includes two vertically adjacent semiconducting chips (12, 14), each chip having a first surface (20, 22) to be connected to a heat sink substrate (24, 26), and a second surface (28, 30) separate from the first and on which at least one electronic component (38a-44b) is arranged, the module being arranged such that the second surfaces of the chips are arranged opposite one another.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: December 23, 2014
    Assignee: Valeo Etudes Electroniques
    Inventors: Jean-Michel Morelle, Ky Lim Tan, Laurent Vivet, Sandra Dimelli, Stéphane Thomelin, Hervé Lorin, Patrick Dubus
  • Publication number: 20140370660
    Abstract: A semiconductor device includes a substrate, a semiconductor element disposed on the substrate, and a heat conductive member composed of a solder material. The heat conductive member covers the semiconductor element, and is connected to a connection pad formed on the substrate. A heat radiator is disposed on the heat conductive member. The heat conductive member thermally connecting the semiconductor element to the heat radiator reduces the risk that electromagnetic noise may be emitted from or may be incident on the semiconductor element.
    Type: Application
    Filed: September 3, 2014
    Publication date: December 18, 2014
    Inventor: Takumi IHARA
  • Publication number: 20140367844
    Abstract: Heat spreaders for dissipating heat from semiconductor devices comprise a contact surface located within a recess on an underside of the heat spreader, the contact surface being configured to physically and thermally attach to a semiconductor device, and a trench extending into the heat spreader adjacent to the contact surface sized and configured to receive underfill material extending from the semiconductor device into the trench. Related semiconductor device assemblies may include these heat spreader and methods may include physically and thermally attaching these heat spreaders to semiconductor devices such that underfill material extends from a semiconductor device into the trench.
    Type: Application
    Filed: June 12, 2013
    Publication date: December 18, 2014
    Inventors: Andy E. Hooper, Xiao Li, Shijian Luo
  • Publication number: 20140367843
    Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, forming dielectric material surrounding the die, forming buildup layers in the dielectric material to form a coreless bumpless buildup package structure, and patterning the carrier material to form microchannel structures on the package structure.
    Type: Application
    Filed: June 2, 2014
    Publication date: December 18, 2014
    Inventors: Ravi K. Nalla, Mathew J. Manusharow
  • Publication number: 20140367702
    Abstract: An object is to provide a fin integrated type semiconductor device and a method of manufacturing the same, which are provided with a simple structure and good heat dissipation characteristics. The semiconductor device includes: a base plate on which fins arranged in a standing condition are formed on a first main face; an insulating layer formed on a second main face of the base plate, the second main face being opposite to the first main face of the base plate; a circuit pattern fixed to the insulating layer; and a semiconductor element joined to the circuit pattern. The fins are formed with slits that pass through in the thickness direction of the fins.
    Type: Application
    Filed: July 25, 2012
    Publication date: December 18, 2014
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kei Yamamoto, Kazuhiro Tada, Hideki Komori, Toru Kimura, Masaki Goto, Hiroyuki Yoshihara
  • Publication number: 20140367847
    Abstract: According to various aspects, exemplary embodiments are disclosed of thermal interface materials, electronic devices, and methods for establishing thermal joints between heat spreaders or lids and heat sources. In exemplary embodiments, a method of establishing a thermal joint for conducting heat between a heat spreader and a heat source of an electronic device generally includes positioning a thermal interface material (TIM1) between the heat spreader and the heat source.
    Type: Application
    Filed: June 3, 2014
    Publication date: December 18, 2014
    Applicant: Laird Technologies, Inc.
    Inventors: Jason L. Strader, Richard F. Hill
  • Patent number: 8907461
    Abstract: The subject matter of the present application relates to a heat dissipation device that is embedded within a microelectronic die. The heat dissipation device may be fabricated by forming at least one trench extending into the microelectronic die from a microelectronic die back surface, which opposes an active surface thereof, and filling the trenches with at least one layer of thermally conductive material. In one embodiment, the heat dissipation device may be a thermoelectric cooling device.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: December 9, 2014
    Assignee: Intel Corporation
    Inventors: Manohar S. Konchady, Mihir K. Roy
  • Patent number: 8906748
    Abstract: The present application provides a method and semiconductor packaging structure comprising a conductive substrate having a first surface, a first lateral surface and a second lateral surface adjacent to the first surface. A first electrode line with two ends are provided on the first surface and the first lateral surface, and a second electrode line with two ends are provided on the first surface and a second lateral surface respectively. A semiconductor device is provided on the first surface of the conductive substrate which electrically connected to the first electrode line and the second electrode line, a protective plate with through holes covers the first surface, and a sheathing overlays the semiconductor device.
    Type: Grant
    Filed: May 8, 2012
    Date of Patent: December 9, 2014
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Sei-Ping Louh
  • Patent number: 8907472
    Abstract: A structure includes a thermal interface material, and a Perforated Foil Sheet (PFS) including through-openings therein, with a first portion of the PFS embedded in the thermal interface material. An upper layer of the thermal interface material is overlying the PFS, and a lower layer of thermal interface material is underlying the PFS. The thermal interface material fills through-openings in the PFS.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: December 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Wensen Hung
  • Publication number: 20140353817
    Abstract: The subject matter of the present application relates to a heat dissipation device that is embedded within a microelectronic die. The heat dissipation device may be fabricated by forming at least one trench extending into the microelectronic die from a microelectronic die back surface, which opposes an active surface thereof, and filling the trenches with at least one layer of thermally conductive material. In one embodiment, the heat dissipation device may be a thermoelectric cooling device.
    Type: Application
    Filed: May 29, 2013
    Publication date: December 4, 2014
    Inventors: Manohar S Konchady, Mihir K. Roy
  • Publication number: 20140353814
    Abstract: A semiconductor device incorporating a heat spreader and improved to inhibit dielectric breakdown is provided. The semiconductor device has an electrically conductive heat spreader having a bottom surface, a sheet member having a front surface and a back surface electrically insulated from each other, IGBTs and diodes fixed on the heat spreader and electrically connected thereto, and a molding resin. The front surface contacts with the bottom surface and has a peripheral portion jutting out from edges thereof. The molding resin encapsulates the front surface of the sheet member, the heat spreader and the semiconductor elements. At least part of the back surface of the sheet member is exposed out of the molding resin. The heat spreader has, at a corner of its bottom surface, corner portions having a beveled shape or a curved-surface shape as seen in plan and having a rectangular shape as seen in section.
    Type: Application
    Filed: February 22, 2012
    Publication date: December 4, 2014
    Applicant: Mitsubishi Electric Corporation
    Inventors: Ken Sakamoto, Taketoshi Shikano, Taishi Sasaki
  • Publication number: 20140353816
    Abstract: A semiconductor device package (100) includes a heat spreader (503) formed by depositing a first thin film layer (301) of a first metal on a top surface (150) of a die (110) and to exposed portions of a top surface of an encapsulant (208), depositing a second thin film layer (402) of a second metal on a top surface of the first thin film layer, and depositing a third layer (503) of a third metal on a top surface of the second thin film layer.
    Type: Application
    Filed: May 28, 2013
    Publication date: December 4, 2014
    Inventors: Weng Foong YAP, Jinbang TANG
  • Patent number: 8901755
    Abstract: A semiconductor device has a substrate with a cavity. A conductive layer is formed within the cavity and over the substrate outside the cavity. A plurality of indentations can be formed in a surface of the substrate opposite the cavity for stress relief. A first semiconductor die is mounted within the cavity. A plurality of conductive vias can be formed through the first semiconductor die. An insulating layer is disposed between the first semiconductor die and substrate with the first conductive layer embedded within the first insulating layer. An encapsulant is deposited over the first semiconductor die and substrate. An interconnect structure is formed over the encapsulant. The interconnect structure is electrically connected to the first semiconductor die and first conductive layer. The substrate is removed to expose the first conductive layer. A second semiconductor die is mounted to the conductive layer over the first semiconductor die.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: December 2, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: HeeJo Chi, Namju Cho, HanGil Shin
  • Patent number: 8901732
    Abstract: Various packages and methods are disclosed. A package according to an embodiment includes a substrate, a chip attached to a surface of the substrate with electrical connectors, a molding compound on the surface of the substrate and around the chip, an adhesive on a surface of the chip that is distal from the surface of the substrate, and a lid on the adhesive. In an embodiment, a region between the molding compound and the lid at a corner of the lid is free from the adhesive. In another embodiment, the lid has a recess in a surface of the lid facing the surface of the molding compound.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: December 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Chih Yew, Fu-Jen Li, Wen-Yi Lin, Po-Yao Lin, Kuo-Chuan Liu
  • Patent number: 8900927
    Abstract: A multi-chip electronic package and methods of manufacture are provided. The method includes contacting pistons of a lid with respective ones of chips on a chip carrier. The method further includes separating the lid and the chip carrier and placing at least one seal shim on one of the lid and chip carrier. The at least one seal shim has a thickness that results in a gap between the pistons with the respective ones of the chips on the chip carrier. The method further includes dispensing thermal interface material within the gap and in contact with the chips. The method further includes sealing the lid to the chip carrier with the at least one seal shim between the lid and the chip carrier.
    Type: Grant
    Filed: August 16, 2010
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Martin M. Beaumier, Steven P. Ostrander, Kamal K. Sikka, Hilton T. Toy, Jeffrey A. Zitz
  • Publication number: 20140346661
    Abstract: Embodiments of the present invention provide a chip package structure and a chip packaging method, which is related to the field of electronic technologies, and can protect chips and effectively dissipate heat for chips. The chip package structure includes a substrate, chips, and a heat dissipating lid, where the chips include at least one master chip disposed on the substrate and at least one slave chip disposed on the substrate; the heat dissipating lid is bonded to the slave chip by using a heat conducting material, and the heat dissipating lid covers the at least one slave chip; and the heat dissipating lid includes a heat dissipating window at a position corresponding to the at least one master chip. The embodiments of the present invention are applicable to multi-chip packaging.
    Type: Application
    Filed: August 12, 2014
    Publication date: November 27, 2014
    Inventors: Weifeng Liu, Li Ding
  • Patent number: 8896110
    Abstract: Embodiments of the present disclosure describe techniques and configurations for paste thermal interface materials (TIMs) and their use in integrated circuit (IC) packages. In some embodiments, an IC package includes an IC component, a heat spreader, and a paste TIM disposed between the die and the heat spreader. The paste TIM may include particles of a metal material distributed through a matrix material, and may have a bond line thickness, after curing, of between approximately 20 microns and approximately 100 microns. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: November 25, 2014
    Assignee: Intel Corporation
    Inventors: Wei Hu, Zhizhong Tang, Syadwad Jain, Rajen S. Sidhu
  • Publication number: 20140339707
    Abstract: A package includes a die, which includes a semiconductor substrate, a plurality of through-vias penetrating through the semiconductor substrate, a seal ring overlapping and connected to the plurality of through-vias, and a plurality of electrical connectors underlying the semiconductor substrate and connected to the seal ring. An interposer is underlying and bonded to the die. The interposer includes a substrate, and a plurality of metal lines over the substrate. The plurality of metal lines is electrically coupled to the plurality of electrical connectors. Each of the plurality metal lines has a first portion overlapped by the first die, and a second portion misaligned with the die. A thermal conductive block encircles the die, and is mounted on the plurality of metal lines of the interposer.
    Type: Application
    Filed: August 4, 2014
    Publication date: November 20, 2014
    Inventor: Jing-Cheng Lin
  • Patent number: 8889489
    Abstract: A heat dissipation device is provided. The heat dissipation device includes an integrated heat spreader and a base plate coupled to the integrated heat spreader, wherein the base plate comprises a plurality of metal pellets to dissipate heat from the integrated heat spreader.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: November 18, 2014
    Assignee: Intel Corporation
    Inventors: Gavin D. Stanley, Michael T. Crocker
  • Patent number: 8890313
    Abstract: An electronic device includes a first chip and a second chip, where each chip has a first conduction terminal on a first surface and a second conduction terminal on a second surface. An insulating body surrounds the first and second chip, a first heat-sink coupled with the first conduction terminals of the first and second chip, and a second heat-sink coupled with the second conduction terminals of the first and second chip. A portion of the first heat-sink and/or the second heat-sink being exposed from the insulating body. The electronic device includes a first conductive lead and a second conductive lead exposed from the insulating body for through-hole mounting of the electronic device on an electronic board, the first conductive lead being coupled with the first heat-sink and the second conductive lead being coupled with the second heat-sink.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: November 18, 2014
    Assignee: STMicroelectronics S.r.l.
    Inventors: Cristiano Gianluca Stella, Gaetano Pignataro, Maurizio Maria Ferrara
  • Patent number: 8890306
    Abstract: A light-emitting diode includes a carrier with a mounting face and includes a metallic basic body and at least two light-emitting diode chips affixed to the carrier at least indirectly at the mounting face, wherein an outer face of the metallic basic body includes the mounting face, the at least two light-emitting diode chips connect in parallel with one another, the at least two light-emitting diode chips are embedded in a reflective coating, the reflective coating covering the mounting face and side faces of the light-emitting diode chips, and the light-emitting diode chips protrude with their radiation exit surfaces out of the reflective coating, and the radiation exit surfaces face away from the carrier.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: November 18, 2014
    Assignee: OSRAM Opto Semiconductor GmbH
    Inventors: Joachim Reill, Georg Bogner, Stefan Grötsch
  • Patent number: 8889458
    Abstract: A method of converting power using a power semiconductor module includes conducting power to power semiconductor devices; converting the conducted power with the power semiconductor devices; conducting heat generated by the power conversion from the power semiconductor devices first through a conductive circuit layer, then through an insulating substrate, to a baseplate; and removing the heat from the baseplate. The conductive circuit layer and the baseplate are formed of a material with a coefficient of thermal expansion less than about 8.0×10=6/° C. and a density less than about 4 g/cm3.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: November 18, 2014
    Assignee: Hamilton Sundstrand Corporation
    Inventors: Gregory I. Rozman, Jacek F. Gieras
  • Publication number: 20140327130
    Abstract: Semiconductor devices may include a first semiconductor die comprising a heat-generating region located at a periphery thereof. A second semiconductor die is attached to the first semiconductor die. At least a portion of the heat-generating region is located laterally outside a footprint of the second semiconductor die. A thermally insulating material is located on a side surface of the second semiconductor die. Methods of forming semiconductor devices may involve attaching a second semiconductor die to a first semiconductor die. The first semiconductor die includes a heat-generating region at a periphery thereof. At least a portion of the heat-generating region is located laterally outside a footprint of the second semiconductor die. A thermally insulating material is located on a side surface of the second semiconductor die.
    Type: Application
    Filed: July 18, 2014
    Publication date: November 6, 2014
    Inventors: Steven Groothuis, Jian Li, Shijian Luo
  • Publication number: 20140327128
    Abstract: A cooling system for molded modules includes a plurality of individual modules each including a semiconductor die encapsulated by a mold compound, a plurality of leads electrically connected to the semiconductor die and at least partly uncovered by the mold compound, and a cooling plate at least partly uncovered by the mold compound. A molded body surrounds a periphery of each individual module to form a multi-die module. The leads of each individual module and the cooling plates are at least partly uncovered by the molded body. A lid with a port is attached to a periphery of the molded body at a first side of the multi-die module. The lid seals the multi-die module at the first side to form a cavity between the lid and the molded body for permitting fluid exiting or entering the port to contact the cooling plates of each individual module.
    Type: Application
    Filed: May 3, 2013
    Publication date: November 6, 2014
    Applicant: Infineon Technologies AG
    Inventors: Inpil Yoo, Carlos Castro Serrato
  • Publication number: 20140327127
    Abstract: According to an exemplary embodiment, a power module is provided which comprises a semiconductor chip, a bonding substrate comprising an electrically conductive sheet and an electric insulator sheet which is directly attached to the electrically conductive sheet and which is thermally coupled to the semiconductor chip, and an array of cooling structures directly attached to the electrically conductive sheet and configured for removing heat from the semiconductor chip when interacting with cooling fluid.
    Type: Application
    Filed: May 3, 2013
    Publication date: November 6, 2014
    Inventors: Wolfram HABLE, Andreas Grassmann, Frank Winter, Ottmar Geitner, Alexander Schwarz, Alexander Herbrandt, Lothar Koenig, Andre Uhlemann
  • Patent number: 8877563
    Abstract: An electrical package with improved thermal management. The electrical package includes a die having an exposed back surface. The package further includes a plurality of fins extending outwardly from the back surface for dissipating heat from the package. The die can be arranged in a multi-die stacking configuration. In another embodiment, a method of forming a die for improved thermal management of an electrical package is provided.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: November 4, 2014
    Assignee: QUALCOMM Incorporated
    Inventor: Arvind Chandrasekaran
  • Patent number: 8877566
    Abstract: A heat spreader or lid for a microelectronic package, in which the heat spreader has an underside surface that includes at least one curvilinear contour, in which the curvilinear contour is selected from at least one positive or protruding curvilinear feature, at least one negative or recessed curvilinear feature, and a combination thereof. A microelectronic package that includes the heat spreader/lid, in which there is improved heat dissipation or reduced mechanical stress in an interface between the heat spreader/lid and a circuit chip.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: November 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Gaynes, Maurice McGlashan-Powell, Soojae Park, Edward J. Yarmchuk
  • Publication number: 20140321063
    Abstract: A semiconductor module includes a substrate having a metallized first side and a metallized second side opposing the metallized first side. A semiconductor die is attached to the metallized first side of the substrate. A plurality of cooling structures are welded to the metallized second side of the substrate. Each of the cooling structures includes a plurality of distinct weld beads disposed in a stacked arrangement extending away from the substrate. The substrate can be electrically conductive or insulating. Corresponding methods of manufacturing such semiconductor modules and substrates with such welded cooling structures are also provided.
    Type: Application
    Filed: April 30, 2013
    Publication date: October 30, 2014
    Inventors: Andre Uhlemann, Alexander Herbrandt
  • Patent number: 8871571
    Abstract: A frame includes heat slug pads coupled together in a N×M matrix such that singulation of the heat slug pads consists of one or more passes across the frame, wherein the one or more passes are parallel. A method of attaching heat slug pads to packages includes gathering a plurality of packages, preparing a heat slug frame including a N×M matrix of heat slug pads, dispensing thermally conductive material onto surfaces of the heat slug pads, attaching the plurality of packages onto the heat slug pads, and singulating the heat slug pads, wherein the singulating step consists of one or more parallel passes across the N×M matrix. A method of attaching heat slug foil to packages includes preparing a plurality of packages, laminating the heat slug foil to one side of the plurality of packages using thermally conductive material, and singulating the plurality of packages.
    Type: Grant
    Filed: February 1, 2011
    Date of Patent: October 28, 2014
    Assignee: UTAC Thai Limited
    Inventor: Saravuth Sirinorakul
  • Patent number: 8872330
    Abstract: A thin-film semiconductor component having a carrier layer and a layer stack which is arranged on the carrier layer, the layer stack containing a semiconductor material and being provided for emitting radiation, wherein a heat dissipating layer provided for cooling the semiconductor component is applied on the carrier layer. A component assembly is also disclosed.
    Type: Grant
    Filed: July 16, 2007
    Date of Patent: October 28, 2014
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Siegfried Herrmann, Berthold Hahn
  • Publication number: 20140312360
    Abstract: A semiconductor device includes an electrically conducting carrier having a mounting surface. The semiconductor device further includes a metal block having a first surface facing the electrically conducting carrier and a second surface facing away from the electrically conducting carrier. A semiconductor power chip is disposed over the second surface of the metal block.
    Type: Application
    Filed: April 17, 2013
    Publication date: October 23, 2014
    Inventors: Ralf Otremba, Josef Hoeglauer, Juergen Schredl, Xaver Schloegel, Klaus Schiess
  • Publication number: 20140312484
    Abstract: An embodiment of an electronic assembly for mounting on an electronic board includes a plurality of electric contact regions exposed on a mounting surface of the electronic board. The electronic assembly includes a chip of semiconductor material in which at least one electronic component is integrated, at least one support element including a first main surface and a second main surface opposite to the first main surface, the chip being enclosed by the at least one support element, a heat dissipation plate thermally coupled to said chip to dissipate the heat produced by it, exposed on the first main surface of the support element, a plurality of contact elements, each electrically coupled to a respective electric terminal of the electronic component integrated in the chip, exposed on the same first main surface of which is exposed to the dissipation plate.
    Type: Application
    Filed: April 22, 2014
    Publication date: October 23, 2014
    Applicant: STMicroelectronics S.r.l.
    Inventors: Pierangelo MAGNI, Giuseppe GATTAVARI, Mark Andrew SHAW
  • Publication number: 20140312485
    Abstract: A semiconductor module system has a semiconductor module and a protective cover. The semiconductor module has a bottom side with a heat dissipation surface and a top side opposite the bottom side, the top side being separated from the bottom side in a vertical direction. The protective cover can be mounted irreleasably on the semiconductor module in such a way that, in a mounted state, the top side is exposed and the protective cover covers the heat dissipation surface. By virtue of the protective cover, a thermal interface material applied onto the heat dissipation surface can be protected.
    Type: Application
    Filed: April 15, 2014
    Publication date: October 23, 2014
    Applicant: Infineon Technologies AG
    Inventor: Michael Daginnus
  • Patent number: 8865523
    Abstract: A method of making a semiconductor packaged device comprises mounting onto a lead frame a bottom of a molded semiconductor chip having a first plastic package body covering a top face of a semiconductor chip, encapsulating the lead frame and the semiconductor chip with a second plastic package body with top surfaces of conductive contact bodies electrically connected to electrodes on the top surface of the semiconductor chip exposed and plating conductive pads on a top surface of the assembly structure to provide external electrical connections to the electrodes through the conductive contact bodies.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 21, 2014
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Yueh-Se Ho, Yan Xun Xue, Jun Lu, Lei Shi, Liang Zhao, Ping Huang
  • Publication number: 20140306336
    Abstract: A fluid cooled semiconductor die package includes a package support substrate with a die mounting surface and an opposite package mounting surface. The package support substrate has external connector solder deposits on respective external connector pads of the package mounting surface, and a package fluid inlet duct and a package fluid outlet duct each providing fluid communication between the die mounting surface and package mounting surface. A semiconductor die is mounted on the die mounting surface. The die has external terminals electrically connected to the external connector pads. An inlet solder deposit is soldered to an inlet pad of the package mounting surface. The inlet pad surrounds an entrance of the fluid inlet duct. An outlet solder deposit is soldered to an outlet pad of the package mounting surface. The outlet pad surrounds an exit of the package fluid inlet duct.
    Type: Application
    Filed: April 15, 2013
    Publication date: October 16, 2014
    Inventors: Chee Seng Foong, Tim V. Pham
  • Patent number: 8860079
    Abstract: Semiconductor packages and methods of forming a semiconductor package are disclosed. The method includes providing at least one die having first and second surfaces. The second surface of the die includes a plurality of conductive pads. A permanent carrier is provided and the at least one die is attached to the permanent carrier. The first surface of the at least one die is facing the permanent carrier. A cap having first and second surfaces is formed to encapsulate the at least one die. The first surface of the cap contacts the permanent carrier and the second surface of the cap is disposed at a different plane than the second surface of the die.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: October 14, 2014
    Assignee: United Test and Assembly Center Ltd.
    Inventors: Catherine Bee Liang Ng, Kriangsak Sae Le, Chuen Khiang Wang, Nathapong Suthiwongsunthorn
  • Patent number: 8859333
    Abstract: An IC package that is suitable for surface mounting arrangements includes a heat spreader device that is coupled to a bottom portion of the package below the IC die. Coupling the heat spreader device to the bottom portion of the package reduces or eliminates the possibility that placement of the heat spreader device will result in the molding compound bleeding on top of the heat spreader device, and delamination at the footings of the heat spreader device that can cause the package to delaminate, or “popcorn”.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: October 14, 2014
    Assignee: LSI Corporation
    Inventors: Kok Hua Simon Chua, Budi Njoman
  • Patent number: 8860211
    Abstract: A semiconductor device includes an insulation layer, a first semiconductor element and a second semiconductor element which are disposed within the insulation layer, a frame which has higher thermal conductivity than the insulation layer and surrounds the first semiconductor element and the second semiconductor element via the insulation layer, and a wiring layer which is disposed over the insulation layer and includes an electrode which electrically connects the first semiconductor element and the second semiconductor element.
    Type: Grant
    Filed: October 10, 2012
    Date of Patent: October 14, 2014
    Assignee: Fujitsu Limited
    Inventor: Junichi Kon
  • Patent number: 8860071
    Abstract: In one embodiment, a semiconductor module includes a leadframe having a first side and an opposite second side. A semiconductor chip is disposed over the first side of the leadframe. A switching element is disposed under the second side of the leadframe. In another embodiment, a method of forming a semiconductor module includes providing a semiconductor device having a leadframe. A semiconductor chip is disposed over a first side of the leadframe. A switching element is attached at an opposite second side of the leadframe.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: October 14, 2014
    Assignee: Infineon Technologies AG
    Inventor: Ralf Otremba
  • Patent number: 8859337
    Abstract: Embodiments described herein provide a chip, comprising a first device on a substrate and a second device on the substrate. The chip further comprises a heat distribution structure in thermal proximity to the first device and the second device, wherein the heat distribution structure is thermally isolated and reduces a thermal gradient between the first device and the second device.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: October 14, 2014
    Assignee: Soitec
    Inventors: Stephen J Gaul, Steven Howard Voldman, Jean-Michel Tschann
  • Patent number: 8860213
    Abstract: A power converter including: a plurality of semiconductor devices forming a power conversion circuit; a base section to which the plurality of semiconductor devices are attached; and radiating fins dissipating heat generated from the semiconductor devices into outside air, in the power converter in which the direction of the flow of a refrigerant flowing into the radiating fins changes depending on the operation status of the power conversion circuit, the shape of each radiating fin changes in such a way that the cross-sectional area of a channel of the refrigerant on the outflow side becomes smaller than the cross-sectional area of the channel of the refrigerant on the inflow side in the radiating fins depending on the direction of the flow of the refrigerant.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: October 14, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Tsutomu Kominami, Mami Kunihiro, Katsumi Ishikawa, Yosuke Yasuda, Sunao Funakoshi