Abstract: A semiconductor device is manufactured in such a way that a semiconductor chip connected with leads whose internal ends are interconnected with bonding wires are completely sealed and enclosed in a resin corresponding to a package while external ends of leads are exposed from the surface of the package. In manufacture, a chip fixing member is used to fix the semiconductor chip in a prescribed position, while wire fixing members are used to fix the bonding wires in prescribed positions. Both the fixing members are retracted into the split mold so as to avoid formation of unfilled portions or voids in the resin in the cavity. In inspection, an electrical conduction is detected between the bonding wire(s) and an electrode layer formed inside of the cavity, so that a semiconductor device produced in the cavity is automatically removed from the manufacturing line.

Abstract: A package may include a semiconductor chip mounted on a film substrate. A method of manufacturing the same may involve providing a semiconductor chip. The semiconductor chip may include recesses and bumps. A film substrate including a through hole may be provided. The semiconductor chip may be inserted into the through hole of the film substrate. Circuit wires may be formed on the film substrate to contact the bumps of the semiconductor chip.

Abstract: Substrate for electrical devices and methods of manufacturing such substrate are disclosed. An embodiment for the substrate comprised of an insulator and a plurality of conductive elements, wherein the insulator having a recess. The conductive elements embedded in the insulator. The conductive elements extend from the insulator surface to the recess. There are two portions of the conductive elements for electrical connection respectively, wherein a portion of conductive element may protrude the insulator surface for electrical connection. In this manner, solder balls are not needed. Moreover, the substrate of the present invention may also comprise an adhesive mean, which is between the conductive elements and the insulator. In addition, the substrate may further comprise a submember such as a chip, heat spreader etc., and the present invention may be capable of affording a thinner electrical device thickness, enhanced reliability, and a decreased cost in production.

Abstract: An automated process for performing MEMS packaging including automatically attaching a die to a chip carrier, resulting in a chip carrier assembly, automatically moving the chip carrier assembly into a vacuum chamber, wherein the vacuum chamber includes one or more lids therein, automatically securing a lid to the chip carrier assembly within the vacuum chamber, thereby forming a packaged die, and automatically removing the packaged die from the vacuum chamber. Unique vacuum chambers suitable for MEMS packaging are also disclosed.

Abstract: An electrically and thermally enhanced die-up ball grid array (BGA) package is described. An integrated circuit (IC) package includes a first substrate, a second substrate, and a stiffener. A surface of the first substrate is attached to a first surface of the stiffener. A surface of the second substrate is attached to a second surface of the stiffener. An IC die may be attached to a second surface of the second substrate or to the second surface of the stiffener. Additional electronic devices may be attached to the second surface of the second substrate.

Abstract: A method, apparatus and system with a semiconductor package including a thermal interface material dam enclosing a volume of thermal interface material.

Abstract: Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided.

Abstract: A semiconductor multi-package module includes a processor and a plurality of memory packages mounted on a surface of the multipackage module substrate. In some embodiments the memory packages include stacked die packages, and in some embodiments the memory packages include stacked memory packages. In some embodiments the processor is situated at or near the center of the multipackage module substrate and the plurality of memory packages or of stacked memory package assemblies are situated on the multipackage module substrate adjacent the processor.

Abstract: A semiconductor device includes a substrate, a semiconductor chip flip-chip mounted on the substrate, a sealing resin layer sealing the surroundings of the semiconductor chip, and a heat sink bonded to the sealing resin layer through a TIM layer. In addition, a cooling medium is encapsulated in an enclosed space formed on the rear surface of the semiconductor chip.

Abstract: One embodiment of a micro-electronic device includes a substrate including micro-electronic components thereon, and a cover including a ring of sealing material secured to the substrate and a raised ring of material positioned opposite the cover from the ring of sealing material.

Abstract: A FET includes elongated, mutually parallel source regions separated by gate and drain regions. Conductive bridges extend over the gate and drain regions and not in electrical contact therewith to electrically and thermally interconnect the sources. A layer of dielectric is applied over surfaces, and an aperture is defined over the bridges. A thick layer of metal is applied over and in thermal and electrical contact with the bridges. Electrical and thermal connections can be made to the thick metal.

Abstract: An integrated circuit package includes a die mounted on a substrate, an integrated heat spreader set above the die, and an array of carbon nanotubes mounted between the die and the integrated heat spreader. The integrated heat spreader is fixed on the substrate, and includes an inner face. The array of carbon nanotubes is formed on the inner face of the integrated heat spreader. Top and bottom ends of the carbon nanotubes perpendicularly contact the integrated heat spreader and the die respectively. Each carbon nanotube can be capsulated in a nanometer-scale metal having a high heat conduction coefficient.

Abstract: Provided is a semiconductor device having a cooling path on its bottom surface. The stack-type semiconductor device having a cooling path comprises a stack-type semiconductor chip comprising a first semiconductor chip and a second semiconductor chip. The first semiconductor chip comprises a first surface in which a circuit unit is formed and a second surface in which a first cooling path is formed, and the second semiconductor chip comprises a first surface in which a circuit unit is formed and a second surface in which a second cooling path is formed. The second surface of the first semiconductor chip and the second surface of the second semiconductor chip are bonded to each other, and a third cooling path is formed in the middle of the stack-type semiconductor chip using the first and second cooling paths. Warpage of the stack-type semiconductor device is suppressed and heat is easily dissipated.

Abstract: Wire bonding methods and apparatuses are described herein. In one aspect of the invention, an exemplary apparatus includes a plurality of electrically conductive contacts disposed on a surface of the IC device, the plurality of electrically conductive contacts being disposed in at least two rows, a plurality of first return paths formed through some of the plurality of electrically conductive contacts, a plurality of signal paths formed through some of the plurality of electrically conductive contacts, and wherein at least one of the plurality of first return paths are placed between every predetermined number of the plurality of the signal-paths. Other methods and apparatuses are also described.

Abstract: A component built-in module includes an insulating layer, wirings integrated with both surfaces of the insulating layer, a via connecting the wirings, and one or more components selected from an electronic component and a semiconductor, which is embedded inside of the insulating layer. In this module, at least one of the wirings is formed on a surface of a wiring board, and the components embedded inside of the insulating layer are mounted on and integrated with the wiring board before embedding. This configuration allows the components such as a semiconductor to undergo a mounting inspection and a property inspection before embedding. As a result, the yields of the module can be improved. In addition, since the components are integrated with the wiring board and embedded, the strength thereof can be enhanced.

Abstract: A heat sink and method for fabricating the same are disclosed. The heat sink includes a lower substrate having a concave portion, a supporting column formed on the concave portion of the lower substrate, and an upper substrate opposed to the lower substrate and tightly fixed to the lower substrate so as to form a cooled liquid receiving space therebetween, wherein the upper substrate has a concave portion formed at a position corresponding to the supporting column of the lower substrate so as to engage with the supporting column.

Abstract: A lead frame of the present invention includes a plurality of tie bars including tie bars each having deformable portions that protect opposite outside frames from deformation. The outside frames each are formed with positioning holes. Element loading portions to be loaded with semiconductor elements are connected to the outside frames by such tie bars. The lead frame is therefore free from deformation during lead forming while promoting the miniaturization of the semiconductor devices.

Abstract: Apparatuses and methods for forming displays are claimed. One embodiment of the invention relates to depositing a plurality of blocks onto a substrate and is coupled to a flexible layer having interconnect deposited thereon. Another embodiment of the invention relates to forming a display along a length of a flexible layer wherein a slurry containing a plurality of elements with circuit elements thereon washes over the flexible layer and slides into recessed regions or holes found in the flexible layer. Interconnect is then deposited thereon. In another embodiment, interconnect is placed on the flexible layer followed by a slurry containing a plurality of elements.

Abstract: An integrated heat spreader (IHS) having a groove and a cavity formed therein is disclosed. In one embodiment, the groove has an insulating layer formed therein, and a power conduit is mounted in the groove, the power conduit is electrically isolated from the IHS by the insulating layer, and the power conduit conducts a voltage relative to the IHS to deliver power to the cavity. In another embodiment, the IHS is soldered to a semiconductor die and a package substrate. In a further embodiment, the power conduit comprises an edge connector.

Abstract: A rerouting element for a semiconductor device includes a substantially planar member that carries at least one contact location, at least one conductive, at least one rerouted bond pad. The contact location is positioned adjacent to a first periphered edge of the substantially planar member and at a location that corresponds to the location of a bond pad of a semiconductor device with which the rerouting element is to be used. The at least one conductive element, which communicates with the at least one contact location, reroutes the bond pad location of the semiconductor device to a corresponding rerouted bond pad location adjacent to a second one peripheral edge of the rerouted substantially planar member which is opposite the first periphered edge. In addition, assemblies including rerouting elements and methods for designing and using rerouting elements are disclosed.

Abstract: A device (10) is provided for matching the CTE between substrates (12, 14), e.g., a semiconductor substrate and packaging material. The first substrate (12) has a first coefficient of thermal expansion and the second substrate (14) has a second coefficient of thermal expansion. At least two layers (16) of liquid crystal polymer are formed between the first substrate (12) and the second substrate (14), each layer having a unique coefficient of thermal expansion progressively higher in magnitude from the first substrate (12) to the second substrate (14).

Abstract: A method of fabricating a printed circuit board (PCB) including embedded chips, composed of forming a hollow portion for chip insertion through a substrate, inserting the chip into the hollow portion, fixing the chip to the substrate by use of a plating process to form a central layer having an embedded chip, and then laminating a non-cured resin layer and a circuit layer having a circuit pattern on the central layer. Also, a PCB including embedded chips fabricated using the above method is provided.

Abstract: Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies are provided. In an embodiment of the methods, a second die is mounted on a first die which is at least partially received within a recess of the second die and an overall height of the dies within the device is less than a combined height of the dies.

Abstract: Apparatus and methods for forming semiconductor assemblies. An interposer includes a perimeter wall surrounding at least a portion of an upper surface thereof to form a recess. An array of electrical connection pads is located within the recess. A semiconductor die can be flip chip attached to the interposer by at least partial insertion of the semiconductor die within the recess with discrete conductive elements between bond pads of the semiconductor die and electrical connection pads of the interposer. The electrical connection pads communicate with a number of other electrical contact pads accessible elsewhere on the interposer, preferably on a lower surface thereof. A low viscosity underfill encapsulant is disposed between the semiconductor die and the interposer and around the discrete conductive elements by permitting the same to flow into the space between the die and the perimeter wall.

Abstract: A substantially planar substrate having opposed major surfaces is provided. The substrate includes a through hole that extends between the major surfaces. The through hole is filled with a conductive interconnecting element. A conductive mounting pad and a conductive connecting pad are formed on different ones of the major surfaces in electrical contact with the conductive interconnecting element. The packaging device formed by the method has a volume that is only a few times that of the semiconductor die and can be fabricated from materials that can withstand high-temperature die attach processes. The packaging device can be configured as the only packaging device used in the semiconductor device or as a submount for a semiconductor die that requires a high-temperature die attach process.

Abstract: Methods and apparatus are provided for designing the electrical interconnects of a substrate. Modules are used to design sections of the electrical interconnects. Multiple modules may be interconnected to generate the electrical interconnects. The placement of modules and/or the interconnection of the modules may depend on a netlist and/or a separate report. Modules may even be defined by various constraints. Accordingly, a module based design may be implemented for efficiently and effectively producing a standardized electrical interconnect design.

Abstract: A method and apparatus for encapsulating microelectronic devices. In one embodiment, the method includes removing a portion of encapsulating material that at least partially surrounds a microelectronic substrate by directing a source of laser radiation toward the encapsulating material. The method can further include exposing a surface of the microelectronic substrate, for example, to enhance a rate at which heat is transferred away from the microelectronic substrate. Alternatively, the encapsulating material can be removed to form heat transfer structures, such as pins or ribs, also to enhance a rate at which heat is transferred away from the microelectronic substrate. In still another embodiment, a portion of the encapsulating material or a support member to which the substrate is attached can be removed to define interlocking features that allow one microelectronic substrate package to be stacked on another and to resist relative movement between the two packages.

Abstract: This invention discloses a method for electroplating nickel/gold on electrically connecting pads on a substrate for chip package and structure thereof. The method comprises: forming a conductive film on a substrate circuit-patterned and defined with a circuit layer; forming on the substrate a resist with an opening for exposing a portion of the conductive film in an electrically connecting pad area intended for the circuit layer; removing a portion of the conductive film not covered with the resist; forming another resist on the substrate to cover a portion of the conductive film residually exposing from the resist; electroplating nickel/gold on at least one electrically connecting pad on the substrate such that the electrically connecting pad is electroplated with a nickel/gold layer; removing the resists and the conductive film thereunder; and forming a solder mask on the substrate, wherein the electrically connecting pad electroplated with the nickel/gold layer is exposed from the solder mask.

Abstract: A method for manufacturing a radiofrequency identification device which includes a manufacturing process for an antenna which includes screen-printing turns of an electrically conductive polymer ink onto a transfer paper sheet, and then subjecting the support to heat treatment to bake and polymerize the conductive ink, connection of a chip 14, provided with contacts, to the antenna 12, lamination which includes making the transfer paper sheet integral with a layer of plastic material 16 which constitutes the support for the antenna, by hot press molding, in such a way that the screen-printed antenna and the chip are both embedded within the layer of plastic material, and removal of the transfer paper sheet.

Abstract: This is an interconnection between electronic devices and other assemblies (e.g. printed circuits). The electronic devices are mounted on high temperature insulating bases, such as ceramic substrates. The insulating base has a conductive pattern to connect the electronic device to another assembly. The conductive pattern terminates in metal bumps capable of being connected to another assembly (e.g. a printed circuit) by a conductive adhesive or metallurgically by soldering, thermocompression, thermosonic or ultrasonic bonding. The bumps are formed by applying a metal with a melting point over 350° C. to contact pads of the conductive pattern of the insulating base, and raising the temperature of the base above the melting point of the metal causing the molten metal to draw back on to the contact pads forming a convex bump.

Abstract: Methods for creating redistribution layers for only selected dice, such as known good dice, to form relatively thin semiconductor component assemblies and packages, and the assemblies and packages created by the methods, are disclosed. A sacrificial layer is deposited on a support substrate. An etch stop layer having a lower etch is deposited on the sacrificial layer. Redistribution lines in a dielectric material are formed on the support substrate on the etch stop layer. Semiconductor dice, either singulated or at the wafer level, are connected to the redistribution lines. The assembly may be scribed to allow the sacrificial layer to be etched to enable removal of the semiconductor dice and associated redistribution layer from the support substrate. The etch stop layer is removed to allow access to the redistribution lines for conductive bumping.

Abstract: A ball grid array (BGA) package that includes a central cavity for receiving a semiconductor die therein is disclosed. The die rests on a base laminate, the die side of which includes traces therein extending into the cavity, which is framed at least by an anisotropically conductive adhesive layer. Bond pads on the die are electrically connected, as by wire bonds or, in the case of a flip-chip configured die, solder balls or conductive adhesive elements, to the traces. The traces are, in turn, electrically connected through conductive vias to conductive element sites on the opposite side of the base laminate through a dielectric layer, the conductive element sites carrying solder balls or other discrete conductive bonding elements for connection to higher-level packaging.

Abstract: The present invention provides a method of mounting a light emitting element, in which a light emission point can be positioned at high accuracy with respect to the mounting member. A semiconductor laser element is placed on a matching stage. Next, a position and an azimuth of a laser stripe of the semiconductor laser element is observed, and linear displacement in X and Y directions of the semiconductor laser element from a reference line and a reference point on the matching stage, and angular displacement in an azimuth (?) within an X-Y plane are measured. In accordance with a measured result, a control signal is sent to a driving mechanism of the feeding collet to drive the feeding collet, and the position of the semiconductor laser element is adjusted on the matching stage. After the adjustment, the semiconductor laser element is fed to and placed on a mounting surface of a heat sink H.

Abstract: A method for packaging a radio frequency integrated circuit (RFIC) in multiple packages begins by determining a 1st position of the RFIC die in a 1st package wherein the positioning is such to minimize adverse affects of parasitic components of coupling between the radio frequency input/output section and an antenna. Once the position within the 1st package has been determined, the corresponding parasitics are measured to determine their values. The processing then continues by determining a 2nd position of the RFIC die in a 2nd package based on the values of the parasitic components. Accordingly, the 2nd position places the die within the 2nd package such that the parasitic components of coupling between the RF I/O section to the antenna within the 2nd package substantially matches the parasitic components of coupling the RFIO section to the antenna in the 1st package. Accordingly, different packages may be used with the same RFIC die, while maintaining the desired noise reduction.

Abstract: A removable Flash integrated memory module card has a plastic shell and an integral Flash memory module. On the backside of the card, there are exposed contact pads. When the card is inserted into a card-hosting device, the card can communicate with the device through the exposed pads. The manufacturing method includes manufacturing of the memory module and utilizing plastic molding techniques for making the card outer body. The method involves preparing the substrate, mounting the components, testing the module, preparing the molding device, and molding the card body.

Abstract: The invention relates to a method for producing information carriers (11), such as labels, tickets or the like, in particular contactless information carriers (11), which have integrated circuits (ICs, 30) and antennas (12, 13) connected to them, wherein antennas (12, 13) are formed at intervals one after the other on surface regions (27, 28) of a web (14), and moreover, one IC (30) provided per antenna (12, 13) is connected electrically conductively by its housing or its contacts (31, 32) to associated contact faces (33, 34) of the antenna (12) (FIG. 1).

Abstract: A bumpless assembly package mainly comprises a substrate, and a chip. The substrate has an upper surface and an opposite lower surface, a plurality of first contacts and a plurality of second contacts formed on the upper surface of the substrate, wherein one of the first contacts is electrically connected to one of the second contacts. The chip has an active surface and a boding pad formed on the active surface and is disposed in the opening, Moreover, an electrically conductive layer is disposed above the upper surface of the substrate and the active surface of the chip, and extended from the upper surface of the substrate to the active surface of the chip so as to electrically connect the chip and the substrate. In addition, a protective layer is provided to dispose above the electrically conductive layer and expose the second contacts so that the second contacts can electrically connect to external electronic devices.

Abstract: A flip chip packaging technique and associated apparatus that consolidates many or all of the steps in a conventional flip chip packaging process results in substantially decreased packaging time, e.g., only one to two hours, complexity, e.g., requiring fewer pieces and much simpler equipment, and cost, arising from reduced equipment operation and maintenance time and decreased labor. An assembly fixture useful for implementing the consolidated assembly technique engages and holds in place a semiconductor flip chip die with a plurality semiconductor package components in a desired package configuration so that they can be assembled into a semiconductor package with a single application of heat and pressure.

Abstract: Salient electrodes on a semiconductor chip and leads on a film substrate are to be connected together with a high accuracy. A change in lead pitch which occurs at the time of connecting salient electrodes on a semiconductor chip and inner leads on a film substrate with each other is taken into account and a correction is made beforehand to the pitch of the inner leads. Likewise, a change in lead pitch which occurs at the time of connecting electrodes on a liquid crystal substrate and outer leads on the film substrate with each other is taken into account and a correction is made beforehand to the pitch of the outer leads.

Abstract: A durable radio frequency identification tag. A preferred embodiment of the invention provides a durable radio frequency identification tag comprising: a flexible substrate including a first major surface and a second major surface opposite the first major surface; a radio frequency identification antenna attached to the first major surface of the substrate; an integrated circuit attached to the antenna; and a thermoplastic guard attached to the flexible substrate adjacent the integrated circuit. The present invention also provides a method of manufacturing a durable radio frequency identification tag.

Abstract: A substrate structure comprising a substrate; a solder mask is formed over the substrate; and a metal trace structure formed within the solder mask. The metal trace structure including a channel therein for the receipt of underfill. The metal trace structure further including a central portion with arms radiating outwardly therefrom, dividing the solder mask into separate areas. A method of underfilling a chip wherein a chip having a pattern of solder bumps formed on the underside of the chip is placed underside first onto the metal trace structure of the present invention. The solder bump pattern including openings over the metal trace structure. Underfill is introduced into the metal trace structure so that the underfill flows from the metal trace structure and between the solder bumps to underfill the chip.

Abstract: A carrier for use in a chip-scale package, including a polymeric film with apertures defined therethrough. The apertures, which are alignable with corresponding bond pads of a semiconductor device, each include a quantity of conductive material extending substantially through the length thereof. The carrier may also include laterally extending conductive traces in contact with or otherwise in electrical communication with the conductive material in the apertures of the carrier. Contacts may be disposed on a backside surface of the carrier. The contacts may communicate with the conductive material disposed in the apertures of the carrier. A conductive bump, such as a solder bump, may be disposed adjacent each or any of the contacts. A chip-scale package including the carrier of the present invention is also within the scope of the present invention.

Abstract: A low-profile package for housing an optoelectric device is disclosed. The low-profile package includes an insulating base having an upper surface. The optoelectric device is mounted to the upper surface of the insulating base. The low-profile package also includes a metal sealing member having a top wall and a bottom wall. The bottom wall of the metal sealing member is attached to the upper surface of the insulating base. The low-profile package further includes a substantially flat metal cover attached to the top wall of the metal sealing member to thereby hermetically seal the metal cover to the insulating base.

Abstract: A laminate is formed from a carrier layer and an electrically conductive layer. In one section, the conductive layer is formed into an antenna structure. The laminate is formed by placing a mask onto a packaging film and vapor-depositing aluminum onto the packaging film and the mask. After removal of the mask, only a desired antenna structure remains on a section of the packaging film. Then a microchip, is adhesively bonded to the packaging film and conductively connected to an end of the antenna structure, so that data can be written in or read out without contact in a wireless transponder system.

Abstract: A microelectronic package is fabricated by a process which includes folding a substrate. A substrate is folded by engaging a folding portion of the substrate with a die so that the folding portion pivots with respect to a first portion of the substrate.

Abstract: An encapsulation mold for forming an encapsulation layer over a semiconductor assembly is disclosed. A semiconductor assembly with multiple semiconductor dies secured to a single semiconductor support structure is inserted into an encapsulation mold. The mold contains a first section and a second section, which form a cavity around the assembly. The mold contains an aperture for transferring encapsulating material into the mold cavity. One of the mold sections has a design feature, such as a raised rib or groove interconnecting at approximately the separation or saw-cut regions of the individual dies of the assembly. Encapsulation material is inserted into the mold cavity until the cavity is filled. The mold section design feature shapes the top surface of the encapsulation layer. The mold is removed leaving the exterior surface of the encapsulation layer patterned with the design feature.

Abstract: A method of packaging at least a portion of a semiconductor die or dice is disclosed. Uncured material may be disposed proximate at least the periphery of at least one semiconductor die and at least partially cured substantially as a whole. Methods of forming conductive elements such as traces, vias, and bond pads are also disclosed. More specifically, forming at least one organometallic layer to a substrate surface and selectively heating at least a portion thereof is disclosed. Also, forming a layer of conductive photopolymer over at least a portion of a surface of a substrate and removing at least a portion thereof is disclosed. A microlens having a plurality of mutually adhered layers of cured, optically transmissive material, methods of forming same, and systems so equipped are disclosed.

Abstract: In a method for producing a protective cover for a device formed in a substrate, at first a sacrificial structure is produced on the substrate, wherein the sacrificial structure comprises a first portion covering a first area of the substrate including the device and a second portion extending from the first portion into a second area of the substrate including no device. Then a first cover layer is deposited that encloses the sacrificial structure such that the second portion of the sacrificial structure is at least partially exposed. Then the sacrificial structure is removed, and the structure formed by the removal of the sacrificial structure is closed.

Abstract: A method of manufacturing a flexible wiring substrate of the present invention includes the steps of preparing a tape-like substrate composed of a resin layer and a reinforcing metal layer provided on its lower surface, then forming a via hole whose depth reaches the reinforcing metal layer by processing the resin layer of the tape-like substrate by the laser, and then forming a wiring pattern which is connected to the reinforcing metal layer through the via hole on the resin layer by the semi-additive process, wherein the reinforcing metal layer is patterned to constitute a connection pad connected to the wiring pattern or is removed.

Abstract: An adhesive layer containing a photo-curing adhesive and a thermosetting adhesive is formed on a semiconductor wafer in which a plurality of semiconductor elements are formed. The adhesive layer and the semiconductor wafer are adhered together by selectively exposing the adhesive layer to light and curing the photo-curing adhesive contained in the adhesive layer on the peripheral portion of each semiconductor element. By developing the photo-curing adhesive, the adhesive layer in an area that has not been exposed is removed. Whether the pattern of the adhesive layer is satisfactory or not is determined for each semiconductor element. A lid part is placed on the adhesive layer of the semiconductor element determined to be satisfactory, and the adhesive layer and the lid part are adhered together by heating the adhesive layer and causing the thermosetting adhesive contained in the adhesive layer to exhibit adhesive properties.