Abstract: In a semiconductor flip-chip package having a semiconductor die as part of a substrate assembly, a lid (or lid assembly) and substrate are supported to prevent tilting and teetering of the lid. The lid and substrate do not adhere, so as to reduce cracking of solder joints due to thermal cycling induced by repeated system power on-off. An adhesion prohibitor may be applied so that a support does not adhere to both lid and substrate; the support may be prevented from adhering to both lid and substrate by a separate curing step. The arrangements and fabrication methods may be applied to many package types, including ball grid array (BGA) and land grid array (LGA) packages.

Abstract: A semiconductor device includes a semiconductor chip, an insulating base film and first projecting electrodes. The first projecting electrodes are formed in a single row on one face of the semiconductor chip along the edge of the semiconductor chip. This face of the semiconductor chip faces a semiconductor chip mounting face of the base film. The semiconductor device also includes second projecting electrodes formed in a single row outside the row of first projecting electrodes. The height of the second projecting electrodes is smaller than the first projecting electrodes. The semiconductor device also includes first inner leads formed on the semiconductor chip mounting face of the base film. The first inner lead extend to the first projecting electrodes. The semiconductor device also includes an insulating film formed between the first inner leads and the semiconductor chip. The semiconductor device also includes second inner leads formed on the insulating film.

Abstract: A die package and a method and apparatus for integrating an electro-osmotic pump and a microchannel cooling assembly into a die package.

Abstract: This application relates to a method of manufacturing an electronic device comprising placing a first chip on a carrier; applying an insulating layer over the first chip and the carrier; applying a metal ions containing solution to the insulating layer for producing a first metal layer of a first thickness; and producing a second metal layer of a second thickness on the insulating layer wherein at least one of the first metal layer and the second metal layer comprises at least a portion that is laterally spaced apart from the respective other metal layer.

Abstract: A method of manufacture of an electronic substrate, having a process of embedding electronic components in a substrate, and a process of ejecting liquid droplets containing a conductive material, to form a wiring pattern connected to the external connection electrodes of the electronic components embedded in the substrate.

Abstract: The insulative wiring board of the present invention, with its both surfaces being covered with solder resist, includes at least one via hole in a semiconductor chip-mounting area penetrating the insulative wiring board, wherein conductor layers are electrically connected to each other via said at least one via hole. Further, the mounting area is covered with the solder resist, excluding said at least one via hole that penetrates the insulative wiring board. Therefore, it is possible to achieve an insulative wiring board that prevents defects caused by expansion occurred due to heating of moisture absorbed by the board, as well as reducing an area where a wiring cannot be provided.

Abstract: A method for manufacturing a circuit board (7); in which, an electronic component is injected into a resin substrate at a low temperature, and then the resin substrate is improved in its heat withstanding property. The manufacturing method comprises the steps of softening by heat a resin substrate which contains a thermoplastic component and a chemical cross-link component and then injecting an electronic component (1) into the resin substrate; curing the resin substrate by bridging the chemical cross-link component of the resin substrate, making the resin substrate into a heat-withstanding substrate (70); and forming an electric wiring pattern (6) on the heat-withstanding substrate (70) for connection with a protruding electrode (2) of the electronic component (1). The circuit board (7) maintains the high dimensional accuracy throughout the manufacturing process. Thus, the present invention offers a superior circuit board, which is thin and compact in size and has a small thermal deformation rate.

Abstract: The surface mount package is assembled from a ceramic base which is imprinted on its upper and lower surfaces with conductive patterns for attachment of and connection to an electronic or electromechanical device, a molded dielectric layer for forming a cavity and a seal ring. The molded dielectric is formed by aligning a dielectric preform with the base, positioning the seal ring on top of the preform, then applying a mold over the layers to shape the dielectric during a firing process that fuses the base, preform and seal ring to create a hermetic seal. The preform is of sufficient thickness that the electronic device will be fully contained within the cavity when placed into the completed package.

Abstract: Bending generated in a side of a device mounting surface of an organic resin substrate after an assembly process for a semiconductor device is inhibited, thereby providing an improved production yield. A semiconductor device 100 is formed by solder-joining a semiconductor chip 105 onto a device mounting surface 111 of an interposer that is composed of an organic resin substrate 101. The interposer is an interposer, which is composed of an organic resin substrate 101, and on one surface of which a semiconductor chip 105 is to be mounted, and has a convex curvature in a side of a back surface 113 opposite to the device mounting surface 111, in a condition before an assembling process for the semiconductor device 100.

Abstract: A semiconductor apparatus comprises a support substrate having through holes filles with conductor adapted to a first pitch; a capacitor formed on or above said support substrate; a wiring layer formed on or above said support substrate, leading some of said through holes filles with conductor upwards through said capacitor, having branches, and having wires of a second pitch different from said first pitch; and plural semiconductor elements disposed on or above said wiring layer, having terminals adapted to the second pitch, and connected with said wiring layer via said terminals. A semiconductor apparatus, in which semiconductor elements having a narrow terminal pitch, a support having through wires at a wider pitch, and a capacitor are suitably electrically connected to realize the decoupling function with reduced inductance and large capacitance.

Abstract: Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. An embodiment of one such method includes forming a plurality of through holes in a substrate with the through holes arranged in arrays, and attaching a plurality of singulated microelectronic dies to the substrate with an active side of the individual dies facing toward the substrate and with a plurality of terminals on the active side of the individual dies aligned with corresponding holes in the substrate. The singulated dies are attached to the substrate after forming the holes in the substrate.

Abstract: The present invention relates to an isolator and a method of manufacturing the same. An isolator according to the present invention includes a silicon wafer, protective devices formed in predetermined regions of the silicon wafer, and a transformer formed in a predetermined region on the silicon wafer, the transformer having at least two coil patterns spaced apart from each other. According to the present invention, an isolator can be protected from impulses generated by ESD and surge, so that its reliability can be improved, and its size can be considerably decreased. Further, the number of wire bonding times is decreased, so that performance of a chip can be enhanced, and packaging efficiency can be improved, thereby increasing productivity.

Abstract: The present invention provides LTCC (low temperature co-fired ceramic) tape compositions and demonstrates the use of said LTCC tape(s) in the formation of Light-Emitting Diode (LED) chip carriers and modules for various lighting applications. The present invention also provides for the use of (LTCC) tape and LED modules in the formation of lighting devices including, but not limited to, LED devices, High Brightness (HB) LED backlights, display-related light sources, automotive lighting, decorative lighting, signage and advertisement lighting, and information display lighting.

Abstract: A method of fabricating a substrate with an embedded component therein including the following steps is provided. First, a core layer having a first dielectric layer, a first patterned circuit layer, and a second patterned circuit layer is provided. The first patterned circuit layer and the second patterned circuit layer are disposed on an upper surface and a lower surface of the first dielectric layer, respectively. Then, a through hole is formed in the core layer. Next, the core layer is arranged on a supporting board and an embedded component having at least one electrode is disposed in the through hole. Afterward, a process of filling glue is carried out, such that the embedded component is fixed in the through hole. Thereafter, the supporting board is removed. Finally, the electrode of the embedded component is electrically connected to the second patterned circuit layer.

Abstract: A substrate and a method of making a substrate having a functionally gradient coefficient of thermal expansion are described herein. A system having a silicon die, an organic package substrate, and a substrate having a functionally gradient coefficient of thermal expansion, connecting the silicon die and the organic substrate is also described. The coefficient of thermal expansion at the upper surface of the substrate matches the coefficient of thermal expansion of the die, the coefficient of thermal expansion at the lower surface of the substrate matches the coefficient of thermal expansion of the package substrate, and the substrate has one or more coefficients of thermal expansion between the coefficients of thermal expansion of the upper and lower surfaces.

Abstract: Various methods and apparatus for coupling capacitors to a chip substrate are disclosed. In one aspect, a method of manufacturing is provided that includes forming a mask on a semiconductor chip substrate that has plural conductor pads. The mask has plural openings that expose selected portions of the plural conductor pads. Each of the plural openings has a footprint corresponding to a footprint of a smallest size terminal of a capacitor adapted to be coupled to the semiconductor chip substrate. A conductor material is placed in the plural openings to establish plural capacitor pads.

Abstract: Various method and apparatus for packaging an integrated circuit are provided. In one aspect, a method of packaging an integrated circuit is provided that includes coupling an integrated circuit to a substrate, mixing an adhesive with a plurality of particles, and coupling a lid to the substrate with the adhesive. At least a portion of the plurality of particles in the adhesive oppose compressive force from the lid to restrict rotation of the lid relative to the substrate.

Abstract: A wafer level package may include a semiconductor substrate supporting an electrode pad. A first insulating layer may be provided on the semiconductor substrate. The first insulating layer may include a first opening through which the electrode pad may be exposed. A seed metal layer may be provided on an entire surface of the first insulating layer. A redistribution interconnection metal layer may be provided on the seed metal layer. A second insulating layer may be provided on the redistribution interconnection metal layer. The second insulating layer may have a second opening spaced from the first opening to expose a portion of the redistribution interconnection metal layer. The second insulating layer may surround the redistribution interconnection metal layer. An unwanted portion of seed metal layer may be removed using the second insulating layer as an etch mask.

Abstract: Various semiconductor chip thermal management systems and methods are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a semiconductor chip to a substrate and coupling a diamond heat spreader that has a thermoelectric cooler to the semiconductor chip. A vapor chamber is coupled to the diamond heat spreader.

Abstract: An integrated circuit device having a flexible leadframe, and techniques for fabricating the flexible leadframe and integrated circuit device, are provided. In one aspect of the invention, an integrated circuit device comprises a heat spreader having a top surface and a bottom surface. At least one integrated circuit die is attached to the top surface of the heat spreader. A flexible leadframe is also attached to the top surface of the heat spreader. The flexible leadframe has one or more flexible layers, including at least one flexible insulating layer. A plurality of electrically conductive traces are defined on the at least one flexible insulating layer.

Abstract: A method for manufacturing a wire sweep resistant semiconductor package provides a die attached to an interposer. The die is electrically connected to the interposer with conductive wires. A sealant is applied on the die at the conductive wires for preventing wire sweep and the sealant is free of contact with the interposer. The die, the interposer, the conductive wires, and the sealant are encapsulated in an encapsulant.

Abstract: A silicon condenser microphone package includes a transducer unit, a substrate, and a cover. The substrate includes an upper surface transducer unit is attached to the upper surface of the substrate and overlaps at least a portion of the recess wherein a back volume of the transducer unit is formed between the transducer unit and the substrate. The cover is placed over the transducer unit and either the cover or the substrate includes an aperture.

Abstract: A cleaning sheet with frame for cleaning a molding die comprising a cleaning heat main body that covers the entire mating surface of a molding die and a reinforcing frame which can be disposed along the peripheral edge to the outside of the plural cavities of the mating surface of the molding die, the cleaning sheet main body being formed with first through holes at positions corresponding to the cavities of the molding die, air vent slits and flow cavity recesses at positions corresponding to the air vents of the cavities, second through holes at positions corresponding to the pots of the molding die, and slits at positions corresponding to the runners of the molding die, thereby capable of improving the cleaning effect of the molding die and shortening the time for the cleaning operation to improve the productivity.

Abstract: An element includes a hollow space for a mechanically sensitive electrical element. The element includes a first housing part and a second housing part rigidly connected to the first housing part via joint surfaces. The element also includes connection surfaces on a base of a recess in the first housing the first housing part being covered by the second housing part to form an enclosed hollow space.

Abstract: A method for forming a lid for a wafer-scale package includes (1) forming a cavity in a substrate, (2) forming an oxide layer over the cavity and over a bond area around the cavity on the substrate, (3) forming a reflective layer over the oxide layer, (4) forming a barrier layer over the reflective layer, (5) etching a portion of the barrier layer down to a portion of the reflective layer over the bond area, and (6) forming a solder layer on the portion of the reflective layer. The reflective layer can be a titanium-platinum-gold metal stack and the barrier layer can be a titanium dioxide layer.

Abstract: The specification teaches a technique for manufacturing microelectronic, microoptoelectronic or micromechanical devices (microdevices) in which a contaminant absorption layer improves the life and operation of the microdevice. In an embodiment, a process for manufacturing the devices includes efficiently integrating a getter material.

Abstract: A component for semiconductor package which has a protective insulating layer on at least one surface of a component body and exposes a conductive material of the component body to an opening part of the protective insulating layer is manufactured by a method including the steps of (a) forming a mask on at least one surface of the component body, (b) forming the protective insulating layer by filling an opening part of the mask with a protective insulating material by a molding method using a metal mold comprising a mold release film, and (c) removing the metal mold and removing the mask. A typical component is a lead frame or a substrate for semiconductor package.

Abstract: A semiconductor package and mounting method of improving reliability by strengthening adhesive strength of both a printed circuit board and a surface mounting package, includes a chip pad on which a semiconductor device is disposed, and lead terminals, wherein at least one of the chip pad and the lead terminals have a plurality of grooves. Accordingly, in comparison with a typical package, since a plurality of grooves are formed on both a chip pad and lead terminals of a package adhering to a printed circuit, an adhesive area of both the package and the cream solder is widened so that the shearing strength may be improved and greater solder joint reliability can be acquired.

Abstract: A method of electrically connecting a microelectronic component having a first surface bearing a plurality of contacts. The method including the steps of forming a subassembly by juxtaposing a connection component having a support structure and a plurality of elongated posts extending substantially parallel to one another from a first surface of the support structure with the microelectronic component so that the support structure overlies the surface of the component with the posts extending away from the component and electrically connecting the posts to the contacts of the microelectronic component.

Abstract: In a multilayer circuit board of the present invention, a plurality of circuit substrates configured by forming a circuit pattern on an insulating base material are stacked via an insulating layer, a through-hole and a via hole are formed in the layering direction, and laser processability and laser processing speed for a processing laser beam used in formation of the through-hole and the via hole are about the same for the insulating substrate material and the insulating layer.

Abstract: A method for manufacturing a semiconductor package that includes forming a frame inside a conductive can, the frame being unwettable by liquid solder.

Abstract: The present invention stacks integrated circuits (ICs) into modules that conserve PWB or other board surface area. In another aspect, the invention provides a lower capacitance memory expansion addressing system and method and preferably with the CSP stacked modules provided herein. In a preferred embodiment in accordance with the invention, a form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design. In a preferred embodiment, the form standard will be devised of heat transference material such as copper to improve thermal performance. In an alternative embodiment, the form standard may include a heat spreader portion with mounting feet. In a preferred embodiment of the memory addressing system, a high speed switching system selects a data line associated with each level of a stacked module to reduce the loading effect upon data signals in memory access.

Abstract: A semiconductor package has: a semiconductor chip having first and second main electrodes arranged on two principal surfaces being opposite to each other; a first main wiring plate connected to the first main electrode and having a first external connection terminal; a second main wiring plate connected to the second main electrode and having a second external connection terminal; a first shell connected through an insulating film to at least a part of a second principal surface of the first main wiring plate, the second principal surface of the first main wiring plate being opposite to a first principal surface of the first main wiring plate that is connected to the first electrode; and a second shell connected through an insulating film to at least a part of a second principal surface of the second main wiring plate, the second principal surface of the second main wiring plate being opposite to a first principal surface of the second main wiring plate that is connected to the second electrode.

Abstract: Microlenses for directing radiation toward a sensor of an imaging device include a plurality of mutually adhered layers of cured optically transmissive material. Systems include at least one microprocessor and a substrate including an array of microlenses formed thereon in electrical communication with the at least one microprocessor. At least one microlens in the array includes a plurality of mutually adhered layers of cured optically transmissive material.

Abstract: A structure and a method for forming the same. The structure includes (i) a carrier substrate which includes substrate pads, (ii) a chip physically attached to the carrier substrate, and (iii) a first frame physically attached to the carrier substrate. A CTE (coefficient of thermal expansion) of the first frame is substantially lower than a CTE of the carrier substrate.

Abstract: A wafer level package includes a device wafer having a micro device, and bonding pads which are connected to the micro device, and formed at one surface of the device wafer, via connectors extending from the bonding pads to the other surface of the device wafer, external bonding pads formed at the other surface of the device wafer and connected to the bonding pads through the via connectors, and a cap structure bonded to one surface of the device wafer so as to allow the micro device to be insulated and hermetically sealed.

Abstract: Embodiments of the invention provide a method for fabricating a system in package. In one embodiment, the method comprises preparing a printed circuit board (PCB) strip comprising a plurality of individual PCBs, stacking a plurality of first semiconductor chips and forming an encapsulant on a first surface of a first individual PCB of the plurality of individual PCBs to form a first semiconductor chip stack structure comprising a first semiconductor chip stack, and performing a first test adapted to test one of the first semiconductor chips in the first semiconductor chip stack. The method further comprises flip chip bonding a second semiconductor chip to a second surface of the first individual PCB if the first semiconductor chip stack structure meets a test standard based on a result of the first test, and dividing the first semiconductor chip stack structure to form a system in package.

Abstract: One embodiment of the present invention provides an integrated chip module and a corresponding method of manufacture that facilitates proximity communication. This module includes a base chip and a bridge chip, both of which include an active face, upon which active circuitry and signal pads reside, and a back face opposite the active face. The active face of the bridge chip is bonded to the active face of the base chip, and the back face of the bridge chip is thinned via planarization or polishing.

Abstract: A printed wiring board for mounting a semiconductor, which printed wiring board has a taper-shaped through hole connecting an upper surface circuit and a lower surface circuit, and/or an internal layer circuit, the taper-shaped through hole being obtained by plating an inner wall surface and a small-diameter side end of a taper-shaped penetration hole with a metal to plate the inner wall surface and seal the small-diameter side end, wherein a ball pad or a bump pad is formed at least a small-diameter side end of the taper-shaped through hole.

Abstract: A semiconductor device capable of wireless communication, which has high reliability in terms of resistance to external force, in particular, pressing force and can prevent electrostatic discharge in an integrated circuit without preventing reception of an electric wave. The semiconductor device includes an on-chip antenna connected to the integrated circuit and a booster antenna which transmits a signal or power included in a received electric wave to the on-chip antenna without contact. In the semiconductor device, the integrated circuit and the on-chip antenna are interposed between a pair of structure bodies formed by impregnating a fiber body with a resin. One of the structure bodies is provided between the on-chip antenna and the booster antenna. A conductive film having a surface resistance value of approximately 106 to 1014 ?/cm2 is formed on at least one surface of each structure body.

Abstract: A method of making an encapsulated plasma sensitive device. The method comprises: providing a plasma sensitive device adjacent to a substrate; depositing a plasma protective layer on the plasma sensitive device using a process selected from non-plasma based processes, or modified sputtering processes; and depositing at least one barrier stack adjacent to the plasma protective layer, the at least one barrier stack comprising at least one decoupling layer and at least one barrier layer, the plasma sensitive device being encapsulated between the substrate and the at least one barrier stack, wherein the decoupling layer, the barrier layer, or both are deposited using a plasma process, the encapsulated plasma sensitive device having a reduced amount of damage caused by the plasma compared to an encapsulated plasma sensitive device made without the plasma protective layer. An encapsulated plasma sensitive device is also described.

Abstract: A substrate for an electronic component comprises a dielectric body having an upper surface including a plurality of inner contact pads and a lower surface including a plurality of outer contact pads. Each outer contact pad has an inner face and an outer face. An insulating layer covers the lower surface of the dielectric body and the peripheral regions of the plurality of outer contact pads. A depression is located in the approximate lateral centre of the outer face of each of the plurality of outer contact.

Abstract: An LGA structure is provided having at least one semiconductor device over a substrate and a mechanical load apparatus over the semiconductor device. The structure includes a load-distributing material between the mechanical load apparatus and the substrate. Specifically, the load-distributing material is proximate a first side of the semiconductor device and a second side of the semiconductor device opposite the first side of the semiconductor device. Furthermore, the load-distributing material completely surrounds the semiconductor device and contacts the mechanical load apparatus, the substrate, and the semiconductor device. The load-distributing material can be thermally conductive and comprises an elastomer and/or a liquid. The load-distributing material comprises a LGA interposer adapted to connect the substrate to a PCB below the substrate and/or a second substrate. Moreover, the load-distributing material comprises compressible material layers and rigid material layers.

Abstract: Semiconductor module comprising semiconductor chips in a plastic housing in separate regions and method for producing the same The invention relates to a semiconductor module (9) comprising semiconductor chips (1, 2) in a plastic housing (3) in separate regions (4, 5), and to a method for producing the same. In this case, the semiconductor module (9) has adjacent regions (4, 5) on a common wiring substrate (7) in a common plastic housing composition (6), said regions being thermally decoupled by a thermal barrier (8). Semiconductor chips whose evolution of heat loss differs are arranged in these thermally separate regions (4, 5), the thermal barrier (8) ensuring that the function of the more thermally sensitive semiconductor chip (2) is not impaired by the heat-loss-generating semiconductor chip (1).

Abstract: The invention provides thermally enhanced BGAs and methods for their fabrication with a ground ring suitable for operably coupling to either the frontside or backside, or both, of an IC chip mounted on a substrate. The methods and devices of the invention disclosed include the fabrication of a ground ring on the surface of a BGA substrate prepared for receiving the frontside of the chip. A heat spreader has ground ring corresponding to substrate round ring and is attached at the backside of the chip with a conductive material. A conductive material is interposed between the heat spreader and substrate ground rings, electrically coupling them. Thus, the backside of the chip may be electrically connected to the ground ring as well as, or instead of, the frontside.

Abstract: A semiconductor chip scale package formed with through-vias, which can be either isolated or electrically connected to a substrate, and a method of producing the semiconductor chip scale package with through-vias, which can be isolated or electrically connected to the substrate.

Abstract: A power module fabrication method and structure thereof is disclosed.

Abstract: Presented is a method for simultaneously producing a multiplicity of surface-mountable semiconductor components each having at least one semiconductor chip, at least two external electrical connections, which are electrically conductively connected to at least two electrical contacts of the semiconductor chip, and an encapsulation material.

Abstract: Structures and methods for forming the same. A semiconductor chip includes a semiconductor substrate and a transistor on the semiconductor substrate. The chip further includes N interconnect layers on top of the semiconductor substrate and being electrically coupled to the transistor, N being a positive integer. The chip further includes a first dielectric layer on top of the N interconnect layers, and a second dielectric layer on top of the first dielectric layer. The second dielectric layer is in direct physical contact with each interconnect layer of the N interconnect layers. The chip further includes an underfill layer on top of the second dielectric layer. The second dielectric layer is sandwiched between the first dielectric layer and the underfill layer. The chip further includes a laminate substrate on top of the underfill layer. The underfill layer is sandwiched between the second dielectric layer and the laminate substrate.

Abstract: Non-volatile data memory cards, flash drives and other memory devices are customized by manufacturing core memory units all the same and then covering them by outer skins which may be made to have different appearances and/or tactile characteristics. The skins are slid over the core memory units by hand from one end. End users of such memory devices may then select how they will look and feel by separately purchasing covers. Sellers of such memory devices may more easily control how their products look and feel.