Abstract: A first insulating substrate is formed on a heat sink, and a semiconductor element is formed thereon. An insulating resin casing is formed so as to cover the first insulating substrate and the semiconductor element. A second insulating substrate is mounted inside the insulating resin casing apart from the first insulating substrate. On the second insulating substrate, a resistance element that functions as a gate balance resistance is fixed by soldering. The second insulating substrate on which the resistance element was thus mounted was made apart from the first insulating substrate on which the semiconductor element was mounted, and was mounted on the side of the insulating resin casing.

Abstract: A method for manufacturing a layered structure for routing electrical signals comprising the steps of providing a layout for the layered structure having an insulating layer with at least one signal trace, a via, and a stub trace on a first side of the insulating layer, and a generally planar electrically conductive layer disposed on a second side of the insulating layer. Identify the stub trace and define a beneficial portion on the second side based upon a layout of the stub trace where the electrically conductive layer on the second side is to be absent. Modify the layout according to the step of defining and manufacture the layered structure according to the modified layout.

Abstract: A film, based on polyimide or epoxy, is laminated onto a surface of a substrate under a vacuum, so that the film closely covers the surface and adheres thereto. Contact surfaces to be formed on the surface are uncovered by opening windows in the film. A contact is established in a plane manner between each uncovered contact surface and a layer of metal. This establishes a large-surface contact providing high current density for power semiconductor chips.

Abstract: An hermetic, gas filled or vacuum package device and method of making a vacuum package device. The device includes a device layer having one or more Micro Electro-Mechanical Systems (MEMS) devices. The device layer includes one or more electrical leads coupled to the one or more MEMS devices. The device also includes a first wafer having one or more silicon pins, wherein a first surface of the first wafer is bonded to a first surface of the device layer in such a manner that the one or more silicon pins are in electrical communication with the electrical leads. A second wafer, which may also have one or more silicon pins, is bonded to a second surface of the device layer. The first and second wafers are formed of borosilicate glass and the device layer is formed of silicon.

Abstract: A semiconductor package is disclosed that includes a semiconductor device; a circuit board; and a connection mechanism including a first conductive terminal provided on the semiconductor device, and a second conductive terminal provided on the circuit board side, the connection mechanism electrically connecting the semiconductor device and the circuit board via the first conductive terminal and the second conductive terminal. At least one of the first conductive terminal and the second conductive terminal of the connection mechanism includes one or more carbon nanotubes each having one end thereof fixed to the surface of the at least one of the first conductive terminal and the second conductive terminal, and extending in a direction away from the surface. The first conductive terminal and the second conductive terminal engage each other through the carbon nanotubes.

Abstract: An integrated circuit product includes a die and an insulation layer. The insulation layer is operatively coupled to the die. The insulation layer includes a plurality of bump apertures. The insulation layer also includes an underfill anchor structure. Methods for making such an integrated circuit product are also described.

Abstract: A package includes a substrate provided with a passing opening and a MEMS device. The MEMS device includes an active surface wherein a portion of the MEMS device is integrated sensitive to the chemical/physical variations of a fluid. The active surface of the MEMS device faces the substrate and is spaced therefrom, the sensitive portion being aligned to the passing opening. A protective package incorporates the MEMS device and the substrate, leaving at least the sensitive portion of the MEMS device exposed through the passing opening of the substrate.

Abstract: A semiconductor device includes a tape carrier substrate having a flexible insulating film base, a plurality of conductor wirings provided on the film base, and wiring bumps respectively formed so as to cover an upper surface and both side surfaces of the conductor wirings, and a semiconductor chip mounted on the tape carrier substrate, wherein electrodes of the semiconductor chip are connected to the conductor wirings via the wiring bumps. Electrode bumps are formed on the electrodes of the semiconductor chip, the electrodes of the semiconductor chip are connected to the conductor wirings via a bonding between the wiring bumps and the electrode bumps, and the electrode bumps are harder than the wiring bumps. This structure can reduce bonding damages to the electrodes of the semiconductor chip caused by a process of connecting the electrodes and the conductor wirings via the bumps.

Abstract: This method of manufacturing a lid made of a transparent resin comprises a step of introducing a resin into a cavity for molding a protrusion continuous with a cavity for molding a lid in a die; a step of forming a molded body including a lid and a protrusion continuous with the lid by solidifying the resin in the cavity for molding a lid and the cavity for molding a protrusion, respectively; a step of separating the molded body from the die by ejecting an ejector pin to the protrusion; and a step of separating the protrusion from the lid.

Abstract: Stacked CSP (chip scale package) modules include a molded first (“top”) chip scale package having a molding side and a substrate side, and a second (“bottom”) package affixed to the substrate side of the top chip scale package, the second package being electrically connected to the first package by wire bonding between the first and second package substrates.

Abstract: The invention relates to an electrical component having a resistance area and contacts electrically connected to the resistance area, the resistance area including electrically conductive diamond. The resistance area can be configured as a resistance layer on top of a substrate while the substrate can be made at least in part of electrically non-conducting diamond.

Abstract: Disclosed is a ball grid array (BGA) package substrate, in which a wire bonding pad and a solder ball pad are formed on a via hole, making high freedom in design of a circuit pattern and a high density circuit pattern possible, and a method of fabricating the same.

Abstract: A semiconductor chip is provided that is highly packageable and particularly well suited for mounting on a circuit board having a curved surface. The semiconductor chip comprises a warpage control film that controls the warpage of a substrate.

Abstract: A semiconductor chip package and printed circuit board assembly including the same which have a variable mounting orientation include a semiconductor chip disposed on a first surface of an insulating substrate, connectors symmetrically disposed at respective first and opposite second sides of the insulating substrate, a plurality of input/output connecting leads and power connecting leads electrically connected by connecting members to a plurality of internal circuits of the semiconductor chip, at least two internal circuits of the plurality of internal circuits being substantially similar circuits, and a radiating pad disposed on a second opposite surface of the insulating substrate and which is electrically connected to the semiconductor chip.

Abstract: A silicon condenser microphone package is disclosed. The silicon condenser microphone package comprises a transducer unit substrate, and a cover. The substrate includes an upper surface having a recess formed therein. The transducer unit is attached to the upper surface of the substrate and overlaps at least a portion of the recess wherein a back volume of the transducer unit is formed between the transducer unit and the substrate. The cover is placed over the transducer unit and includes an aperture.

Abstract: A package of the present invention has a laminate structure of a plurality of ceramic layers, and includes a cavity for housing a light emitting element. A mount surface is defined on a side surface parallel with the depth direction of the cavity. A pair of external electrodes each including a charged electrode portion and a coated electrode portion are formed over the entire length in the laminating direction at two corners defined by intersection of the mount surface and two side surfaces perpendicular to the mount surface. When the package is mounted, a pair of charged electrode portions and a pair of coated electrode portions are soldered to a surface of a substrate.

Abstract: One aspect of the invention relates to a semiconductor device including a housing and a semiconductor chip partly embedded in a plastic housing composition. Another aspect relates to a method for producing the same. The plastic housing composition has at least one host component having a softening temperature and an incorporated component having a phase change temperature. In this case, the softening temperature of the host component is greater than the phase change temperature of the incorporated component.

Abstract: Stacked package assemblies include first and second stacked packages, each having at least one die affixed to, and electrically interconnected with, a die attach side of the package substrate. One package is inverted in relation to the other, that is, the die attach sides of the package substrates face one another, and the “land” sides of the substrates face away from one another. Z-interconnection of the packages is by wire bonds connecting the first and second package substrates. The assembly is encapsulated in such a way that both the second package substrate (one side of the assembly) and a portion of the first package substrate (on the opposite side of the assembly) are exposed, so that second level interconnection and interconnection with additional components may be made. One or more additional components may be stacked over the land side of the first package substrate.

Abstract: The yield of a sealing process for a semiconductor device which adopts a flip-chip mounting method is to be improved. In a molding process wherein plural semiconductor chip ICs mounted on a parts mounting surface of a substrate matrix through bump electrodes are to be sealed all together with a sealing resin in a reduced state of the internal pressure of a cavity of a molding apparatus, a clamping pressure at the time of clamping the substrate matrix by both a lower die and an upper die of a molding die is set at a relatively low pressure in an initial stage of injection of the sealing resin and is changed to a relatively high pressure when the sealing resin has covered the semiconductor chip ICs located in a final stage in the resin injecting direction.

Abstract: The invention relates to an LED package and proposes a method of fabricating an LED package including steps of providing a package substrate having a mounting area of an LED and a metal pattern to be connected with the LED, and plasma-treating the package substrate to reform at least a predetermined surface area of the package substrate where a resin-molded part will be formed. The method also includes mounting the LED on the mounting area on the substrate package and electrically connecting the LED with the metal pattern, and forming the resin-molded part in the mounting area of the LED to seal the LED package.

Abstract: Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided.

Abstract: A stacked integrated circuit package-in-package system is provided forming a first integrated circuit package having a first encapsulation and a second integrated circuit package having a second encapsulation, stacking the first integrated package below the second integrated circuit package with the first encapsulation attached to the second encapsulation, forming a substrate having an opening from a substrate top surface to a substrate bottom surface, mounting the first integrated circuit package over the substrate top surface, electrically connecting the first integrated circuit package and the substrate bottom surface through the opening, and electrically connecting the second integrated circuit package and the substrate top surface.

Abstract: A housing accommodating a semiconductor chip is set out. The housing and chip may be used for sending and/or receiving radiation. Popular applications of the housing may be in light emitting diodes. The housing includes a conductor strip that is punched into two electrically isolated portions. The housing further includes a cavity extending inwards from the top of the housing. The conductor portions include respective areas that are exposed at the bottom of the cavity. The semiconductor chip is bonded to one of the exposed areas and a wire bonds the chip to the second exposed area. The conductor portions also terminate in exposed electrodes, which allow for electrical connection of the chip with external devices. A window is formed in the cavity and the walls of the housing that form the cavity may be made of a reflective material. The electrodes remain unexposed to the window but for any residual areas about the chip and bonding wire within the first and second exposed areas.

Abstract: A method is provided for making a semiconductor multi-package module, by providing a lower molded ball grid array package including a lower substrate and a die, affixing an upper molded package including an upper substrate in inverted orientation onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.

Abstract: A method of forming a protective barrier in an organic light emitting device is disclosed, wherein the organic light emitting device is formed on a substrate and includes a plurality of layers of materials, the plurality of layers of materials including an organic light emitting layer. The method includes forming an inorganic layer and a semi-crystalline parylene-based polymer layer over an underlying layer, wherein the semi-crystalline parylene-based polymer layer is formed via transport polymerization of a reactive intermediate species. Organic light emitting devices having barriers are also disclosed.

Abstract: To provide a semiconductor device with high performance and reliability, in which peeling off an interconnection layer caused due to peeling off of a resin film at a land part is suppressed and thus electrical break down is prevented, and an efficient method for manufacturing the semiconductor device. The semiconductor device includes a semiconductor substrate (e.g., a silicon wafer 10); an insulating film 12 formed on the semiconductor substrate 10; a conductive layer 20 formed on the insulating film 12, the conductive layer 20 formed of an interconnection part 22 and a land part 24 which connects the interconnection part 22 to an external terminal 40; and a resin film 30 covering the conductive layer 20, wherein the resin film 30 is in contact with the insulating film 12 at least at a part of the land part 24 by passing through the conductive layer 20.

Abstract: Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one embodiment, a method for manufacturing a plurality of microelectronic imaging units includes placing a plurality of singulated imaging dies on a support member. The individual imaging dies include a first height, an image sensor, an integrated circuit operably coupled to the image sensor, and a plurality of external contacts operably coupled to the integrated circuit. The method further includes electrically connecting the external contacts of the imaging dies to corresponding terminals on the support member and forming a base on the support member between adjacent imaging dies. The base has a second height less than or approximately equal to the first height of the dies. The method further includes attaching a plurality of covers to the base so that the covers are positioned over corresponding image sensors.

Abstract: A semiconductor arrangement has a silicon body with a first surface and a second surface and a thick metal layer arranged on at least one surface of the silicon body. The thickness of the thick metal-layer is at least 10 micrometers (?m).

Abstract: Productivity of a semiconductor integrated circuit device is improved. According to how many times the photomask is used, a photomask having an opaque pattern made of metal and a photomask having an opaque pattern made of a resist film are properly used, and thereby an exposure treatment is performed.

Abstract: A metal interconnection for two workplaces such as a semiconductor chip and an insulating substrate. The first workpiece (101) has a first contact pad (201) with a gold stud (110); the second workplace (103) is covered with an insulating layer (213) and a window in the layer to a second contact pad (211). The interconnection between the second pad and the gold stud is a 278° C. eutectic structure (111) with about 80 weight percent gold and about 20 weight percent tin. The eutectic structure has a Young's modulus of 59.2 GPa and a lamellar micro-structure of the phases Au5Sn and AuSn. There is substantially no metallic tin at the second contact pad.

Abstract: A microelectronic cooling assembly and method for fabricating the same are described. In one example, a microelectronic cooling assembly includes a microelectronic device, a heat spreader, and a thermal interface material (TIM) that thermally joins the microelectronic device and heat spreader, the TIM comprising a sintered metallic nanopaste.

Abstract: A memory module and a method of mounting memory devices on a PCB to form the memory module substantially reduce unnecessary routing space and improve signal attenuation characteristics. In the method of mounting and sequentially connecting at least two memory devices on a printed circuit board (PCB) having an axis of elongation to form a memory module, at least one of the memory devices is mounted on at least one face of the PCB so that a base line along an longitudinal axis of the at least one memory device lies at an acute angle with respect to the axis of elongation of the PCB.

Abstract: The invention is directed to a hermetically sealed device and a method for making such device. The device includes optical, micro-electromechanical, electronic and opto-electronic devices, having a substrate with one or a plurality of optical, opto-electronic, electronic or micro-electromechanical (“MEMS”) elements either singly or in combination that are located on a substrate; a covering having a top part and an extension extending a distance from the top part from the top part, an adhesive that is used to bond the extension portion of the covering to the substrate; and a sealing agent for hermetically sealing the area where the covering extension is bonded to the substrate. In the method of the invention the sealing agent is applied using atomic layer deposition techniques.

Abstract: A process for fabricating an integrated circuit package includes: selectively etching a first side of a substrate thereby providing etched regions of the substrate to partially define at least a plurality of contact pads; adding a dielectric material to the etched regions of the substrate; selectively etching a second side of the substrate to further define at least the plurality of contact pads and thereby provide a package base of at least the contact pads and the dielectric; mounting a semiconductor die to the package base and connecting the semiconductor die to the contact pads; fixing a lid to the package base to cover the semiconductor die in a cavity between the lid and the package base; and singulating to provide the integrated circuit package.

Abstract: A system and method for manufacturing a thermal expansion pre-compensated package system. The system including a substrate having a first and a second planar surface. The first planar surface being opposed to the second planar surface. The system further including a mold compound having a third and a fourth planar surface. The fourth planar surface affixed to the first planar surface of the substrate to provide a low stress interface. A cavity is formed in the third planar surface of the mold compound.

Abstract: A circuit board with an built-in electronic component according to the present invention includes an insulating layer, a first wiring pattern provided on a first main surface of the insulating layer, a second wiring pattern provided on a second main surface different from the first main surface of the insulating layer, and an electronic component such as a semiconductor chip or the like provided in an internal portion of the insulating layer. The electronic component includes a first external connection terminal formed on a first surface and a second external connection terminal formed on a second surface different from the first surface. The first external connection terminal is connected electrically to the first wiring pattern, and the second external connection terminal is connected electrically to the second wiring pattern.

Abstract: A stacked chip semiconductor package may be formed in a “package in package” arrangement. The internal package may include two substrates. One substrate may have two dice stacked on each of two opposed sides and the other substrate may have two dice stacked on it as well. The two stacked substrates may be separated by molding compound and then electrically coupled to a third substrate. Thereafter, the entire assembly may be encapsulated.

Abstract: A method of packaging a plurality of semiconductor chips comprises: providing a substrate panel having a first coefficient of thermal expansion (CTE); providing a carrier having a second CTE that is less than the first CTE; heating the substrate panel and the carrier to first and second elevated temperatures respectively; mounting the substrate panel at about the first elevated temperature to the carrier, the carrier being at said second elevated temperature, to provide a connection between the carrier and the substrate panel; and cooling the carrier and the substrate panel from the first and second elevated temperatures thereby putting the substrate panel into tension in at least one direction. A stiffener panel may be affixed to the substrate panel and heated to an elevated temperature and while the substrate panel is heated to an elevated temperature. A plurality of dies may be mounted and electrically connected to the substrate panel.

Abstract: The present invention provides a lubricant container inside a microelectromechanical device package. The lubricant container contains selected lubricant that evaporates from the container and contact to a surface of the microelectromechanical device for lubricating the surface.

Abstract: Integrated circuit assembly including a die stack assembly having a heat dissipation device thermally coupled to a lateral of surface the die stack assembly. The die stack assembly includes a plurality integrated circuits placed on each other. In another embodiment a heat dissipation device comprising an encapsulant is thermally coupled to and surrounds a die stack assembly that includes a plurality of integrated circuits placed on each other. At least one heat conducting intermediate layer between integrated circuits is thermally coupled to the heat dissipation device.

Abstract: A method of sealing and leading out an electrode for an MEMS device such as an angular velocity sensor, an acceleration sensor, or a combined sensor is provided. A fixed portion is formed within a device forming region surrounded with a base support, a beam is connected to the fixed portion, and a movable portion is connected to the beam. Further, a detection portion for detecting the displacement of the movable portion is disposed within the device forming region. An interconnection is connected to the movable portion and the detection portion, and the interconnection extends from the hermetically sealed device forming region to the external region at the outside. The interconnection penetrates the base support and is connected with the terminal. A hole is formed between the interconnection and the base support, and an insulating film is formed in the hole. The interconnection and the base support are insulated by an insulating film buried in the hole.

Abstract: Methods and apparatuses for encapsulating a microelectronic die or other components in the fabrication of packaged microelectronic devices. In one aspect of the invention, a packaged microelectronic device assembly includes a microelectronic die, a substrate attached to the die, a protective casing covering a portion of the substrate, and a barrier projecting away from the surface of the substrate. The microelectronic die can have an integrated circuit and a plurality of bond-pads operatively coupled to the integrated circuit. The substrate can have a cap-zone defined by an area that is to be covered by the protective casing, a plurality of contact elements arranged in the cap-zone, a plurality of ball-pads arranged in a ball-pad array outside of the cap-zone, and a plurality of conductive lines coupling the contact elements to the ball-pads. The contact elements are electrically coupled to corresponding bond-pads on the microelectronic die, and the protective casing covers the cap-zone.

Abstract: A semiconductor device mountable to a substrate is provided. The device includes a semiconductor die and an electrically conductive attachment region having a first attachment surface and a second attachment surface. The first attachment surface is arranged for electrical communication with the semiconductor die. An interlayer material is formed on the second attachment surface of the electrically conductive attachment region. The interlayer material is a thermally conductive, dielectric material. A housing at least in part encloses the semiconductor die and the interlayer material.

Abstract: When a two-division structure heat treatment jig for semiconductor substrate that includes a silicon first jig that comes into direct contact with a semiconductor substrate that is heat treated and supports the semiconductor substrate, and a second jig (holder) that holds the first jig and is mounted on a heat treatment boat is adopted as a heat treatment boat of a vertical heat treatment furnace, the stress concentrated during the heat treatment on a particular portion of the semiconductor substrate can be reduced; in the case of a semiconductor substrate large in the tare stress and having an outer shape of 300 mm being heat treated, or even in the case of the heat treatment being carried out under very high temperature conditions, the slips can be suppressed from occurring. The present invention can be widely applied as a stable heat treatment method of semiconductor substrates.

Abstract: The manufacturing process of a circuit board includes forming a thermal interface layer on a first metal thin layer of a thermal plate. Joining a second metal layer of a main circuit board comprises at least one opening with the thermal interface layer. Then, reflowing the main circuit board with the joined thermal plate. A circuit board with a cooling function using the foregoing manufacturing process is also provided.

Abstract: Methods for preparing thermally enhanced multilayer substrates and methods for their use in assembling BGA packages are disclosed. Steps in preferred embodiments of the invention include opening a hole in a dielectric material at one surface of a multilayer substrate thereby forming a die pad on the second metal layer or primary thermal spreading layer. A plurality of vias are provided through the substrate from the surface of the die pad to the opposing surface of the substrate. In an alternative embodiments of the invention, an embedded thermal conductor is also formed on the die pad. In another embodiment, a hole in an bottom dielectric layer exposing a bottom metal layer and embedded thermal conductor may also be provided between the bottom of the substrate and the second metal layer from the bottom, e.g. the third and fourth layers. The die pad may be plated, cleaned, and/or masked to receive a die.

Abstract: A plate structure having a chip embedded therein, comprises an aluminum oxide plate having an upper surface, a lower surface, plural aluminum channels connected to the upper surface and the lower surface, and a cavity therein; a chip embedded in the cavity, wherein the chip has an active surface; at least one electrode pad mounted on the active surface; and at least one build-up structure mounted on the surface of the aluminum oxide plate and the active surface of the chip, wherein the build-up structure comprises at least one conductive structure to electrically connect to the electrode pad. Besides, a method of manufacturing a plate structure having a chip embedded therein is disclosed.

Abstract: A method of sizing a load plate for an Application Specific Integrated Circuit (ASIC) assembly includes compressing the load plate prior to installation in the ASIC assembly. The compression is adjusted to cause the load plate to provide a target load when installed in the ASIC assembly.

Abstract: A method of manufacturing a module, formed of a semiconductor element flip-chip bonded to a substrate and chip component soldered to the substrate, is disclosed. The method includes a step of mounting the chip component and the semiconductor element to the substrate, a first injection step for injecting first resin from a center of a lateral face of the semiconductor element into a gap between the semiconductor element and the substrate, a second injection step for applying second resin having a greater viscosity than the first resin to corners of the semiconductor element before the first resin reaches the corners, and a curing step for heating the module. This method allows mounting the chip component closer to the semiconductor element, so that the component can be mounted at a higher density on the module.

Abstract: In a method for manufacturing an acceleration sensor device, a lid for covering an opening of a package body is prepared by stamping. The lid is plated and plating films are formed on surfaces of the lid. The burrs formed on the surfaces of the lid in the plating process are removed by chemical polishing. A semiconductor sensor chip is inserted in the package body through the opening and fixed. Then, the lid 70 is attached to the package body.