Abstract: A phase change memory device including a phase change layer includes a storage node and a switching device. The switching device is connected to the storage node. The storage node includes a phase change layer selectively grown directly on a lower electrode. In a method of manufacturing a phase change memory device, an insulating interlayer is formed on a semiconductor substrate to cover a switching device. A lower electrode connected to the switching device is formed, and a phase change layer is selectively grown directly on the lower electrode.

Abstract: An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for at least partially enclosing a FeCap array with hydrogen barrier walls and a hydrogen barrier top plate.

Abstract: A multi-operation mode application specific integrated circuit (ASIC) implemented in fully-depleted silicon-on-insulator (FDSOI) includes an ASIC implemented in FDSOI having a plurality of operating modes, plurality of power rails, and a power supply that provides voltages for the first and second rails corresponding to the plurality of operating modes. The power rails include at least one VDD rail, at least one Vss rail, a first rail for biasing a NGP region of PMOS transistor devices in the ASIC, and a second rail for biasing a PGP region of NMOS transistor devices in the ASIC.

Abstract: Embodiments disclosed herein may relate to electrically conductive vias in cross-point memory array devices. In an embodiment, the vias may be formed using a lithographic operation also utilized to form electrically conductive lines in a first electrode layer of the cross-point memory array device.

Abstract: Nanostructure array optoelectronic devices are disclosed. The optoelectronic device may be a multi junction solar cell. The optoelectronic device may have a bi-layer electrical interconnect that is physically and electrically connected to sidewalls of the array of nanostructures. The optoelectronic device may be operated as a multi junction solar cell, wherein each junction is associated with one portion of the device. The bi-layer electrical interconnect allows current to pass from one portion to the next. Thus, the bi-layer electrical interconnect may serve as a replacement for a tunnel junction, which is used in some conventional multi junction solar cells.

Abstract: A leadframe-based semiconductor package and a fabrication method thereof are provided. The leadframe-based semiconductor package includes a chip implanted with a plurality of first and second conductive bumps thereon, and a leadframe having a plurality of leads. The first conductive bumps are bonded to the leads to electrically connect the chip to the leadframe. The chip, the first and second conductive bumps, and the leadframe are encapsulated by an encapsulant, with bottom ends of the second conductive bumps and bottom surfaces of the leads being exposed from the encapsulant. This allows the second conductive bumps to provide additional input/output electrical connections for the chip besides the leads.

Abstract: A method of forming an active region structure includes preparing a semiconductor substrate including a cell array region and a peripheral circuit region, forming preliminary cell active regions in the cell array region of the semiconductor substrate, and forming cell active regions in the preliminary cell active regions and at least one peripheral active region in the peripheral circuit region of the semiconductor substrate, such that the preliminary cell active regions, the cell active regions, and the at least one peripheral active region are integrally formed with the semiconductor substrate and protrude from the semiconductor substrate.

Abstract: Programmable nanotube interconnect is disclosed. In one embodiment, a method includes forming a interconnect layer using a plurality of nanotube structures, and automatically altering a route of an integrated circuit based on an electrical current applied to at least one of the plurality of nanotube structures in the interconnect layer. Neighboring interconnect layers separated by planar vias may include communication lines that are perpendicularly oriented with respect to each of the neighboring interconnect layers. The nanotube structure may be chosen from a group comprising a polymer, carbon, and a composite material. A carbon nanotube film may be patterned in a metal layer to form the plurality of nanotube structures. A sputtered planar process may be performed across a trench of electrodes to create the carbon nanotube structures.

Abstract: An array of vertically stacked tiers of non-volatile cross point memory cells includes a plurality of horizontally oriented word lines within individual tiers of memory cells. A plurality of horizontally oriented global bit lines having local vertical bit line extensions extend through multiple of the tiers. Individual of the memory cells comprise multi-resistive state material received between one of the horizontally oriented word lines and one of the local vertical bit line extensions where such cross, with such ones comprising opposing conductive electrodes of individual memory cells where such cross. A plurality of bit line select circuits individually electrically and physically connects to individual of the local vertical bit line extensions and are configured to supply a voltage potential to an individual of the global horizontal bit lines. Other embodiments and aspects are disclosed.

Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.

Abstract: A semiconductor device includes a semiconductor substrate including a first region having a cell region and a second region having a peripheral circuit region, first transistors on the semiconductor substrate, a first protective layer covering the first transistors, a first insulation layer on the first protective layer, a semiconductor pattern on the first insulation layer in the first region, second transistors on the semiconductor pattern, a second protective layer covering the second transistors, the second protective layer having a thickness greater than that of the first protective layer, and a second insulation layer on the second protective layer and the first insulation layer of the second region.

Abstract: In a layout for a semiconductor device, each active region comprises a first active region, a right active region on the right side of the first active region, a left active region on the left side of the first active region, an upper active region on the upper side of the first active region and a lower active region on the lower side of the first active region, wherein the first active region, the right active region, the left active region, the upper active region and the lower active region each have an inclined portion having a bit-line contact region; and first and second portions having a storage node contact region, first and second ends formed on left and right ends of the inclined portion at a predetermined tilt angle with respect to the inclined portion, the active region being intersected by two word lines and one bit line.

Abstract: A symmetrical circuit is disclosed (FIG. 4). The circuit includes a first transistor (220) having a first channel in a substantial shape of a parallelogram (FIG. 5A) with acute angles. The first transistor has a first current path (506) oriented in a first crystal direction (520). A first control gate (362) overlies the first channel. A second transistor (222) is connected to the first transistor and has a second channel in the substantial shape of a parallelogram with acute angles. The second transistor has a second current path (502) oriented parallel to the first current path. A second control gate (360) overlies the second channel.

Abstract: A semiconductor structure includes an active region; a gate strip overlying the active region; and a metal-oxide-semiconductor (MOS) device. A portion of the gate strip forms a gate of the MOS device. A portion of the active region forms a source/drain region of the MOS device. The semiconductor structure further includes a stressor region over the MOS device; and a stressor-free region inside the stressor region and outside the region over the active region.

Abstract: Photonic power switch and method of controlling current flow in the photonic power switch, the photonic power switch comprising an avalanche photo diode installed on a switch element, the switch element comprising a carrier donor layer and a channel layer. Photons are injected in the avalanche photo diode for generating electrical charge carriers by photoeffect, and the generated charge carriers are accelerated the by an electric field so as to produce an avalanche effect and are injected from the avalanche photo diode into the carrier donor layer of the switch element. A conduction layer built between the donor layer and the channel layer of the switch element is modulated, thereby modulating a current flow between a drain and a source of the power switch through said conduction layer.

Abstract: Shapes and orientations of contacts or other closed contours on an integrated circuit are characterized by calculating Elliptic Fourier descriptors. The descriptors are then used for generating design rules for the integrated circuit and for assessing process capability for the manufacturing of the integrated circuit. Monte Carlo simulation can be performed in conjunction with the elliptic Fourier descriptors.

Abstract: Two configurable systems including: a first configurable system including a first configurable logic die connected to at least one first configurable Input-Output die, and a second configurable system including a second configurable logic die connected to at least one second configurable Input-Output die; wherein the first configurable logic die includes a multiplicity of device layers, and the second configurable logic die includes a multiplicity of device layers; wherein the first configurable logic die size is substantially larger than the second configurable logic die size, and wherein the device layers of the second configurable logic die are substantially the same as a portion of the corresponding device layers of the first configurable logic die.

Abstract: A method of making a semiconductor device includes forming a layer over a substrate, forming a plurality of spaced apart features of imagable material over the layer, forming sidewall spacers on the plurality of features and filling a space between a first sidewall spacer on a first feature and a second sidewall spacer on a second feature with a filler feature. The method also includes removing the sidewall spacers to leave the first feature, the filler feature and the second feature spaced apart from each other, and etching the layer using the first feature, the filler feature and the second feature as a mask.

Abstract: A memory cell has N?6 transistors, in which two are access transistors, at least one pair [say (N?2)/2] are pull-up transistors, and at least another pair [say (N?2)/2] are pull-down transistors. The pull-up and pull-down transistors are all coupled between the two access transistors. Each of the access transistors and the pull-up transistors are the same type, p-type or n-type. Each of the pull-down transistors is the other type, p-type or n-type. The access transistors are floating body devices. The pull-down transistors are non-floating body devices. The pull-up transistors may be floating or non-floating body devices. Various specific implementations and methods of making the memory cell are also detailed.

Abstract: A programmable resistance memory combines multiple cells into a block that includes one or more shared electrodes. The shared electrode configuration provides additional thermal isolation for the active region of each memory cell, thereby reducing the current required to program each memory cell.

Abstract: On embodiment of a contact structure may include a lower insulation layer on a lower substrate, an upper substrate on the lower insulation layer, a groove penetrating the upper substrate to extend into the lower insulation layer, the groove below an interface between the upper substrate and the lower insulation layer, an upper insulation layer in the groove, and a contact plug penetrating the upper insulation layer in the groove to extend into the lower insulation layer.

Abstract: A monolithic microwave integrated circuit structure having a semiconductor substrate structure with a plurality of active devices and a microwave transmission line having an input section, an output section and a interconnecting section electrically interconnecting the active devices on one surface and a metal layer on an opposite surface overlaying the interconnection section and absent from overlaying at least one of the input section and the output section.

Abstract: A semiconductor device has a substrate with a source region and a drain region formed on the substrate. A silicide layer is disposed over the source region and drain region. A first interconnect layer is formed over the silicide layer and includes a first runner connected to the source region and second runner connected to the drain region. A second interconnect layer is formed over the first interconnect layer and includes a third runner connected to the first runner and a fourth runner connected to the second runner. An under bump metallization (UBM) is formed over and electrically connected to the second interconnect layer. A mask is disposed over the substrate with an opening in the mask aligned over the UBM. A conductive bump material is deposited within the opening in the mask. The mask is removed and the conductive bump material is reflowed to form a bump.

Abstract: It is desirable to design and manufacture electronic chips that are resistant to modern reverse engineering techniques. Disclosed is a method and device that allows for the design of chips that are difficult to reverse engineer using modern teardown techniques. The disclosed device uses devices having the same geometry but different voltage levels to create different logic devices. Alternatively, the disclosed uses devices having different geometries and the same operating characteristics. Also disclosed is a method of designing a chip using these devices.

Abstract: A method of forming a memory array includes forming first and second strings of serially-coupled memory cells respectively on first and second sides of a conductive pillar. Forming the first string of memory cells includes forming a first control gate on the first side of the conductive pillar and interposing a first charge trap between the first side of the conductive pillar and the first control gate. Forming the second string of memory cells comprises forming a second control gate on the second side of the conductive pillar and interposing a second charge trap between the second side of the conductive pillar and the second control gate. The first and second charge traps are electrically isolated from each other, and the first and second control gates are electrically isolated from each other.

Abstract: One-time programmable (OTP) Electronically Programmable Read-Only Memories (EPROMs) have been used in a number of applications for many years. One drawback with these OTP EPROMs is that these nonvolatile memories tend to be slow and/or may use a considerable amount of area. Here, however, a bit cell is provided that employs a compact dual cell, which generally includes two OTP cells. These OTP cells are generally arranged in differential configuration to increase speed and are arranged to have a small impact on area.

Abstract: According to one embodiment, there is provided a method of manufacturing a semiconductor device having a buffer circuit. In the method, a plurality of semiconductor elements is formed on a semiconductor substrate. The plurality of semiconductor elements are connected in parallel to each other in the buffer circuit. In the method, driving forces of the formed semiconductor elements is evaluated. In the method, one mask is selected from a plurality of masks based on the evaluating. The plurality of masks are formed in advance to have different wiring mask patterns to cause the numbers of semiconductor elements connected in parallel with each other among the plurality of semiconductor elements of the buffer circuit to be different from each other. In the method, a wiring pattern corresponding to the wiring mask pattern is formed by using the selected one mask.

Abstract: A two terminal ESD protection structure formed by an alternating arrangement of adjacent p-n-p-n-p semiconductor regions provides protection against both positive and negative ESD pulses. When an ESD pulse appears across the two terminals of the ESD protection structure, one of the inherent n-p-n-p thyristors is triggered into a snap-back mode thereby to form a low impedance path to discharge the ESD current. Some embodiments of the ESD protection structure of the present invention have an enhanced current handling capability and are formed by combining a number of standard cells. The standard cells include a corner cell, a center cell and an edge cell which are arranged adjacent each other to form an ESD protection structure which provides for current flow from across many locations therein. Some embodiments of the ESD protection structure of the present invention include a network consisting of a pair of current sources, e.g.

Abstract: A memory array including a plurality of memory cells, a plurality of word lines, a dummy word line, and a plug is provided. Each word line is coupled to corresponding memory cells. A dummy word line is directly adjacent to an outmost word line of the plurality of word lines. The plug is located between the dummy word line and the outmost word line.

Abstract: A method of forming a memory device includes providing a substrate having a surface region, defining a cell region and first and second peripheral regions, sequentially forming a first dielectric material, a first wiring structure for a first array of devices, and a second dielectric material over the surface region, forming an opening region in the first peripheral region, the opening region extending in a portion of at least the first and second dielectric materials to expose portions of the first wiring structure and the substrate, forming a second wiring material that is overlying the second dielectric material and fills the opening region to form a vertical interconnect structure in the first peripheral region, and forming a second wiring structure from the second wiring material for a second array of devices, the first and second wiring structures being separated from each other and electrically connected by the vertical interconnect structure.

Abstract: A plurality of diffused resistors and a plurality of wirings (resistive elements) are alternately disposed along a virtual line, and those diffused resistors and wirings are connected in series by contact vias. In the same wiring layer as that of the wirings, a dummy pattern is formed so as to surround a formation region of the wirings and the diffused resistors. A space between the dummy pattern and the wirings is set in accordance with, for example, a minimum space between wirings in a chip formation portion.

Abstract: An integrated circuit memory device, including a memory circuit and a peripheral circuit, is described which is suitable for low cost manufacturing. The memory circuit and peripheral circuit for the device are implemented in different layers of a stacked structure. The memory circuit layer and the peripheral circuit layer include complementary interconnect surfaces, which upon mating together establish the electrical interconnection between the memory circuit and the peripheral circuit. The memory circuit layer and the peripheral circuit layer can be formed separately using different processes on different substrates in different fabrication lines. This enables the use of independent fabrication process technologies, one arranged for the memory array, and another arranged for the supporting peripheral circuit. The separate circuitry can then be stacked and bonded together.

Abstract: An active matrix substrate 40 according to the present invention includes a conductive film 44 and a wiring 80 for supplying a signal to the conductive film 44, characterized in that the wiring 80 includes a first conductive layer 61 and a second conductive layer 62 having a relatively large line width in comparison with the first conductive layer 61 and laminated so as to cover the first conductive layer 61, and the conductive film 44 is arranged in a matrix pattern, and at least a portion of the conductive film 44 is disposed overlapping the wiring 80.

Abstract: A semiconductor package is disclosed that includes a semiconductor device; a circuit board; and a connection mechanism including a first conductive terminal provided on the semiconductor device, and a second conductive terminal provided on the circuit board side, the connection mechanism electrically connecting the semiconductor device and the circuit board via the first conductive terminal and the second conductive terminal. At least one of the first conductive terminal and the second conductive terminal of the connection mechanism includes one or more carbon nanotubes each having one end thereof fixed to the surface of the at least one of the first conductive terminal and the second conductive terminal, and extending in a direction away from the surface. The first conductive terminal and the second conductive terminal engage each other through the carbon nanotubes.

Abstract: A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations and provides for stitching distally disposed transistors using a lower or intermediate metal layer or a subjacent conductive material. The transistors may be disposed in or adjacent longitudinally arranged word line decoder or other cells and the conductive coupling using the metal or conductive material lowers gate resistance between transistors and avoids RC signal delays.

Abstract: A method for forming an integrated circuit for a non-volatile memory cell transistor is disclosed that includes: forming a layer of discrete storage elements over a substrate in a first region of the substrate and in a second region of the substrate; forming a first layer of dielectric material over the layer of discrete storage elements in the first region and the second region; forming a first layer of barrier work function material over the first layer of dielectric material in the first region and the second region; and removing the first layer of barrier work function material from the second region, the first layer of dielectric material from the second region, and the layer of discrete storage elements from the second region. After the removing, a second layer of barrier work function material is formed over the substrate in the first region and the second region. The second layer of barrier work function material is removed from the first region.

Abstract: A display device and a manufacturing method thereof, include a first thin film transistor including a first control electrode, a first semiconductor disposed on the first control electrode, and a first input electrode and a first output electrode opposite to each other on the first semiconductor; and a second thin film transistor including a second control electrode, a second semiconductor disposed on the second control electrode, and a second input electrode and a second output electrode opposite to each other on the second semiconductor, wherein the first semiconductor includes a first lower semiconductor including polysilicon, and a first upper semiconductor disposed on the first lower semiconductor, the first upper semiconductor including amorphous silicon.

Abstract: Some embodiments include cross-point memory structures. The structures may include a line of first electrode material extending along a first horizontal direction, a multi-sided container of access device materials over the first electrode material, a memory element material within the multi-sided container, and a line of second electrode material over the memory element material and extending along a second horizontal direction that is orthogonal to the first horizontal direction. Some embodiments include methods of forming memory arrays. The methods may include forming a memory cell stack over a first electrode material, and then patterning the first electrode material and the memory cell stack into a first set of spaced lines extending along a first horizontal direction. Spaced lines of second electrode material may be formed over the first set of spaced lines, and may extend along a second horizontal direction that is orthogonal to the first horizontal direction.

Abstract: An integrated circuit created from a cell library of compact cells. The cell library includes cells having a metal trace routed along the boundary of the cells for carrying a power supply voltage. The cells also include another metal trace routed along the interior of the cells for carrying another power supply voltage. A cell pin carrying an input signal or output signal of the cell is located outside of the region between the two power rails. By routing the power supply voltages and cell pins of the cell in this manner, the integrated circuit created from the cell is extremely compact while still complying with various design rules.

Abstract: A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. Each of a number of conductive features within a gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature having a centerline aligned parallel to a first direction. The conductive features respectively form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and second NMOS transistor devices are electrically connected. However, the first PMOS and second NMOS transistor devices are physically separate within the gate electrode level region. The gate electrodes of the second PMOS and first NMOS transistor devices are electrically connected. However, the second PMOS and first NMOS transistor devices are physically separate within the gate electrode level region.

Abstract: An interconnection architecture for multilayer circuits includes metal-insulator transition channels interposed between address leads and each bar in the multilayer circuit. An extrinsic variable transducer selectively transitions the metal-insulator channels between insulating and conducting states to selectively connect and disconnect the bars and the address leads. A method for accessing a programmable crosspoint device within a multilayer crossbar circuit is also provided.

Abstract: A nonvolatile semiconductor memory device includes: a substrate; a stacked body with a plurality of dielectric films and electrode films alternately stacked therein, the stacked body being provided on the substrate and having a step in its end portion for each of the electrode films; an interlayer dielectric film burying the end portion of the stacked body; a plurality of semiconductor pillars extending in the stacking direction of the stacked body and penetrating through a center portion of the stacked body; a charge storage layer provided between one of the electrode films and one of the semiconductor pillars; and a plug buried in the interlayer dielectric film and connected to a portion of each of the electrode films constituting the step, a portion of each of the dielectric films in the center portion having a larger thickness than a portion of each of the dielectric films in the end portion.

Abstract: Semiconductor devices, methods of manufacturing thereof, and methods of arranging circuit components of an integrated circuit are disclosed. In one embodiment, a semiconductor device includes an array of a plurality of devices arranged in a plurality of rows. At least one electrostatic discharge (ESD) protection circuit or a portion thereof is disposed in at least one of the plurality of rows of the array of the plurality of devices.

Abstract: A scalable non-blocking switching network (SN) having switches and intermediate (stages of) conductors that are used to connect a first plurality of conductors to other multiple sets of conductors in a generally unrestricted fashion within respective interconnect resources constraints. The SN can be applied in a wide range of applications, in tandem or hierarchically, to provide a large switch network used in network, routers, and programmable logic circuits. The SN is used to connect a first set of conductors, through the SN, to multiple sets of conductors in a given logic circuit hierarchy whereby the conductors in each of the multiple sets are equivalent or exchangeable, which in term, by construction, makes the first set of conductors equivalent when used in the next level of circuit hierarchy. The SN is scalable for large sized sets of conductors and can be used hierarchically to enable programmable interconnections among large sized circuits.

Abstract: A thin film transistor (TFT) substrate includes first and second TFTs on the same substrate. The first TFT has a feature that a lower conductive layer or a bottom gate electrode layer is provided between the substrate and a first insulating layer while an upper conductive layer or a top gate electrode layer is disposed on a second insulating layer formed on a semiconductor layer which is formed on the first insulating layer. The first conductive layer has first and second areas such that the first area overlaps with the first conductive layer without overlapping with the semiconductor layer while the second area overlaps with the semiconductor layer, and the first area is larger than the second area while the second insulating layer is thinner than the first insulating layer. The second TFT has the same configuration as the first TFT except that the gate electrode layer is eliminated.

Abstract: A semiconductor device includes a first mono-crystallized semiconductor layer; and a second mono-crystallized semiconductor layer; wherein said first and second mono-crystallized semiconductor layers are overlaying one on top of the other, and wherein said first mono-crystallized semiconductor layer comprise repeating memory structure with sub structures defined by etching.

Abstract: A method of making a device includes providing a first device level containing first semiconductor rails separated by first insulating features, forming a sacrificial layer over the first device level, patterning the sacrificial layer and the first semiconductor rails in the first device level to form a plurality of second rails extending in a second direction, wherein the plurality of second rails extend at least partially into the first device level and are separated from each other by rail shaped openings which extend at least partially into the first device level, forming second insulating features between the plurality of second rails, removing the sacrificial layer, and forming second semiconductor rails between the second insulating features in a second device level over the first device level. The first semiconductor rails extend in a first direction. The second semiconductor rails extend in the second direction different from the first direction.

Abstract: Modular dies and modular masks that can be used during the manufacture of semiconductor devices are described. The modular mask can be used repeatedly to make multiple, substantially-similar modular dies. The modular die contains a substrate with an integrated circuit as well as a conductive layer containing a source metal and a gate metal connected respectively to the source and gate of the integrated circuit. The gate metal of the conductive layer is located only in an outer portion of the modular die. The modular die can be made by providing the integrated circuit in a first and second portion of the substrate, providing the conductive layer on both the first and second portions, making a first modular die by patterning the conductive layer on the first portion using the modular mask; moving the modular mask to the second portion and using it to make a second modular die by patterning the conductive layer on the second portion. Thus, fewer mask sets need to be made, improving efficiency and reducing costs.

Abstract: Some embodiments include methods of forming memory arrays. A stack of semiconductor material plates may be patterned to subdivide the plates into pieces. Electrically conductive tiers may be formed along sidewall edges of the pieces. The pieces may then be patterned into an array of wires, with the array having vertical columns and horizontal rows. Individual wires may have first ends joining to the electrically conductive tiers, may have second ends in opposing relation to the first ends, and may have intermediate regions between the first and second ends. Gate material may be formed along the intermediate regions. Memory cell structures may be formed at the second ends of the wires. A plurality of vertically-extending electrical interconnects may be connected to the wires through the memory cell structures, with individual vertically-extending electrical interconnects being along individual columns of the array. Some embodiments include memory arrays incorporated into integrated circuitry.

Abstract: The disclosure describes an antenna protection circuit for use in circuits where Single Event Transients from energetic particles is a concern. The antenna protection circuit may include at least three diodes, connected electrically in series and arranged such that at most all but one of the at least three diodes produce a transient current pulse from an energetic particle. During the transient current pulse event, the remaining diode remains reverse biased thereby sufficiently blocking the transient current pulse and an SET does not occur on the signal node. The antenna protection circuit may be constructed so that no unshorted parasitic p-n junction structure is associated with any of the diodes in the circuit, which would otherwise have to be explicitly included in the at least three diodes.