Abstract: Semiconductor devices comprise at least one integrated circuit layer, at least one conductive trace and an insulative material adjacent at least a portion of the at least one conductive trace. At least one interconnect structure extends through a portion of the at least one conductive trace and a portion of the insulative material, the at least one interconnect structure comprising a transverse cross-sectional dimension through the at least one conductive trace which differs from a transverse cross-sectional dimension through the insulative material. Methods of forming semiconductor devices comprising at least one interconnect structure are also disclosed.

Abstract: A method for fabricating a 3-D monolithic memory device. Silicon-oxynitride (SixOyNz) on amorphous carbon is used an effective, easily removable hard mask with high selectivity to silicon, oxide, and tungsten. A silicon-oxynitride layer is etched using a photoresist layer, and the resulting etched SixOyNz layer is used to etch an amorphous carbon layer. Silicon, oxide, and/or tungsten layers are etched using the amorphous carbon layer. In one implementation, conductive rails of the 3-D monolithic memory device are formed by etching an oxide layer such as silicon dioxide (SiO2) using the patterned amorphous carbon layer as a hard mask. Memory cell diodes are formed as pillars in polysilicon between the conductive rails by etching a polysilicon layer using another patterned amorphous carbon layer as a hard mask. Additional levels of conductive rails and memory cell diodes are formed similarly to build the 3-D monolithic memory device.

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement memory architectures configured to enhance throughput for cross point arrays including memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes arrays that include memory elements being formed BEOL above a FEOL logic layer within a boundary in a plane parallel to a substrate, and array lines. Further, the integrated circuit includes array line decoders disposed in the logic layer within a region located coextensive with the boundary and between the substrate and the arrays. In some embodiments, the disposition of peripheral circuitry, such as the array line decoders, under the arrays can preserve or optimize die efficiency for throughput enhancement.

Abstract: A specially designed mask controls the arrangement of conductive materials that form a source and drain of a transistor. Designing the mask can be costly and time-consuming, which means that the testing of a circuit involving a transistor can also be costly, time consuming and a barrier towards efficient circuit development and testing. Accordingly, the present invention provides a pre-fabricated, general-purpose pattern comprising an array of conductive islands. The pattern is used as a source and a drain terminal for the formation of a thin-film transistor and as a conductive source for the formation of other electrical components upon the array.

Abstract: A method of making a device includes providing a first device level containing first semiconductor rails separated by first insulating features, forming a sacrificial layer over the first device level, patterning the sacrificial layer and the first semiconductor rails in the first device level to form a plurality of second rails extending in a second direction, wherein the plurality of second rails extend at least partially into the first device level and are separated from each other by rail shaped openings which extend at least partially into the first device level, forming second insulating features between the plurality of second rails, removing the sacrificial layer, and forming second semiconductor rails between the second insulating features in a second device level over the first device level. The first semiconductor rails extend in a first direction. The second semiconductor rails extend in the second direction different from the first direction.

Abstract: A symmetrical circuit is disclosed (FIG. 4). The circuit includes a first transistor (220) having a first channel in a substantial shape of a parallelogram (FIG. 5A) with acute angles. The first transistor has a first current path (506) oriented in a first crystal direction (520). A first control gate (362) overlies the first channel. A second transistor (222) is connected to the first transistor and has a second channel in the substantial shape of a parallelogram with acute angles. The second transistor has a second current path (502) oriented parallel to the first current path. A second control gate (360) overlies the second channel.

Abstract: A scalable non-blocking switching network (SN) having switches and intermediate (stages of) conductors that are used to connect a first plurality of conductors to other multiple sets of conductors in a generally unrestricted fashion within respective interconnect resources constraints. The SN can be applied in a wide range of applications, in tandem or hierarchically, to provide a large switch network used in network, routers, and programmable logic circuits. The SN is used to connect a first set of conductors, through the SN, to multiple sets of conductors in a given logic circuit hierarchy whereby the conductors in each of the multiple sets are equivalent or exchangeable, which in term, by construction, makes the first set of conductors equivalent when used in the next level of circuit hierarchy. The SN is scalable for large sized sets of conductors and can be used hierarchically to enable programmable interconnections among large sized circuits.

Abstract: Structures and methods for standard cell layouts having variable rules for spacing of layers to cell boundaries are disclosed. In one embodiment, a first standard cell layout is provided with a conductive layer having at least two portions spaced apart by a minimum spacing distance, the conductive layer having at least one portion spaced from a cell boundary by a first spacing distance of less than half of the minimum spacing distance; a second standard cell disposed adjacent the first standard cell with at least one second portion of the conductive layer in the second cell disposed adjacent the first portion in the first standard cell and spaced apart from a common cell boundary by a second spacing greater than half of the minimum; wherein the sum of the first and second spacings is at least as great as the minimum spacing. A method for forming standard is disclosed.

Abstract: A method of forming a semiconductor integrated circuit, includes providing a first logic cell, a second logic cell and a metallic wiring connected to the first logic cell and a gate electrode of the second logic cell, and providing a third logic cell including a gate electrode connected to the metallic wiring, such that the third logic cell makes no contribution to a logic operation of the semiconductor integrated circuit, in order that an antenna ratio of the first gate electrode to the metallic wiring does not satisfy an antenna criterion, and an antenna ratio of the first gate electrode and the second gate electrode to the metallic wiring satisfies the antenna criterion.

Abstract: A signal routing grid. A first metal layer has wires running in a first direction. A second metal layer, spaced from and substantially parallel to the first metal layer, has wires running in a second direction different to the first direction, such that the wires of the first and second metal layers appear from above or below to form virtual intersections. Vias or contacts are coupled between the first and second metal layers and configured to route signals between the first and second metal layers. Pins are coupled to the first metal layer and configured to provide input signals or receive output signals from a standard cell, the pins being positioned along the wires in the first metal layer so as to be spaced from the virtual intersections.

Abstract: A method of forming a memory array includes forming first and second strings of serially-coupled memory cells respectively on first and second sides of a conductive pillar. Forming the first string of memory cells includes forming a first control gate on the first side of the conductive pillar and interposing a first charge trap between the first side of the conductive pillar and the first control gate. Forming the second string of memory cells comprises forming a second control gate on the second side of the conductive pillar and interposing a second charge trap between the second side of the conductive pillar and the second control gate. The first and second charge traps are electrically isolated from each other, and the first and second control gates are electrically isolated from each other.

Abstract: A flexible display device adapted to prevent a disconnection of pad electrode and a line short-circuit is disclosed. The flexible display device and the manufacturing method thereof according to the present embodiments forms only the barrier film or no layer on the mother substrate in the vicinity of the cut line which divides the mother substrate into the TFT substrate. Even when the mother substrate is pressed using a press machine, cracks or lifts of layers are not generated in the TFT substrate unlike the conventional technology so that a disconnection is not generated in the gate pad electrode or the data pad electrode. Thus, line short-circuits generated as the layers are separated and attached to the TFT substrate can be prevented.

Abstract: The present invention provides providing a substrate, forming a sensor array on the substrate, forming a structured array of uncommitted logic surrounding the sensor array on the substrate, and providing electrical interconnects to the structured array of uncommitted logic, wherein the structured array of uncommitted logic forms functions that support the operation of the sensor array.

Abstract: Provided are a mask layout method and a semiconductor device and a method for fabricating the same. The semiconductor device can include a main pattern, a first dummy pattern, and a second dummy pattern. The main pattern can be disposed on a substrate. The first dummy pattern and the second dummy pattern can be disposed around a side of the main pattern. The first dummy pattern can have an inner open region. The second dummy pattern can be disposed on the inner open region of the first dummy pattern, such that the first dummy pattern surrounds the second dummy pattern.

Abstract: A memory cell device includes a semiconductor nanowire extending, at a first end thereof, from a substrate; the nanowire having a doping profile so as to define a field effect transistor (FET) adjacent the first end, the FET further including a gate electrode at least partially surrounding the nanowire, the doping profile further defining a p-n junction in series with the FET, the p-n junction adjacent a second end of the nanowire; and a phase change material at least partially surrounding the nanowire, at a location corresponding to the p-n junction.

Abstract: Methods and apparatuses to design an Integrated Circuit (IC) with a shielding of wires. In at least one embodiment of the present invention, a shielding mesh of at least two reference voltages (e.g., power and ground) is used to reduce both the capacitive coupling and the inductive coupling in routed signal wires in IC chips. In some embodiments, a type of shielding mesh (e.g., a shielding mesh with a window surrounded by a power ring, or a window with a parser set of shielding wires) is selected to make more routing area available in locally congested areas. In other embodiments, the shielding mesh is used to create or add bypass capacitance. Other embodiments are also disclosed.

Abstract: A method of forming an integrated circuit structure includes providing a substrate including a first active region and a second active region; forming a gate electrode layer over the substrate; and etching the gate electrode layer. The remaining portions of the gate electrode layer include a first gate strip and a second gate strip substantially parallel to each other; and a sacrificial strip unparallel to, and interconnecting, the first gate strip and the second gate strip. The sacrificial strip is between the first active region and the second active region. The method further includes forming a mask layer covering portions of the first gate strip and the second gate strip, wherein the sacrificial strip and portions of the first gate strip and the second gate strip are exposed through an opening in the mask layer; and etching the sacrificial strip and the portions of the first gate strip and the second gate strip through the opening.

Abstract: A semiconductor device comprises a semiconductor substrate that is provided with an integrated circuit; a multi-layered member that is installed in the semiconductor substrate, including a plurality of conductive members and an insulation member; and an external terminal formed on a part of the surface of the multi-layered member. A pair of the conductive members contacts with the upper surface and the lower surface of the insulation member directly under the external terminal, includes a portion where the conductive members are overlapped each other, and are electrically coupled to each other.

Abstract: A scalable non-blocking switching network (SN) having switches and intermediate (stages of) conductors that are used to connect a first plurality of conductors to other multiple sets of conductors in a generally unrestricted fashion within respective interconnect resources constraints. The SN can be applied in a wide range of applications, in tandem or hierarchically, to provide a large switch network used in network, routers, and programmable logic circuits. The SN is used to connect a first set of conductors, through the SN, to multiple sets of conductors in a given logic circuit hierarchy whereby the conductors in each of the multiple sets are equivalent or exchangeable, which in term, by construction, makes the first set of conductors equivalent when used in the next level of circuit hierarchy. The SN is scalable for large sized sets of conductors and can be used hierarchically to enable programmable interconnections among large sized circuits.

Abstract: A semiconductor device includes a first mono-crystallized layer including first transistors, and a first metal layer forming at least a portion of connections between the first transistors; and a second layer including second transistors, the second transistors including mono-crystalline material, the second layer overlying the first metal layer, wherein the first metal layer includes aluminum or copper, and wherein the second layer is less than one micron in thickness and includes logic cells.

Abstract: A storage system and method for forming a storage system that uses punch-through diodes as a steering element in series with a reversible resistivity-switching element is described. The punch-through diode allows bipolar operation of a cross-point memory array. The punch-through diode may have a symmetrical non-linear current/voltage relationship. The punch-through diode has a high current at high bias for selected cells and a low leakage current at low bias for unselected cells. Therefore, it is compatible with bipolar switching in cross-point memory arrays having resistive switching elements. The punch-through diode may be a N+/P?/N+ device or a P+/N?/P+ device.

Abstract: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings comprises: a first columnar semiconductor layer extending in a vertical direction to a substrate; a charge accumulation layer formed around the first columnar semiconductor layer via a first insulation layer; and a first conductive layer formed around the charge accumulation layer via a second insulation layer. Each of the first conductive layers is formed to expand in a two-dimensional manner, and air gaps are formed between the first conductive layers located there above and there below.

Abstract: Memory devices, such as DRAM memory devices, may include one or more metal layers above a local interconnect of the DRAM memory that make contact to lower gate regions of the memory device. As the size of semiconductor components decreases and circuit densities increase, the density of the metal routing in these upper metal layers becomes increasingly difficult to fabricate. By providing additional metal routing in the lower gate regions that may be coupled to the upper metal layers, the spacing requirements of the upper metal layers may be eased, while maintaining the size of the semiconductor device. In addition, the additional metal routing formed in the gate regions of the memory devices may be disposed parallel to other metal contacts in a strapping configuration, thus reducing a resistance of the metal contacts, such as buried digit lines of a DRAM memory cell.

Abstract: An apparatus, system, and method are provided for a vertical two-terminal nanotube device configured to capture and generate energy, to store electrical energy, and to integrate these functions with power management circuitry. The vertical nanotube device can include a column disposed in an anodic oxide material extending from a first distal end of the anodic oxide material to a second distal end of the anodic oxide material. Further, the vertical nanotube device can include a first material disposed within the column, a second material disposed within the column, and a third material disposed between the first material and the second material. The first material fills the first distal end of the column and extends to the second distal end of the column along inner walls of the column. The second material fills the first distal end of the column and extends to the second distal end of the column within the first material.

Abstract: A method for forming three-dimensional multilayer circuit includes forming an area distributed CMOS layer configured to selectively address a set of first vias and a set of second vias. A template is then aligned with the first set of vias and lower crossbar segments are created using the template. The template is then removed, rotated, and aligned with the set of second vias. Upper crossbar segments which attach to the second set of vias are then created.

Abstract: A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles. Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved. Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process. In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations. The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost.

Abstract: Memory cells of a memory device including a variable resistance material have a cavity between the memory cells. Electronic systems include such memory devices. Methods of forming a memory device include providing a cavity between memory cells of the memory device.

Abstract: A non-volatile memory device includes a first electrode, a diode steering element, at least three resistivity switching storage elements, and a second electrode. The diode steering element electrically contacts the first electrode and the at least three resistivity switching storage elements. The second electrode electrically contacts only one of the at least three resistivity switching storage elements.

Abstract: A method for fabricating a display includes providing a first substrate divided into a pixel part and first and second pad parts, forming a gate electrode and a gate line in the pixel part of the first substrate and forming a gate pad line in the first pad part of the first substrate, forming a first insulation film and a semiconductor film over the gate electrode, the gate line and the gate pad line, forming an active pattern over the gate electrode from the semiconductor film with the first insulation film interposed therebetween and forming a contact hole exposing a portion of the gate pad line using a single mask, forming source and drain electrodes in the pixel part, forming a pixel electrode in the pixel part, forming a gate pad electrode electrically connected with the gate pad line via the contact hole, forming a second insulation film over the pixel electrode and the gate pad electrode, exposing a portion of the pixel electrode and at least one portion of the gate pad electrode, and attaching the fir

Abstract: Circuits and methods are provided for facilitating transitioning of a digital circuit from backgate biased standby mode to active mode. The digital circuit includes a semiconductor substrate, multiple n-channel transistors disposed at least partially in one or more p-type wells in the semiconductor substrate, multiple p-channel transistors disposed at least partially in one or more n-type wells in the semiconductor substrate, and a backgate control circuit. The backgate control circuit is electrically coupled to the p-type well(s) and to the n-type well(s) to facilitate transitioning of the multiple n-channel transistors and the multiple p-channel transistors from backgate biased standby mode to active mode by automatically shunting charge from the n-type well(s) to the p-type well(s) until a well voltage threshold is reached indicative of a completed transition of the transistors from backgate biased standby mode to active mode.

Abstract: The present invention provide circuits, methods, and apparatus directed to an integrated circuit having a memory interface that is configurable to have one of a multiple different bus widths. The memory interface has a first set of lines and a second set of lines. The first and second set of lines are arranged such that there are multiple locations at which a via may be placed to connect a line of the first set to a line of the second set. The placement of the vias determines the bus width of the memory interface.

Abstract: A system for terminating a homogenous cell array is disclosed. A preferred embodiment comprises a plurality of homogenous cells arranged in rows and columns to form the homogenous cell array, wherein a first homogenous cell of each column is electrically differently connected than a rest of the homogenous cells of the column.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device including a semiconductor layer with a main surface, a first insulating layer formed on the main surface of the semiconductor layer, a charge storage layer formed on the first insulating layer, a second insulating layer formed on the charge storage layer, and a control gate electrode formed on the second insulating layer. At least one inelastic scattering film that reduces energy of electrons by scattering is contained in at least one of the charge storage layer and second insulating layer.

Abstract: A method for fabricating a semiconductor device includes forming electrode patterns over a substrate, wherein the electrode patterns include a hard mask, forming a passivation layer on the electrode patterns, forming an insulation layer on the passivation layer, filling a space between the electrode patterns, planarizing the insulation layer until shoulder portions of the hard mask are planarized, forming a mask pattern on a resultant structure, and etching a portion of the insulation layer to form a contact hole.

Abstract: Extendable connectors are facilitated. According to an example embodiment, an integrated electrical circuit uses a connector that has first and second connected ends. The connector is unbundled from an initial state in which the first and second connected ends are separated by a first proximate distance and applied in an extended state in which the first and second connected ends are separated by a second distance that is greater than the first proximate distance.

Abstract: A method of forming an active region structure includes preparing a semiconductor substrate including a cell array region and a peripheral circuit region, forming preliminary cell active regions in the cell array region of the semiconductor substrate, and forming cell active regions in the preliminary cell active regions and at least one peripheral active region in the peripheral circuit region of the semiconductor substrate, such that the preliminary cell active regions, the cell active regions, and the at least one peripheral active region are integrally formed with the semiconductor substrate and protrude from the semiconductor substrate.

Abstract: A multi-function core base cell includes a set of functional microcircuits. These microcircuits are used to design a Library of Logic Function Macros. The functional macros consisting of one or more microcircuits have a fixed and complete physical layout similar to a conventional standard cell library macro set. In addition to a core functional macro set, primary input/output buffers and commonly used single and dual port memory blocks are also defined in the library. The library includes all the ASIC synthesis, simulation, and physical design rules.

Abstract: A first via opening is formed to a first conductor and a second via opening is formed to a second conductor. The first and second via openings are formed through insulative material. Then, the first conductor is masked from being exposed through the first via opening and to leave the second conductor outwardly exposed through the second via opening. An antifuse dielectric is formed within the second via opening over the exposed second conductor while the first conductor is masked. Then, the first conductor is unmasked to expose it through the first via opening. Then, conductive material is deposited to within the first via opening in conductive connection with the first conductor to form a conductive interconnect within the first via opening to the first conductor and to within the second via opening over the antifuse dielectric to form an antifuse comprising the second conductor, the antifuse dielectric within the second via opening and the conductive material deposited to within the second via opening.

Abstract: A phase change memory and the method for manufacturing the same are disclosed. The phase change memory includes a word line, a phase change element, a plurality of heating parts, and a plurality of bit lines. The phase change material layer is electrically connected to the word line and the heating parts. Each heating part is electrically connected to a respective bit line.

Abstract: A method is disclosed for defining a dynamic array section to be manufactured on a semiconductor chip. The method includes defining a peripheral boundary of the dynamic array section. The method also includes defining a manufacturing assurance halo outside the boundary of the dynamic array section. The method further includes controlling chip layout features within the manufacturing assurance halo to ensure that manufacturing of conductive features inside the boundary of the dynamic array section is not adversely affected by chip layout features within the manufacturing assurance halo.

Abstract: Method, algorithms, architectures, packages, circuits, and/or approaches for relatively low cost packaged integrated circuits (e.g., ball grid array or BGA packages) are disclosed. For example, a packaged integrated circuit can include a chip with a plurality of bond pads thereon; a plurality of bond pad connectors in electrical communication with the plurality of bond pads; a substrate having a plurality of layers, where at least one of the layers is configured to electrically connect a plurality of bond pad connectors and a plurality of external package connections; and a redistribution layer on the chip, where the redistribution layer is configured to electrically connect at least one of the bond pad connectors and at least one of the bond pads on the chip. Such an approach enables reductions in overall package costs. The RDL may complete an electrical path between one or more substrate traces and the corresponding bond pad(s) to avoid increasing the substrate layer count.

Abstract: A plurality of diffused resistors and a plurality of wirings (resistive elements) are alternately disposed along a virtual line, and those diffused resistors and wirings are connected in series by contact vias. In the same wiring layer as that of the wirings, a dummy pattern is formed so as to surround a formation region of the wirings and the diffused resistors. A space between the dummy pattern and the wirings is set in accordance with, for example, a minimum space between wirings in a chip formation portion.

Abstract: An array with cells that have adjacent similar structures that are displaced from each other across a common cell border in a direction that is not perpendicular to the cell border thus avoiding an across cell border design rule violation between the adjacent similar structures. A method of forming reduced area memory arrays by displacing adjacent similar structures along a common cell border. A method of building arrays using conventional array building software by forming unit pairs with cells that are not identical and are not mirror images or rotated versions of each other.

Abstract: An array with cells that have adjacent similar structures that are displaced from each other across a common cell border in a direction that is not perpendicular to the cell border thus avoiding an across cell border design rule violation between the adjacent similar structures. A method of forming reduced area memory arrays by displacing adjacent similar structures along a common cell border. A method of building arrays using conventional array building software by forming unit pairs with cells that are not identical and are not mirror images or rotated versions of each other.

Abstract: Multi-chip package includes first through Nth semiconductor chips, each of which includes an input/output pad, an input/output driver coupled to the input/output pad, and an internal circuit. Each of the first through Nth semiconductor chips includes an internal pad for coupling the internal input/output driver and the internal circuit. The internal pads of the first through Nth semiconductor chips are coupled to each other such as via a common pad installed at a substrate. The input/output pad of the first semiconductor chip directly receives an input/output signal transmitted via a corresponding pin of the multi-chip package. The second through Nth semiconductor chips indirectly receive the input/output signal via the internal pads coupled to each other. The multi-chip package can improve signal compatibility by maintaining a parasitic load of a pin to at least the level of a single chip, when a signal is transmitted to the pin at high speed.

Abstract: Disclosed are embodiments of an improved integrated circuit switching device that incorporates multiple sets of series connected field effect transistors with each set further connected in parallel between two nodes. The sets are arranged in a linear fashion with each set positioned such that it is in contact with and essentially symmetrical relative to an adjacent set. Arranging the sets in this manner allows adjacent diffusion regions of the same type (i.e., sources or drains) from adjacent sets to be merged. Merging of the diffusion regions provides several benefits, including but not limited to, reducing the device size, reducing the amount of required wiring for the device (i.e., reducing resistance) and reducing side capacitance between the now merged diffusion regions and the substrate. Also disclosed are embodiments of an associated design structure for the device and an associated method of forming the device.

Abstract: A scalable non-blocking switching network (SN) having switches and intermediate (stages of) conductors that are used to connect a first plurality of conductors to other multiple sets of conductors in a generally unrestricted fashion within respective interconnect resources constraints. The SN can be applied in a wide range of applications, in tandem or hierarchically, to provide a large switch network used in network, routers, and programmable logic circuits. The SN is used to connect a first set of conductors, through the SN, to multiple sets of conductors in a given logic circuit hierarchy whereby the conductors in each of the multiple sets are equivalent or exchangeable, which in term, by construction, makes the first set of conductors equivalent when used in the next level of circuit hierarchy. The SN is scalable for large sized sets of conductors and can be used hierarchically to enable programmable interconnections among large sized circuits.

Abstract: Provided are a non-volatile memory device that may expand to a stacked structure and may be more easily highly integrated and an economical method of fabricating the non-volatile memory device. The non-volatile memory device may include at least one semiconductor column. At least one first control gate electrode may be arranged on a first side of the at least one semiconductor column. At least one second control gate electrode may be arranged on a second side of the at least one semiconductor column. A first charge storage layer may be between the at least one first control gate electrode and the at least one semiconductor column. A second charge storage layer may be between the at least one second control gate electrode and the at least one semiconductor column.

Abstract: An integrated circuit 78 is formed of multiple layers of circuits 14, 16 superimposed to produce stacks of circuit blocks 2, 4. Stack control circuitry 18, 20 is associated with the input and output signals from the circuit blocks to direct these to/from the currently active circuit block(s) as appropriate. The superimposed circuit blocks 2, 4 provide redundancy for each other, both for manufacturing defect resistance and for operational redundancy, such as providing multiple modular redundancy in safety critical environments.

Abstract: Support structures for semiconductor devices and methods of manufacturing thereof are disclosed. In some embodiments, the support structures include a plurality of support members that is formed in a substantially annular shape beneath a wire bond region. The central region inside the substantially annular shape of the plurality of support members may be used to route functional conductive lines for making electrical contact to active areas of the semiconductor device. Dummy support structures may optionally be formed between the functional conductive lines. The support structures may be formed in one or more conductive line layers and semiconductive material layers of a semiconductor device. In other embodiments, support members are not formed in an annular shape, and are formed in insulating layers that do not comprise low dielectric constant (k) materials.