Abstract: An integrated circuit includes a substrate having a semiconducting surface (605) and a plurality of standard cells arranged in a plurality of rows including at least a first row (610) and a second row (615) immediately above the first row. The first row (610) include at least a first decap filler cell (602) including a first active area (612) and a field dielectric outside the first active area (612) having a portion with a full field dielectric thickness portion 621 and a portion with a thinned field dielectric (622), and at least a first MOS transistor (618) having a gate electrode (619) on a thick gate dielectric (613) on the first active area (612) connected as a decoupling capacitor.

Abstract: A cell array includes a semiconductor substrate including an active region comprising a first region, a second region, and a transition region, the second region being separated from the first region by the transition region, wherein a top surface of the second region is at a different level than a top surface of the first region. The cell array also includes a plurality of word lines crossing over the first region. The cell array also includes a selection line crossing over the active region, wherein at least a portion of the selection line is located over the transition region.

Abstract: A film thickness prediction method of predicting a film thickness of a second processed layer after planarization includes the steps of: creating first to third actual measurement databases; obtaining a reference film thickness of a second processed layer formed on a region in which no circuit pattern exists; segmenting a first processed layer to be formed on a substrate into grid-like meshes, and obtaining a pattern area ratio occupied by a circuit pattern to be formed on a first processed layer in each mesh and further obtaining a circumferential length of the circuit pattern in each mesh; obtaining an initial thickness of the second processed layer in each mesh; and predicting the film thickness of the second processed layer after planarization from an initial film thickness predicted value and an amount of planarization Hij of the second processed layer in the mesh.

Abstract: Disclosed herein is a method of positioning and placing an integrated circuit on a printed circuit board. The integrated circuit comprises first geometrical elements. The first geometrical elements are of one or more predefined shapes and are located on one or more predefined surfaces of the integrated circuit. The printed circuit board comprises second geometrical elements. The second geometrical elements are shaped to accommodate the first geometrical elements. The first geometrical elements are designed to fit into the second geometrical elements. The first geometrical elements are positioned and placed over the second geometrical elements. The first geometrical elements come in contact with the second geometrical elements at two or more points. The positioning and placement of the first geometrical elements over the second geometrical elements limits displacement of connections of the integrated circuit from the printed circuit board.

Abstract: In the present invention, a method of testing an unpackaged integrated circuit die is disclosed. The die has a plurality of first input/output pads. A serial electrical connection is fabricated in the die between all of the input/output pads of the die which are not of the first plurality (hereinafter: “second plurality”). The second plurality has a start input and an end output. The start input of the second plurality is connected to the output of one selected input buffer of the input pad of the first plurality and the end output of the second plurality is also connected to the input of one selected output pad of the first plurality. The second plurality of input/output pads are tested through selected input pad and selected output pad of the first plurality without electrical probes making contact during the wafer sort. The present invention also relates to an integrated circuit die so fabricated as to facilitate testing.

Abstract: A non-volatile semiconductor storage device includes: a substrate; a control circuit layer provided on the substrate; a support layer provided on the control circuit layer; and a memory cell array layer provided on the support layer. The memory cell array layer includes: a first lamination part having first insulation layers and first conductive layers alternately laminated therein; and a second lamination part provided on either the top or bottom surface of the respective first lamination part and laminated so as to form a second conductive layer between second insulation layers. The control circuit layer includes at least any one of: a row decoder driving word lines provided in the memory cell array layer, and a sense amplifier sensing and amplifying a signal from bit lines provided in the memory cell array layer.

Abstract: A phase change memory device and an associated method of making same are presented. The phase change memory device, includes first wiring lines, second wiring lines, memory cells, and conduction contacts. The first wiring lines are arranged substantially in parallel to each other so that the first wiring lines are grouped into odd and even numbered first wiring lines. The memory cells are coupled to the first and second wiring lines. The conduction contacts coupled to the first wiring lines so that only one conduction contact is coupled to a center of a corresponding odd numbered first wiring line. Also only two corresponding conduction contacts are coupled to opposing edges of a corresponding even numbered first wiring line. Accordingly, the conduction contacts are arranged on the first wiring lines so that conduction contacts are not adjacent to each other with respect to immediately adjacent first wiring lines.

Abstract: In one embodiment, a semiconductor device has a topmost or highest conductive layer with at least one opening. The semiconductor device includes a semiconductor substrate having a cell array region and an interlayer insulating layer covering the substrate having the cell array region. The topmost conductive layer is disposed on the interlayer insulating layer in the cell array region. The topmost conductive layer has at least one opening. A method of fabricating the semiconductor device is also provided. The openings penetrating the topmost metal layer help hydrogen atoms reach the interfaces of gate insulating layers of cell MOS transistors and/or peripheral MOS transistors during a metal alloy process, thereby improve a performance (production yield and/or refresh characteristics) of a memory device.

Abstract: A symmetrical circuit is disclosed (FIG. 4). The circuit includes a first transistor (220) having a first channel in a substantial shape of a parallelogram (FIG. 5A) with acute angles. The first transistor has a first current path (506) oriented in a first crystal direction (520). A first control gate (362) overlies the first channel. A second transistor (222) is connected to the first transistor and has a second channel in the substantial shape of a parallelogram with acute angles. The second transistor has a second current path (502) oriented parallel to the first current path. A second control gate (360) overlies the second channel.

Abstract: Semiconductor devices, methods of manufacturing thereof, and methods of arranging circuit components of an integrated circuit are disclosed. In one embodiment, a semiconductor device includes an array of a plurality of devices arranged in a plurality of rows. At least one radio frequency (RF) circuit or a portion thereof is disposed in at least one of the plurality of rows of the array of the plurality of devices.

Abstract: During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a plurality of NAND strings and a buffer are formed.

Abstract: An integrated circuit system comprising: providing a substrate; forming a main feature using a first non-cross-junction assist feature over the substrate; forming the main feature using a second non-cross-junction assist feature, adjacent a location of the first non-cross-junction feature, over the substrate; and forming an integrated circuit having the substrate with the main feature thereover.

Abstract: Embodiments of the present invention are directed to mixed-scale electronic interfaces, included in integrated circuits and other electronic devices, that provide for dense electrical interconnection between microscale features of a predominantly microscale or submicroscale layer and nanoscale features of a predominantly nanoscale layer. A method is provided for fabricating a nanoscale/microscale interface having a microscale layer and a predominantly nanoscale layer.

Abstract: The present invention is a method for manufacturing a semiconductor apparatus including a chip which is fabricated in large numbers on a wafer and has a plurality of information blocks. In the method, a unique information bit is written in a chip discrimination block of each chip within a shot, which is a segmented region of the wafer, by a fixed pattern method. In addition, an information bit uniquely given to each shot within the wafer is written by a mask shift method. Further, an information bit uniquely given to each wafer is written in a wafer discrimination block of the chip which is fabricated on the wafer by the mask shift method and mask combination method.

Abstract: A semiconductor structure and a method for forming the same. The structure includes (a) a substrate which includes semiconductor devices and (b) a first ILD (inter-level dielectric) layer on top of the substrate. The structure further includes N first actual metal lines in the first ILD layer, N being a positive integer. The N first actual metal lines are electrically connected to the semiconductor devices. The structure further includes first trenches in the first ILD layer. The first trenches are not completely filled with solid materials. If the first trenches are completely filled with first dummy metal lines, then (i) the first dummy metal lines are not electrically connected to any semiconductor device and (ii) the N first actual metal lines and the first dummy metal lines provide an essentially uniform pattern density of metal lines across the first ILD layer.

Abstract: A semiconductor device has a semiconductor substrate that in turn has a top semiconductor layer portion and a major supporting portion under the top semiconductor layer portion. An interconnect layer is over the semiconductor layer. A memory array is in a portion of the top semiconductor layer portion and a portion of the interconnect layer. The memory is erased by removing at least a portion of the major supporting portion and, after the step of removing, applying light to the memory array from a side opposite the interconnect layer. The result is that the memory array receives light from the backside and is erased.

Abstract: A fuse structure, an integrated circuit including the structure, and methods for making the structure and (re)configuring a circuit using the fuse. The fuse structure generally includes (a) a conductive structure with at least two circuit elements electrically coupled thereto, (b) a dielectric layer over the conductive structure, and (c) a first lens over both the first dielectric layer and the conductive structure configured to at least partially focus light onto the conductive structure. The method of making the structure generally includes the steps of (1) forming a conductive structure electrically coupled to first and second circuit elements, (2) forming a dielectric layer thereover, and (3) forming a lens on or over the dielectric layer and over the conductive structure, the lens being configured to at least partially focus light onto the conductive structure.

Abstract: A CCD containing circuit and method for making the same. The circuit includes a CCD array and a protection circuit. The CCD array is constructed on an integrated circuit substrate and includes a plurality of gate electrodes that are insulated from the substrate by an insulating layer. The gate electrodes are connected to a conductor bonded to the substrate. The protection circuit is also constructed on the substrate. The protection circuit is connected to the conductor and to the substrate and protects the CCD array from both negative and positive voltage swings generated by electrostatic discharge events and the like. The protection circuit and the CCD can be constructed in the same integrated circuit fabrication process.

Abstract: Methods for manufacturing a semiconductor device are provided that reduces the thickness of an oxide layer formed on a polysilicon layer for bit line contacts. A reduced thickness oxide layer can prevent short circuits between adjoining bit lines. A reduced thickness oxide layer can also eliminate the need for overetching in a subsequent etching process, thereby preventing loss of an isolation layer in a peripheral region.

Abstract: A nonvolatile memory device includes: a first interconnection extending in a first direction; a second interconnection extending in a second direction nonparallel to the first direction; and a memory layer placed between the first interconnection and the second interconnection and reversibly transitioning between a first state and a second state by a current supplied via the first interconnection and the second interconnection. A cross section parallel to the first and the second direction of the memory layer decreases toward the second interconnection.

Abstract: A cell based design layout of an application specific integrated circuit (ASIC) having a function has reduceddecreased power leakage because functionally unconnected additional cells or spare cells of the integrated design layout are unconnected to the power supplies Vdd and Vss.

Abstract: Methods of fabricating integrated circuit devices are provided using composite spacer formation processes. A composite spacer structure is used to pattern and etch the layer stack when forming select features of the devices. A composite storage structure includes a first spacer formed from a first layer of spacer material and second and third spacers formed from a second layer of spacer material. The process is suitable for making devices with line and space sizes at less then the minimum resolvable feature size of the photolithographic processes being used. Moreover, equal line and space sizes at less than the minimum feature size are possible. In one embodiment, an array of dual control gate non-volatile flash memory storage elements is formed using composite spacer structures. When forming the active areas of the substrate, with overlying strips of a layer stack and isolation regions therebetween, a composite spacer structure facilitates equal lengths of the strips and isolation regions therebetween.

Abstract: A phase change memory device resistant to stack pattern collapse is presented. The phase change memory device includes a silicon substrate, switching elements, heaters, stack patterns, bit lines and word lines. The silicon substrate has a plurality of active areas. The switching elements are connected to the active areas. The heaters are connected to the switching elements. The stack patterns are connected to the heaters. The bit lines are connected to the stack patterns. The word lines are connected to the active areas of the silicon substrate.

Abstract: A phase change memory device resistant to stack pattern collapse is presented. The phase change memory device includes a silicon substrate, switching elements, heaters, stack patterns, bit lines and word lines. The silicon substrate has a plurality of active areas. The switching elements are connected to the active areas. The heaters are connected to the switching elements. The stack patterns are connected to the heaters. The bit lines are connected to the stack patterns. The word lines are connected to the active areas of the silicon substrate.

Abstract: A method of fabricating a resistance variable device includes forming selection devices on a substrate, forming a conductive layer on the selection devices, patterning the conductive layer in a first direction to form conductive patterns spaced apart from each other in the first direction and connecting a pair of adjacent selection devices to each other in the first direction, forming a resistance-variable-material-layer on the conductive patterns, and patterning the resistance-variable-material-layer and the conductive patterns in a second direction to form rows of resistance-variable material extending in the second direction and to form electrodes spaced apart from one another, such that each electrode corresponds to a separate selection device.

Abstract: A method of manufacturing at least one NAND-coupled semiconductor component is disclosed. A layer structure is formed on or above a semiconductor substrate. The layer structure is patterned to expose at least one region to be doped. The exposed region is doped and annealed. The patterned layer structure is at least partially removed. Replacing material is formed in the region in which the patterned layer structure has been removed, thereby forming the at least one NAND-coupled semiconductor component.

Abstract: Provided are semiconductor integrated circuit (IC) devices including gate patterns having a step difference therebetween and a connection line interposed between the gate patterns. The semiconductor IC device includes a semiconductor substrate including a peripheral active region, a cell active region, and a device isolation layer. Cell gate patterns are disposed on the cell active region and the device isolation layer. A peripheral gate pattern is disposed on the peripheral active region. A cell electrical node is disposed on the cell active region adjacent to the cell gate patterns. Peripheral electrical nodes are disposed on the peripheral active region adjacent to the peripheral gate pattern. Connection lines are disposed on the cell gate patterns disposed on the device isolation layer. The connection lines are connected between the cell gate patterns and the peripheral gate pattern.

Abstract: A method for preventing arcing during deep via plasma etching is provided. The method comprises forming a first patterned set of parallel conductive lines over a substrate and forming a plurality of semiconductor pillars on the first patterned set of parallel conductive lines and extending therefrom, wherein a pillar comprises a first barrier layer, an antifuse layer, a diode, and a second barrier layer, wherein an electric current flows through the diode upon a breakdown of the antifuse layer. The method further comprises depositing a dielectric between the plurality of semiconductor pillars, and plasma etching a deep via recess through the dielectric and through the underlying layer after the steps of forming a plurality of semiconductor pillars and depositing a dielectric. An embodiment of the invention comprises a memory array device.

Abstract: A method of making a semiconductor device includes forming at least one device layer over a substrate, forming at least two spaced apart features over the at least one device layer, forming sidewall spacers on the at least two features, selectively removing the spaced apart features, filling a space between a first sidewall spacer and a second sidewall spacer with a filler feature, selectively removing the sidewall spacers to leave a plurality of the filler features spaced apart from each other, and etching the at least one device layer using the filler feature as a mask.

Abstract: A method of manufacturing a display substrate includes forming a plurality of thin film transistors (TFTs) on a first substrate in a matrix, forming a plurality of pixel electrodes connected to the TFTs, forming a connecting pad to receive a common voltage, forming an organic pattern on the connecting pad, depositing an inorganic alignment layer covering the organic pattern on the first substrate, and removing the organic pattern and the inorganic alignment layer remaining on the organic pattern.

Abstract: A method for fabricating non-volatile storage having individually controllable shield plates between storage elements. The shield plates are formed by depositing a conductive material such as doped polysilicon between storage elements and their associated word lines, and providing contacts for the shield plates. The shield plates reduce electromagnetic coupling between floating gates of the storage elements, and can be used to optimize programming, read and erase operations. In one approach, the shield plates provide a field induced conductivity between storage elements in a NAND string during a sense operation so that source/drain implants are not needed in the substrate. In some control schemes, alternating high and low voltages are applied to the shield plates. In other control schemes, a common voltage is applied to the shield plates.

Abstract: A method of making a semiconductor device includes forming at least one device layer over a substrate, forming a plurality of spaced apart first features over the device layer, where each three adjacent first features form an equilateral triangle, forming sidewall spacers on the first features, filling a space between the sidewall spacers with a plurality of filler features, selectively removing the sidewall spacers, and etching the at least one device layer using at least the plurality of filler features as a mask. A device contains a plurality of bottom electrodes located over a substrate, a plurality of spaced apart pillars over the plurality of bottom electrodes, and a plurality of upper electrodes contacting the plurality of pillars. Each three adjacent pillars form an equilateral triangle, and each pillar comprises a semiconductor device.

Abstract: A memory circuit arrangement and fabrication method thereof are presented in which the parts of the memory circuit arrangement are situated on two different substrates. An integrated memory cell array is situated on one substrate. An integrated control circuit that controls access to the memory cells is situated on the other (logic circuit) substrate. The control circuit controls sequences when reading, writing or erasing content of a memory cell. The logic circuit substrate also contains a CPU and encryption coprocessor. The memory circuit contains a sense amplifier, with the aid of which the memory state of a memory cell can be determined, and a decoding circuit that selects a word or bit line.

Abstract: An active matrix substrate 40 according to the present invention includes a conductive film 44 and a wiring 80 for supplying a signal to the conductive film 44, characterized in that the wiring 80 includes a first conductive layer 61 and a second conductive layer 62 having a relatively large line width in comparison with the first conductive layer 61 and laminated so as to cover the first conductive layer 61, and the conductive film 44 is arranged in a matrix pattern, and at least a portion of the conductive film 44 is disposed overlapping the wiring 80.

Abstract: Some embodiments of the invention provide configurable integrated circuits (“IC's”) with configurable node arrays. In some embodiments, the configurable node array includes numerous (e.g., 50, 100, etc.) configurable nodes arranged in several rows and columns. This array also includes several direct offset connections, where each particular direct offset connection connects two nodes that are neither in the same column nor in the same row in the array. In some embodiments, at least some direct offset connections connect pairs of nodes that are separated in the array by more than one row and at least one column, or by more than one column and at least one row. Some embodiments establish a direct connection by (1) a set of wire segments that traverse through a set of the IC's wiring layers, and (2) a set of vias when two or more wiring layers are involved. In some embodiments, some of the direct connections have intervening circuits (e.g.

Abstract: A method is disclosed to form an upward-pointing p-i-n diode formed of deposited silicon, germanium, or silicon-germanium. The diode has a bottom heavily doped p-type region, a middle intrinsic or lightly doped region, and a top heavily doped n-type region. The top heavily doped p-type region is doped with arsenic, and the semiconductor material of the diode is crystallized in contact with an appropriate silicide, germanide, or silicide-germanide. A large array of such upward-pointing diodes can be formed with excellent uniformity of current across the array when a voltage above the turn-on voltage of the diodes is applied. This diode is advantageously used in a monolithic three dimensional memory array.

Abstract: In one embodiment of the present invention, a method for connecting a plurality of bit lines to sense circuitry comprises providing a plurality of bit lines extending from a memory array in a first metal layer. The plurality of bit lines are separated from each other by an average spacing x in a first region of the first metal layer. The method further comprises elevating a portion of the plurality of bit lines into a second metal layer overlying the first metal layer. The elevated bit lines are separated from each other by an average spacing y in the second metal layer, with y >x. The method further comprises extending a portion of the plurality of bit lines into a second region of the first metal layer. The extended bit lines are separated from each other by an average spacing z in the second region of the first metal layer, with z>x. The method further comprises connecting a bit line in the second metal layer and a bit line in the first metal layer to the sense circuitry.

Abstract: A cross-point semiconductor memory device includes: a plurality of first wirings extending in a first direction; a plurality of second wirings positioned on a layer different from the first wirings to extend in a second direction different from the first direction; and memory parts provided in overlap areas of the first wirings and the second wirings, wherein the odd-numbered first wirings and the even-numbered first wirings are arranged on different insulating interlayers in an up-down direction.

Abstract: A method for fabricating a 3-D monolithic memory device. Silicon-oxynitride (SixOyNz) on amorphous carbon is used an effective, easily removable hard mask with high selectivity to silicon, oxide, and tungsten. A silicon-oxynitride layer is etched using a photoresist layer, and the resulting etched SixOyNz layer is used to etch an amorphous carbon layer. Silicon, oxide, and/or tungsten layers are etched using the amorphous carbon layer. In one implementation, conductive rails of the 3-D monolithic memory device are formed by etching an oxide layer such as silicon dioxide (SiO2) using the patterned amorphous carbon layer as a hard mask. Memory cell diodes are formed as pillars in polysilicon between the conductive rails by etching a polysilicon layer using another patterned amorphous carbon layer as a hard mask. Additional levels of conductive rails and memory cell diodes are formed similarly to build the 3-D monolithic memory device.

Abstract: A method of making a semiconductor device includes forming at least one device layer over a substrate, forming at least two spaced apart features over the at least one device layer, forming sidewall spacers on the at least two features, filling a space between a first sidewall spacer on a first feature and a second sidewall spacer on a second feature with a filler feature, selectively removing the sidewall spacers to leave the first feature, the filler feature and the second feature spaced apart from each other, and etching the at least one device layer using the first feature, the filler feature and the second feature as a mask.

Abstract: A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced.

Abstract: Areas of a semiconductor substrate where semiconductor devices are not to be formed are filled in with dummy active areas. Whole dummy active areas are formed in areas of the semiconductor substrate where semiconductor devices are not to be formed, and partial dummy active areas are formed in areas of the semiconductor substrate where semiconductor devices are not to be formed, but where whole dummy active areas can not be accommodated. The dummy active areas are staggered so as to provide uniform parasitic capacitive coupling to overlying leads regardless of the placement of the leads. The dummy active areas are substantially evenly separated from one another by dividers. The dummy active areas and dividers are formed concurrently with formation of semiconductor devices in non-dummy active areas. The dummy active areas mitigate yield loss by, among other things, providing more uniformity across the substrate, at least with regard to parasitic capacitances and stress and subsequent processing.

Abstract: A semiconductor memory device includes a semiconductor substrate; a memory cell array on the semiconductor substrate, the memory cell array comprising a plurality of memory cells capable of electrically storing data; a sense amplifier configured to detect the data stored in at least one of the memory cells; a cell source driver electrically connected to source side terminals of the memory cells and configured to supply a source potential to at least one of the source side terminals of the memory cells; a first wiring configured to electrically connect between at least one of the source side terminals of the memory cells and the cell source driver; and a second wiring formed in a same wiring layer as the first wiring, the second wiring being insulated from the first wiring and being electrically connected to the sense amplifier, wherein the first wiring and the second wiring have a plurality of through holes provided at a predetermined interval.

Abstract: A method of manufacturing semiconductor memory device comprises forming a first wiring layer and a memory cell layer above a semiconductor substrate; forming a plurality of first trenches extending in a first direction in the first wiring layer and the memory cell layer, thereby forming first wirings and separating the memory cell layer; burying a first interlayer film in the first trenches to form a stacked body; forming a second wiring layer above the stacked body; forming a plurality of second trenches, extending in a second direction intersecting the first direction and reaching an upper surface of the first interlayer film in depth, in the first stacked body with the second wiring layer formed thereabove, thereby forming second wirings; removing the first interlayer film isotropically; and digging the second trenches down to an upper surface of the first wirings, thereby forming memory cells.

Abstract: A diode for alternating current (DIAC) electrostatic discharge (ESD) protection circuit is formed in a silicon germanium (SiGe) hetrojunction bipolar transistor (HBT) process that utilizes a very thin collector region. ESD protection for a pair of to-be-protected pads is provided by utilizing the base structures and the emitter structures of the SiGe transistors.

Abstract: Method for making a coreless packaging substrate are disclosed in the present invention. The coreless packaging substrate is made by first providing a metal adhesion layer having a melting point lower than that of the substrate, and removing a core board connected with the substrate therefrom through melting the metal adhesion layer. In addition, the disclosed packaging substrate further includes a circuit built-up structure of which has the electrical pads embedded under a surface. The disclosed packaging substrate can achieve the purposes of reducing the thickness, increasing circuit layout density, and facilitating the manufacturing of the substrate.

Abstract: The invention includes methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates. In one implementation, a method of forming a field effect transistor includes forming masking material over semiconductive material of a substrate. A trench is formed through the masking material and into the semiconductive material. Gate dielectric material is formed within the trench in the semiconductive material. Gate material is deposited within the trench in the masking material and within the trench in the semiconductive material over the gate dielectric material. Source/drain regions are formed. Other aspects and implementations are contemplated.

Abstract: Systems and arrangements to interconnect cells and structures within cells of an integrated circuit to enhance cell density are disclosed. Embodiments comprise an adjusted polysilicon gate pitch to metal wire pitch relationship to improve area scalars while increasing ACLV tolerance with a fixed polysilicon gate pitch. In some embodiments, the wire pitch for at least one metallization layer is adjusted to match the pitch for the polysilicon gate. In one embodiment, the next to the lowest metallization layer running in the same orientation as the polysilicon gate, utilized to access the input or output of the interconnected cell structures is relaxed to match the minimum contacted gate pitch and the metal is aligned above each polysilicon gate. In another embodiment, the polysilicon gate pitch may be relaxed to attain a smaller lowest common multiple with the wire pitch for an integrated circuit to reduce the minimum step off.

Abstract: In various embodiments, an adder circuit includes a plurality of transistors, all of the transistors being of a single type selected from the group consisting of NMOS transistors and PMOS transistors, and dissipates no more power than an equivalent CMOS circuit.

Abstract: A method for fabricating a semiconductor device includes forming buried bit lines separated from each other by a trench in a substrate, forming a plurality of first pillar holes that expose a top surface of the substrate, forming first active pillars buried in the first pillar holes, forming a gate conductive layer over entire surface of a resultant structure including the first active pillars, forming a gate electrode by etching the gate conducting layer to cover the first active pillars, forming a plurality of second pillar holes that expose the first active pillars by partially etching the gate electrode, and forming second active pillars buried in the second pillar holes and connected to the first active pillars.