Abstract: An insulated gate bipolar transistor according to an embodiment includes a first conductive type collector ion implantation area in a substrate; a second conductive type buffer layer, including a first segment buffer layer and a second segment buffer layer, on the first conductive collector ion implantation area; a first conductive type base area on the second conductive type buffer layer; a gate on the substrate at a side of the first conductive type base area; a second conductive type emitter ion implantation area in the first conductive type base area; an insulating layer on the gate; an emitter electrode electrically connected to the second conductive type emitter ion implantation area; and a collector electrode electrically connected to the first conductive collector ion implantation area.

Abstract: A power electronic device is integrated on a semiconductor substrate of a first type of conductivity. The device includes a plurality of elemental units, and each elemental unit includes a body region of a second type of conductivity which is realized on a semiconductor layer of the first type of conductivity formed on the semiconductor substrate, and a column region of the first type of conductivity which is realized in said semiconductor layer below the body region. The semiconductor layer includes multiple semiconductor layers which overlap each other. The resistivity of each layer is different from that of the other layers. The column region includes a plurality of doped sub-regions, each realized in one of the semiconductor layers. The amount of charge of each doped sub-region balances the amount of charge of the corresponding semiconductor layer in which each doped sub-region is realized.

Abstract: An integrated circuit including a resistive memory element and a method of manufacturing the integrated circuit are described. The method of manufacturing the integrated circuit includes depositing a switching layer material and intentionally forming inhomogeneously distributed defects within the switching layer material to increase a number of switching cycles of the resistive memory element. The resistive memory element includes a switching layer that selectively switches between a low resistance state and a high resistance state. The switching layer contains intentionally formed defects that increase the number of switching cycles of the switching layer.

Abstract: A starting wafer for high voltage semiconductor devices is formed by implanting arsenic into the top surface of a p type silicon substrate wafer to a depth of about 0.1 micron. A N type non-graded epitaxial layer is then grown atop the substrate without any diffusion step so that the arsenic is not intentionally driven. Device junction are then diffused into the epitaxially grown layer.

Abstract: An electrostatic discharge (ESD) device and method is provided. The ESD device can comprise a substrate doped to a first conductivity type, an epitaxial region doped to the second conductivity type, and a first well doped to the first conductivity type disposed in the substrate. The first well can comprise a first region doped to the first conductivity type, a second region doped to a second conductivity type, and a first isolation region disposed between the first region and the second region. The ESD device can also comprise a second well doped to a second conductivity type disposed in the substrate adjacent to the first well, where the second well can comprise a third region doped to the first conductivity type, a fourth region doped to the second conductivity type, and a second isolation region disposed between the third region and the fourth region.

Abstract: A semiconductor device and/or a method for fabricating a semiconductor device (e.g. fabricating an LIGBT) that may minimize occurrences of latch-up due to increases of hole current. A semiconductor device and/or a method of fabricating a semiconductor device that may prevent and/or eliminate latch-up due to operation of a parasitic thyrister without significantly deteriorating performances of significant parameters considered when fabricating a high voltage power control device.

Abstract: A semiconductor device and a method of forming the semiconductor device include a substrate and an n drift layer on the substrate with an insulator film placed between them. A trench is provided in a section between a p base region and an n buffer layer on the surface layer of the n drift layer. Moreover, the distance between the bottom of the trench and the insulator film on the substrate is 1 ?m or more and 75% or less than the thickness of the n drift layer. This reduces the ON-state Voltage Drop and enhances the device breakdown voltage and the latch up current in a lateral IGBT or a lateral MOSFET.

Abstract: A semiconductor subassembly is provided for use in a switching module of an inverter circuit for a high power, alternating current motor application. The semiconductor subassembly includes a wafer having first and second opposed metallized faces; a semiconductor switching device electrically coupled to the first metallized face of the wafer and having at least one electrode region; and an interconnect bonded to the semiconductor switching device. The interconnect includes a first metal layer bonded to the at least one electrode region of the semiconductor switching device, a ceramic layer bonded to the first metal layer, the ceramic layer defining a via for accessing the first metal layer, a second metal layer bonded to the ceramic layer, and a conducting substance disposed in the via of the ceramic layer to electrically couple the first metal layer to the second metal layer.

Abstract: The fabrication of a semiconductor component having a semiconductor body in which is arranged a very thin dielectric layer having sections which run in the vertical direction and which extend very deeply into the semiconductor body is disclosed. In one method a trench is formed in a drift zone region proceeding from the front side of a semiconductor body, a sacrificial layer is produced on at least a portion of the sidewalls of the trench and at least a portion of the trench is filled with a semiconductor material which is chosen such that the quotient of the net dopant charge of the semiconductor material in the trench and the total area of the sacrificial layer on the sidewalls of the trench between the semiconductor material and the drift zone region is less than the breakdown charge of the semiconductor material, and the sacrificial layer is replaced with a dielectric.

Abstract: One aspect of the present subject matter relates to a memory cell, or more specifically, to a scalable GLTRAM cell that provides DRAM-like density and SRAM-like performance. According to various embodiments, the memory cell includes an access transistor and a gated, lateral thyristor integrally formed above the access transistor. The access transistor has a drain region, a raised source region, and a gate. The thyristor has a first end that is formed with the raised source region of the access transistor. In various embodiments, the lateral thyristor is fabricated using a metal-induced lateral crystallization technique (MILC) adopted for thin-film-transistor (TFT) technology. In various embodiments, the stacked lateral thyristor is integrated by raising the source region of the access transistor using a selective epitaxy process for raised source-drain technology. Other aspects are provided herein.

Abstract: A semiconductor fuse box includes a fuse structure and a protective structure disposed between the fuse structure and an integrated circuit structure. The protective structure has at least one irregular side surface. The protective structure (which may also include a pad formed there-under) extends beyond a bottom of the fuse structure. Such an irregular side surface and such an extension of the protective structure minimize propagation of damaging energy to the adjacent integrated circuit structure when a laser beam is directed to the fuse structure.

Abstract: A semiconductor component comprising a monocrystalline semiconductor body, and to a method for producing the same is disclosed. In one embodiment, the semiconductor body has a semiconductor component structure with regions of a porous-mono crystalline semiconductor.

Abstract: A method is provided for fabricating a memory device. A semiconductor substrate is provided which includes a first well region having a first conductivity type, a second well region having the first conductivity type, a first gate structure overlying the first well region and the second gate structure overlying the second well region. An insulating material layer is conformally deposited overlying exposed portions of the semiconductor substrate. Photosensitive material is provided over a portion of the insulating material layer which overlies a portion of the second well region. The photosensitive material exposes portions of the insulating material layer. The exposed portions of the insulating material layer are anisotropically etched to provide a sidewall spacer adjacent a first sidewall of the second gate structure, and an insulating spacer block formed overlying a portion of the second gate structure and adjacent a second sidewall of the second gate structure.

Abstract: A thin film transistor including a gate, a gate insulating layer, a semiconductor layer and a source/drain is provided. The gate is disposed over a substrate, wherein the gate comprises at least one molybdenum-niobium alloy nitride layer. The gate insulating layer is formed over the substrate to cover the gate. The semiconductor layer is disposed over the gate insulating layer above the gate. The source/drain is disposed over the semiconductor layer.

Abstract: A method for manufacturing a semiconductor device according to the present invention has a step of forming a plurality of MOSFETs each having a channel of a first conductivity type in a stripe on the first major surface of a wafer; a step of implanting an impurity of a first conductivity type into the second major surface of the wafer, and performing a laser annealing treatment in a stripe leaving equidistant gaps, to form a buffer layer that has been activated in a stripe; a step of implanting an impurity of a second conductivity type into the second major surface of the substrate after forming the buffer layer, and performing a laser annealing treatment on the entire surface of the second major surface, to form a collector layer, and to activate the buffer layer; and a step of forming an emitter electrode on the first major surface, and forming a collector electrode on the second major surface.

Abstract: A insulated gate bipolar transistors (IGBT) having an enhanced modulation layer provides reduced on-state power dissipation and better conductivity modulation than conventional devices. The IGBT includes an enhanced modulation layer disposed within a portion of the n? doped drift layer, in a n-type device, or p? doped drift layer, in a p-type device. The enhanced modulation layer contains a higher carrier concentration than the n? or p? doped drift layer. If the IGBT device is in an on state, the enhanced modulation layer decreases a size of a depletion region formed around the p well body region or n well body region. In a n-type enhanced modulation layer IGBT, electrons, traveling from the n+ region towards the emitter, are spread laterally and uniformly in the n? doped drift layer. In a p-type enhanced modulation layer IGBT, holes, traveling from the p+ region towards the emitter, are spread laterally and uniformly in the p? doped drift layer.

Abstract: A drift diffusion layer of a low concentration is formed so as to surround a collector buffer layer having a relatively high concentration including a high-concentration collector diffusion layer in a plane structure. Thereby, current crowding in corner portions of the high-concentration collector diffusion layer is suppressed while maintaining a short turnoff time, and the improvement of breakdown voltage at on-time is realized.

Abstract: In a semiconductor device of the present invention, a first base region 16 is extended to a part under a gate electrode 7 while having a vertical concentration profile of an impurity that increases from the surface of a semiconductor layer 3 and becomes maximum under an emitter region 5, and the length in the lateral direction from a point where the impurity concentration becomes maximum located under an end of the gate electrode 7 to the boundary with a second base region is is not smaller than the length in the vertical direction from the point where the impurity concentration becomes maximum to the boundary with the second base region 15.

Abstract: An electrostatic discharge (ESD) protection device and a fabrication method thereof are provided. The ESD protection device with an embedded high-voltage P type SCR (EHVPSCR) structure of the present invention is employed to guide the ESD current/voltage to a system voltage trace VDD via a pad.

Abstract: A semiconductor device includes a body region, a drift region having a first part and a second part, and a trench gate electrode. The body region is disposed on the drift region. The first and second parts extend in an extending direction so that the second part is adjacent to the first part. The trench gate electrode penetrates the body region and reaches the drift region so that the trench gate electrode faces the body region and the drift region through an insulation layer. The trench gate electrode extends in a direction crossing with the extending direction of the first and second parts. The first part includes a portion near the trench gate electrode, which has an impurity concentration equal to or lower than that of the body region.

Abstract: An electrostatic discharge protection device, an electrostatic discharge protection structure, and a manufacturing process of the device are provided. The electrostatic discharge protection device includes at least four doping regions, wherein two adjacent regions are of different types. The electrostatic discharge protection structure includes an electrostatic discharge bus, a plurality of first electrostatic discharge protection devices connecting to the gates of the display transistors and the electrostatic discharge bus, a plurality of second electrostatic discharge protection devices connecting to the source/drain of the transistors and the electrostatic discharge bus, and a plurality of third electrostatic discharge protection devices connecting to the input/output terminals of the drive circuit of the display and the electrostatic discharge bus.

Abstract: A resurf region of a second conductivity type and a base region of a first conductivity type adjacent to each other are formed in surface portions of a semiconductor substrate of the first conductivity type. An emitter region of the second conductivity type is formed in the base region to be spaced from the resurf region. A gate insulating film is formed to cover a portion of the base region disposed between the emitter region and the resurf region, and a gate electrode is formed on the gate insulating film. A top semiconductor layer of the first conductivity type electrically connected to the base region is formed in a surface portion of the resurf region. A collector region of the first conductivity type is formed in a surface portion of the resurf region to be spaced from the top semiconductor layer. The collector region and the top semiconductor layer have substantially the same impurity concentration and are disposed at substantially the same depth.

Abstract: A thyristor-based semiconductor device includes a filled trench separating and electrically insulating adjacent thyristor control ports. According to an example embodiment of the present invention, the filled trench is formed in a substrate adjacent to at least one thyristor body region. The filled trench includes a conductive filler material, an insulative material formed on the conductive filler material and at least two laterally-adjacent thyristor control ports separated from one another by the conductive filler material and the insulative material. One of the control ports is adapted for capacitively coupling to the thyristor body region for controlling current in the thyristor. With this approach, two or more control ports can be formed in a single filled trench and electrically isolated by the conductive filler material/insulative material combination.

Abstract: A method for integration is disclosed herein. The method includes forming an N-type double drain (NDD) layer, and fabricating at least one transistor from a controller circuitry and a transistor switch on a single chip. The controller circuitry is operable for controlling the transistor switch.

Abstract: A semiconductor device includes a thyristor configured to be formed through sequential joining of a first region of a first conductivity type, a second region of a second conductivity type opposite to the first conductivity type, a third region of the first conductivity type, and a fourth region of the second conductivity type, and have a gate formed over the third region. The first to fourth regions are formed in a silicon germanium region or germanium region.

Abstract: In accordance with an embodiment of the invention, a superjunction semiconductor device includes an active region and a termination region surrounding the active region. A central vertical axis of a boundary column of a second conductivity type material defines the boundary between the active region and the termination region. The active and termination regions include columns of first and second conductivity type material alternately arranged along a horizontal direction in a semiconductor region having top and bottom surfaces. At least one of the columns of the first conductivity type material in the termination region has a different width than a width of the columns of the first conductivity type material in the active region.

Abstract: In a method of fabricating a fin field effect transistor having a plurality of protruding channels, the fin field effect transistor is formed by forming a dummy gate pattern on a first hard mask pattern and a first insulating layer on a semiconductor substrate having an active region pattern, forming a source and drain region in a portion of the active region pattern, forming a plurality of vertically protruding channels between the source and drain region, forming a gate dielectric layer on the active region pattern having the plurality of protruding channels, and forming a gate electrode on the gate dielectric layer.

Abstract: In a low voltage ESD protection device, an extra control electrode is created by not connecting the n+ drain and p+ emitter regions of the LVTSCR, and controlling the control electrode by means of a diode connected NMOS.

Abstract: In a method of processing a semiconductor device, a silicide-blocking layer may be formed over a semiconductor material. After defining the silicide-blocking layer, impurities may be implanted into portions of the semiconductor material as defined by the silicide-blocking layer. After the implant, silicide may be formed in a surface region of the semiconductor material as permitted by the silicide-blocking layer. Regions of the impurity implant may comprise boundaries that are related to the outline of the silicide formed thereover. In a further embodiment, the implant may define a base region to a thyristor device. The implant may be performed with an angle of incidence to extend portions of the base region beneath a peripheral edge of the blocking mask. Next, an anode-emitter region may be formed using an implant of a substantially orthogonal angle of incidence and self-aligned to the mask.

Abstract: A core process is described for the manufacture of a Schottky, MOSFET or Accufet, using a plurality of identical manufacturing steps, including spaced trenches, in a single production line, with the device type to be produced being defined at an implant and diffusion stage for forming very low concentration mesas for a Schottky; higher concentration mesas with source regions for Accufet devices and a channel implant and source implant for a vertical conduction MOSFET.

Abstract: An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry. The ESD protection circuit includes a silicon controlled rectifier (SCR) having at least one first type high dopant region coupled to a first reference potential of the protected circuitry, and at least one second type high dopant region coupled to a second reference potential of the IC. The SCR is triggered by an external on-chip trigger device, which is adapted for injecting a trigger current into at least one gate of the SCR.

Abstract: A p-type impurity layer is formed in an n-type semiconductor substrate. Since the p-type impurity layer has a low impurity concentration and a sufficiently shallow depth of 1.0 ?m or less, the carrier injection coefficient can be reduced. In the p-type impurity layer, a p-type contact layer of a high impurity concentration is formed for reducing a contact resistance. Since the p-type contact layer has a sufficiently shallow depth of 0.2 ?m or less, it does not influence the carrier injection coefficient. Further, a silicide layer is formed between the p-type contact layer and an electrode such that the contact-layer-side end of the silicide layer corresponds to that portion of the p-type contact layer, at which the concentration profile of the contact layer assumes a peak value. The silicide layer further reduces the contact resistance.

Abstract: A method for fabricating a semiconductor and at least one second semiconductor zone of a semiconductor component having a semiconductor body having a first semiconductor zone. At least one field zone arranged in an edge region of the semiconductor body is reduced in size by means of an etching method. In another embodiment, the semiconductor body is partially removed in a region outside the first semiconductor zone. At least one second semiconductor zone is then fabricated in the partially removed region.

Abstract: The present invention provides a method of fabricating a high-voltage CMOS device, in which an extended drain region failing to enclose a heavily-doped drain region is separated from a high current flow path to enable high electric field concentration and breakdown to occur within a bulk of a silicon substrate and by which device reliability can be enhanced. The present invention includes the steps of forming a pad oxide layer on a substrate, forming a heavily doped drain region, a heavily doped source region, a source region, and an extended drain region failing to enclose the heavily doped drain region by ion implantation using a pattern provided on the pad oxide layer, forming a field oxide layer on a prescribed area of the extended drain region, and forming a gate and a gate spacer over the substrate.

Abstract: In one embodiment a method is provided. The method comprises inserting a first end of a P-type semiconductor pin in a first through hole via in a substrate; inserting a first end of an N-type semiconductor pin in a second through hole via in the substrate; and electrically connecting the first ends of the P and N-type semiconductor pins to form a precursor Peltier cooling device which in cooperation with a semiconductor die, bridges the P and N-type semiconductor pins between their ends remote from the first ends to define a Peltier cooling device in the substrate.

Abstract: The invention describes a structure and a process for providing ESD semiconductor protection with reduced input capacitance. The structure consists of heavily doped P+ guard rings surrounding the I/O ESD protection device and the Vcc to Vss protection device. In addition, there is a heavily doped N+ guard ring surrounding the I/O protection device and its P+ guard ring. The guard rings enhance structure diode elements providing enhanced ESD energy discharge path capability enabling the elimination of a specific conventional Vss to I/O pad ESD protection device. This reduces the capacitance seen by the I/O circuit while still providing adequate ESD protection for the active circuit devices.

Abstract: An integrated circuit structure includes a semiconductor substrate and a thyristor formed thereon. The thyristor has at least four layers, with three P-N junctions therebetween. At least two of the layers are formed horizontally and at least two of the layers are formed vertically. A gate is formed adjacent at least one of the vertically formed layers. An access transistor is formed on the semiconductor substrate, and an interconnect is formed between the thyristor and the access transistor.

Abstract: A double diffused region (65), (75), (85) is formed in an epitaxial layer (20). The double diffused region is formed by first implanting light implant specie such as boron through an opening in a photoresist layer prior to a hard bake process. Subsequent to a hard bake process heavy implant specie such as arsenic can be implanted into the epitaxial layer. During subsequent processing such as LOCOS formation the double diffused region is formed. A dielectric layer (120) is formed on the epitaxial layer (20) and gate structures (130), (135) are formed over the dielectric layer (120).

Abstract: Methods for fabricating Fin-Field Effect Transistors (Fin-FETs) are provided. A fin is formed on an integrated circuit substrate. The fin defines a trench on the integrated circuit substrate. A first insulation layer is formed in the trench such that a surface of the first insulation layer is recessed beneath a surface of the fin exposing sidewalls of the fin. A protection layer is formed on the first insulation layer and a second insulation layer is formed on the protection layer in the trench such that protection layer is between the second insulation layer and the sidewalls of the fin. Related Fin-FETs are also provided.

Abstract: A semiconductor memory device having a thyristor is manufactured in a manner that makes possible self-alignment of one or more portions of the thyristor. According to an example embodiment of the present invention, a gate is formed over a first portion of doped substrate. The gate is used to mask a portion of the doped substrate and a second portion of the substrate is doped before or after a spacer is formed. After the second portion of the substrate is doped, the spacer is then formed adjacent to the gate and used to mask the second portion of the substrate while a third portion of the substrate is doped. The gate and spacer are thus used to form self-aligned doped portions of the substrate, wherein the first and second portions form base regions and the third portion form an emitter region of a thyristor.

Abstract: An emitter includes an electron source and a cathode. The cathode has an emissive surface. The emitter further includes a continuous anisotropic conductivity layer disposed between the electron source and the emissive surface of the cathode. The anisotropic conductivity layer has an anisotropic sheet resistivity profile and provides for substantially uniform emissions over the emissive surface of the emitter.

Abstract: A FinFET device and a method of lowering a gate capacitance and extrinsic resistance in a field effect transistor, wherein the method comprises forming an isolation layer comprising a BOX layer over a substrate, configuring source/drain regions above the isolation layer, forming a fin structure over the isolation layer, configuring a first gate electrode adjacent to the fin structure, disposing a gate insulator between the first gate electrode and the fin structure, positioning a second gate electrode transverse to the first gate electrode, and depositing a third gate electrode on the fin structure, the first gate electrode, and the second gate electrode, wherein the isolation layer is formed beneath the insulator, the first gate electrode, and the fin structure. The method further comprises sandwiching the second gate electrode with a dielectric material. The fin structure is formed by depositing an oxide layer over a silicon layer.

Abstract: A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming a trench therein. A thyristor is formed around the trench and within the semiconductor substrate. The thyristor has at least four layers with three P-N junctions therebetween. A gate for the thyristor is formed within the trench. An access transistor is formed on the semiconductor substrate. An interconnect is formed between the thyristor and the access transistor.

Abstract: A semiconductor device is formed having a thyristor, a pass device and a conductive shunt that electrically connects an emitter region of the thyristor with a node near an upper surface of the substrate. In one example embodiment of the present invention, the conductive shunt is formed in a trench in a substrate and extending from an upper surface of the substrate to an emitter region of a vertical thyristor, with the emitter region being in the substrate and below the upper surface. In one implementation, the thyristor includes a thyristor body and a control port, with an N+ emitter region of the thyristor body being in the substrate and below and upper surface thereof. A pass device is formed adjacent to the thyristor, and the conductive shunt is formed in a trench extending from the N+ emitter region to a source/drain region of the pass device.

Abstract: JFET and MESFET structures, and processes of making same, for low voltage, high current and high frequency applications. The structures may be used in normally-on (e.g., depletion mode) or normally-off modes. The structures include an oxide layer positioned under the gate region which effectively reduces the junction capacitance (gate to drain) of the structure. For normally off modes, the structures reduce gate current at Vg in forward bias. In one embodiment, a silicide is positioned in part of the gate to reduce gate resistance. The structures are also characterized in that they have a thin gate due to the dipping of the spacer oxide, which can be below 1000 angstroms and this results in fast switching speeds for high frequency applications.

Abstract: In a method for forming a channel zone in field-effect transistors, a polysilicon layer is patterned above the channel zone to be formed. The polysilicon layer serves as a mask substrate for the subsequent doping of the channel zone. The expedient patterning of the polysilicon layer with holes in a gate region and pillars in a source region enables the channel zone to be doped more lightly. In another embodiment, the novel method is used for a channel width shading of a PMOS transistor cell.

Abstract: A memory system having a plurality of T-RAM cells arranged in an array is presented where each T-RAM cell has dual vertical devices and is fabricated over a SiC substrate. Each T-RAM cell has a vertical thyristor and a vertical transfer gate. The top surface of each thyristor is coplanar with the top surface of each transfer gate within the T-RAM array to provide a planar cell structure for the T-RAM array. A method is also presented for fabricating the T-RAM array having the vertical thyristors, the vertical transfer gates and the planar cell structure over the SiC substrate.

Abstract: A semiconductor device is formed having a thyristor and trench arranged to electrically insulate an emitter region of the thyristor from another circuit structure. In one example embodiment of the present invention, a trench having a bottom portion with two different trench depths is etched in the substrate. A thyristor is formed having a control port in a trench and having an emitter region adjacent to the trench and below an upper surface of the substrate. A deeper portion of the trench electrically insulates the emitter region from the other circuit structure. The control port is capacitively coupled to the thyristor and to the other circuit structure (e.g., in response to at least one edge of a voltage pulse applied thereto). In one implementation, the trench further includes an emitter-access connector extending from the emitter region to an upper surface of the substrate.

Abstract: In one embodiment, a transistor is formed to have alternating depletion and conduction regions that are formed by doping the depletion and conduction regions through an opening in a substrate of the transistor.

Abstract: A composite barrier layer formed between a glass film and active regions of a memory device is disclosed. The composite barrier layer comprises an oxide layer formed by atomic deposition process and an insulating layer, for example a nitride barrier layer, formed over the oxide layer. The composite barrier layer eliminates the diffusion of impurity atoms from the glass film into the active regions of the device.