Abstract: The invention includes SOI constructions containing one or more memory cells which include a transistor and a thyristor. In one aspect, a scalable GLTRAM cell provides DRAM-like density and SRAM-like performance. The memory cell includes an access transistor and a gated-lateral thyristor integrally formed above the access transistor. The cathode region (n+) of the stacked lateral thyristor device (p+/n/p/n+) is physically and electrically connected to one of the source/drain regions of the FET to act as the storage node for the memory cell. The FET transistor can include an active region which extends into a Si/Ge material. The material comprising Si/Ge can have a relaxed crystalline lattice, and a layer having a strained crystalline lattice can be between the material having the relaxed crystalline lattice and the transistor gate. The device construction can be formed over a versatile substrate base.

Abstract: A method for fabricating a field-effect-controllable semiconductor component includes providing a configuration having a semiconductor body with a front side, a rear side, a first terminal zone of a first conduction type, a channel zone of a second conduction type formed above the first terminal zone, and at least one control electrode adjacent the channel zone. The control electrode is insulated from the semiconductor body. A second terminal zone of the first conduction type is fabricated in the channel zone near the front side of the semiconductor body by: doping the channel zone near the front side with a first dopant concentration to fabricate a first zone of the first conduction type, and doping a section of the first zone with a second dopant concentration higher than the first dopant concentration to form a second zone of the first conduction type.

Abstract: A thyristor-based semiconductor device has a control port formed in a trench having a height-to-width aspect ratio that can be prohibitive to filling a bottom portion of the trench with an insulative material. According to an example embodiment of the present invention, a trench is formed in the substrate adjacent to a thyristor region, and a control port is formed near a bottom of the trench. An upper portion of the trench is then filled, thereby covering the control port. The control port is adapted to reduce the aspect ratio of a remaining portion of the trench over the control port, making it possible to fill trenches having a high height-to-width aspect ratio (e.g., at least 2:1). The thyristor control port is capacitively coupled to the thyristor region via a dielectric on a sidewall of the trench, and is configured and arranged to control current in the thyristor body via the capacitive coupling.

Abstract: Switching times of a thyristor-based semiconductor device are improved by enhancing carrier drainage from a buried thyristor-emitter region. According to an example embodiment of the present invention, a conductive contact extends to a doped well region buried in a substrate and is adapted to drain carriers therefrom. The device includes a thyristor body having at least one doped emitter region buried in the doped well region. A conductive thyristor control port is adapted to capacitively couple to the thyristor body and to control current flow therein. With this approach, the thyristor can be rapidly switched between resistance states, which has been found to be particularly useful in high-speed data latching implementations including but not limited to memory cell applications.

Abstract: A device comprising a semiconductor film (12) formed on a substrate (11), a gate region (15), in which a gate insulating film (13) formed on the semiconductor film and a gate electrode film (14) are laminated, isolation means (A) formed on both sides of the gate region to prevent contact between the gate electrode film and other regions, and a source region and a drain region formed by baking a liquid semiconductor material (17) and disposed on regions on the substrate and on both sides of the gate region.

Abstract: A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming a thyristor thereon. The thyristor has at least four layers, with three P-N junctions therebetween. At least two of the layers are formed horizontally and at least two of the layers are formed vertically. A gate is formed adjacent at least one of the vertically formed layers. An access transistor is formed on the semiconductor substrate, and an interconnect is formed between the thyristor and the access transistor.

Abstract: A MOS-gated semiconductor device is shown and described which includes deep implanted junctions and thick oxide spacers disposed over a substantial portion of common conduction regions.

Abstract: An N?-type silicon substrate (1) has a bottom surface and an upper surface which are opposed to each other. In the bottom surface of the N?-type silicon substrate (1), a P-type impurity diffusion layer (3) of high concentration is entirely formed by diffusing a P-type impurity. In the upper surface of the N?-type silicon substrate (1), a P-type isolation region (2) is partially formed by diffusing a P-type impurity. The P-type isolation region (2) has a bottom surface reaching an upper surface of the P-type impurity diffusion layer (3). As viewed from the upper surface side of the N?-type silicon substrate (1), the P-type isolation region (2) is formed, surrounding an N? region (1a) which is part of the N?-type silicon substrate (1). The N? region (1a) surrounded by the P-type isolation region (2) is defined as an element formation region of the N?-type silicon substrate (1).

Abstract: In one embodiment of the invention, a semiconductor component includes a semiconductor substrate (110), a first dielectric layer (120) above the semiconductor substrate, a first ohmic contact region (410) and a second ohmic contact region (420) above the semiconductor substrate, a gate electrode (1120) above the semiconductor substrate and between the first ohmic contact region and the second ohmic contact region, a field plate (210) above the first dielectric layer and between the gate electrode and the second ohmic contact region, a second dielectric layer (310) above the field plate, the first dielectric layer, the first ohmic contact region, and the second ohmic contact region, and a third dielectric layer (910) between the gate electrode and the field plate and not located above the gate electrode or the field plate.

Abstract: A method for manufacturing a gate pad protection structure applied in a power semiconductor device is provided. The method includes steps of (a) forming a gate oxide layer on a substrate, (b) forming a polysilicon layer on the gate oxide layer, (c) forming a polysilicon window and a polysilicon window array on the polysilicon layer, and (d) performing an ion implantation via the polysilicon window and the polysilicon window array.

Abstract: A semiconductor device includes a thyristor body having at least one region in a substrate. According to an example embodiment of the present invention, a trench is in a substrate and adjacent to a thyristor body region in the substrate. The trench is lined with an insulative material and further includes conductive material that is insulated from the thyristor body region in the substrate by the liner material. A conductive thyristor control port is located in the trench and adapted for capacitively coupling to the thyristor body region in the substrate and to control current in the thyristor body by causing an outflow of minority carriers in the thyristor. With this approach, conductive material can be used to fill a portion of the trench while using the trench portion including the conductive material to electrically isolate a portion of the thyristor body in the substrate.

Abstract: In the manufacturing process of a Bi-CMOS semiconductor device, which includes a CMOSFET and a bipolar transistor, the steps for forming a well region, source regions, and drain regions of the CMOSFET are also used for forming the bipolar transistor. One of the steps is used for introducing impurities of the same conductivity type in a surface of a base region of the bipolar transistor in order to form a high impurity concentration region in the surface. The high impurity concentration region is formed such that the distance between an emitter region of the bipolar transistor and the high impurity concentration region becomes 1 to 2 &mgr;m. The shift in device characteristics of the bipolar transistor is improved by the high impurity concentration region even if the impurity concentration is relatively low at the surface of the base region of the bipolar transistor.

Abstract: A semiconductor device having a thyristor is manufactured and arranged in a manner that reduces or eliminates difficulties commonly experienced in the formation and implementation of such devices. According to an example embodiment of the present invention, a thyristor (e.g., a thin capacitively-coupled thyristor) is formed having some or all of the body of the thyristor formed inlayed in a semiconductor device substrate. A trench is provided in the substrate, and a semiconductor material is formed in the trench. One or more layers of material are formed in the trench and used to form a portion of a body of the thyristor. The thyristor is formed having adjacent regions of different polarity, wherein at least one of the adjacent regions includes a portion of the semiconductor material and at least one of the adjacent regions includes a portion of the substrate.

Abstract: A method for stabilizing a tunnel junction component, in which a mask is formed on the surface of a substrate, and conductors are constructed by evaporation onto the substrate in an evaporation chamber, and at least one thin oxide layer element is oxidized on top of a selected conductor. This remains partly under the following conductor, thus forming a tunnel junction element with those conductors and titanium (Ti) or another gettering substance is evaporated on top of the said following conductor, before the tunnel junction component is removed from the evaporation chamber, when the titanium layer thus created protects the tunnel junction element from the detrimental effects of air molecules.

Abstract: Area efficient static memory cells and arrays containing p-n-p-n or n-p-n-p transistors which can be latched-up in a bistable on state. Each transistor memory cell includes a gate which is pulse biased during the write operation to latch-up the cell. Also provided are linked memory cells in which the transistors share common regions.

Abstract: A semiconductor memory device having a thyristor is manufactured in a manner that makes possible self-alignment of one or more portions of the thyristor. According to an example embodiment of the present invention, a gate is formed over a first portion of doped substrate. The gate is used to mask a portion of the doped substrate and a second portion of the substrate is doped before or after a spacer is formed. After the second portion of the substrate is doped, the spacer is then formed adjacent to the gate and used to mask the second portion of the substrate while a third portion of the substrate is doped. The gate and spacer are thus used to form self-aligned doped portions of the substrate, wherein the first and second portions form base regions and the third portion form an emitter region of a thyristor.

Abstract: Power semiconductor switching devices, power converters, integrated circuit assemblies, integrated circuitry, power current switching methods, methods of forming a power semiconductor switching device, power conversion methods, power semiconductor switching device packaging methods, and methods of forming a power transistor are described. One exemplary aspect provides a power semiconductor device including a semiconductive substrate having a surface; and a power transistor having a planar configuration and comprising a plurality of electrically coupled sources and a plurality of electrically coupled drains formed using the semiconductive substrate and adjacent the surface.

Abstract: In a method of manufacturing a semiconductor element (6) having a cathode (3) and an anode (5), the starting material used is a relatively thick wafer (1) to which, as a first step, a barrier region (21) is added on the anode side. It is then treated on the cathode side, and the thickness of the wafer (1) is then reduced on the side opposite to the cathode (3), and an anode (5) is produced on this side in a further step. The result is a relatively thin semiconductor element which can be produced economically and without epitaxial layers.

Abstract: A semiconductor substrate is disclosed, which comprises a lightly doped substrate that contains impurities at a low concentration, a heavily doped diffusion layer which is formed over a top of the lightly doped substrate and is higher in impurity concentration than the lightly doped substrate, and an epitaxial layer which is formed over a top of the heavily doped diffusion layer and contains impurities at a lower concentration than the heavily doped diffusion layer.

Abstract: A method for manufacturing a semiconductor device with a substrate having a device layer and a backside electrode is disclosed. Here, a surface roughness of the substrate is defined as a ratio between a substantial area and a projected area. The method includes polishing and wet-etching a backside surface of the substrate mechanically with using predetermined abrasive grains so that a surface roughness of the backside surface of the substrate becomes to be equal to or larger than 1.04, and forming the backside electrode on the backside surface of the substrate after polishing and wet-etching the backside surface of the substrate.

Abstract: An optical inspection system and method which uses a procedure for determining an offset between a field of view and a center or rotation of an R-theta stage, or polar coordinate stage. Determining this offset allows the precise location of a site being inspected on a wafer to be determined. The system and method take advantage of the fact that in a R-theta system there can be only two positions for the R-theta stage that will position a particular site under the lens of the imaging system of the optical inspection system. By moving the stage from a first position where a particular site is positioned in the field of view, to the second position where the particular site is positioned in the field of view, the offset can be determined.

Abstract: A double diffused region (65), (75), (85) is formed in an epitaxial layer (20). The double diffused region is formed by first implanting light implant specie such as boron through an opening in a photoresist layer prior to a hard bake process. Subsequent to a hard bake process heavy implant specie such as arsenic can be implanted into the epitaxial layer. During subsequent processing such as LOCOS formation the double diffused region is formed. A dielectric layer (120) is formed on the epitaxial layer (20) and gate structures (130), (135) are formed over the dielectric layer (120).

Abstract: A new method to form a LVT-SCR device in the manufacture of an integrated circuit device is achieved. The method comprises providing a SOI substrate comprising a silicon layer overlying a buried oxide layer. The silicon layer further comprises a first well of a first type and a second well of a second type. First and second doped regions of the first type are formed. The first doped region is in the first well. The second doped region is in the second well and forms an anode. Third, fourth, and fifth doped regions of the second type are formed. The third and fourth doped regions are in the first well. The fifth doped region is partly in the first well and partly in the second well. The first and third doped regions form a cathode. First and second gates are formed overlying the silicon layer. The first gate is between the third and fourth doped regions. The second gate is between the fourth and fifth doped regions. The doped regions are not separated by isolation oxide.

Abstract: A method for providing self aligned contacts for a trench power MOSFET is disclosed. The method includes, etching trenches in a substrate through a mask of silicon nitride deposited on an oxide layer, forming a gate oxide layer on the walls of the trenches, applying polysilicon to fill the trenches and to cover the surface of the mask of silicon nitride, removing the polysilicon from the surface of the mask of silicon nitride and applying a photoresist mask to cover a location of a gate bus.

Abstract: A MOS-gated semiconductor device is shown and described which includes deep implanted junctions and thick oxide spacers disposed over a substantial portion of common conduction regions.

Abstract: A method to form a SCR device in the manufacture of an integrated circuit device is achieved. The method comprises providing a SOI substrate comprising a silicon layer overlying a buried oxide layer. The silicon layer further comprises a first well of a first type and a second well of a second type. A first heavily doped region of the first type is formed in the second well to form an anode terminal. A second heavily doped region of the second type is formed in the first well to form a cathode terminal and to complete the SCR device. A gate isolation method is described. A salicide method is described. LVT-SCR methods, including a floating-well, LVT-SCR method, are described.

Abstract: A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first or second conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one trench in the epitaxial layer. A barrier material is deposited along the walls of the trench. A dopant of a second conductivity type is implanted through the barrier material into a portion of the epitaxial layer adjacent to and beneath the bottom of the trench. The dopant is diffused to form a first doped layer in the epitaxial layer and the barrier material is removed from at least the bottom of the trench. The trench is etched through the first doped layer. A second doped layer is formed in the same manner as the first doped layer. The second doped layer is located vertically below the first doped layer.

Abstract: A semiconductor device according to an aspect of the present invention includes a substrate having a semiconductor substrate and a semiconductor layer provided on the semiconductor substrate, said semiconductor layer being insulated by an insulating film; a thyristor with a gate, its pnpn structure being laterally formed in said semiconductor layer of said substrate; and a transistor formed in said semiconductor layer of said substrate; said transistor being connected to one terminal of said thyristor.

Abstract: A semiconductor device having a thyristor is manufactured in a manner that reduces or eliminates manufacturing difficulties commonly experienced in the formation of such devices. According to an example embodiment of the present invention, a thyristor is formed having some or all of the body of the thyristor extending above a substrate surface of a semiconductor device. The semiconductor device includes at least one transistor having source/drain regions formed in the substrate prior to the formation of the thyristor. One or more layers of material are deposited on the substrate surface and used to form a portion of a body of the thyristor that includes anode and cathode end portions. Each end portion is formed having a base region and an emitter region, and at least one of the end portions includes a portion that is in the substrate and electrically coupled to the transistor. A control port is formed capacitively coupled to at least one of the base regions.

Abstract: Gate oxide films, gate electrodes, base regions and emitter regions, which constitute IGBTs, are formed on a semiconductor wafer. A silicon oxide film is formed on the gate electrodes. Further, an emitter electrode is formed thereabove, and a passivation film is formed over the emitter electrode. Thereafter, an internal area of a back surface of the semiconductor wafer is polished to form a protrusion at its outer peripheral portion. Afterwards, an impurity is injected from the back surface of the semiconductor wafer to form a collector region. After a collector electrode is further formed, the semiconductor wafer is mounted on a stage smaller than the internal area and subjected to dicing along scribe areas. Thus, the strength of the semiconductor wafer is held by the protrusion, and cracking or the like of the semiconductor wafer can be reduced owing to the execution of the dicing in the above-described manner.

Abstract: A memory system having a plurality of T-RAM cells arranged in an array is presented where each T-RAM cell has dual vertical devices and is fabricated over a SiC substrate. Each T-RAM cell has a vertical thyristor and a vertical transfer gate. The top surface of each thyristor is coplanar with the top surface of each transfer gate within the T-RAM array to provide a planar cell structure for the T-RAM array. A method is also presented for fabricating the T-RAM array having the vertical thyristors, the vertical transfer gates and the planar cell structure over the SiC substrate.

Abstract: A semiconductor device constituting an IGBT exhibits low losses yet can be manufactured using an inexpensive wafer and with high yields, and exhibits low losses. The IGBT is produced by using a wafer, for example an FZ wafer, that is cut form an ingot and has its surface polished and cleaned, wherein an n-type impurity diffusion layer having an enough dose to stop the electric field in turn-off is provided between a collector layer and a base layer as a field-stop layer for stopping an electric field in turn-off. The thickness of this field-stop layer defined by Xfs−Xj is controlled in the range from 0.5 &mgr;m to 3 &mgr;m, where Xfs is the position at which the impurity concentration in the field-stop layer is twice the impurity concentration of the base layer, and Xj is the position of the junction between the filed-stopping layer and the collector layer.

Abstract: A negative buffer layer and a positive collector layer are formed on a side of one surface of a semiconductor substrate. The positive collector layer is set to have a low dose amount and set shallow so that a low injection efficiency emitter structure is realized. Break down voltage of a power device is controlled by a thickness of a drift layer. A positive base layer, a negative emitter layer and a positive base contact layer are formed on a side of the other surface of the semiconductor substrate. A negative low resistant layer reduces a junction FET effect. An emitter electrode comes into contact with the negative emitter layer and the positive base contact layer. A collector electrode comes into contact with the positive collector layer. A gate electrode is formed on a gate insulating film above a channel region on a surface portion of the positive base layer.

Abstract: A method for manufacturing a gate pad protection structure applied in a power semiconductor device is provided. The method includes steps of (a) forming a gate oxide layer on a substrate, (b) forming a polysilicon layer on the gate oxide layer, (c) forming a polysilicon window and a polysilicon window array on the polysilicon layer, and (d) performing an ion implantation via the polysilicon window and the polysilicon window array.

Abstract: A novel device structure and process are described for an SCR ESD protection device used with shallow trench isolation structures. The invention incorporates polysilicon gates bridging SCR diode junction elements and also bridging between SCR elements and neighboring STI structures. The presence of the strategically located polysilicon gates effectively counters the detrimental effects of non-planar STI “pull down” regions as well as compensating for the interaction of silicide structures and the effective junction depth of diode elements bounded by STI elements. Connecting the gates to appropriate voltage sources such as the SCR anode input voltage and the SCR cathode voltage, typically ground, reduces normal operation leakage of the ESD protection device.

Abstract: A semiconductor device of the present invention has a pn-repeating structure that a structure in which a p-type impurity region (4) and an n-type drift region (3) are aligned side by side is repeated twice or more, and a low concentration region which is either p-type impurity region (4) or n-type drift region (3) located at the outermost portion of this pn-repeating structure has the lowest impurity concentration or has the least generally effective charge amount among all the p-type impurity regions (4) and n-type drift regions (3) forming the pn-repeating structure.

Abstract: An embedded SCR in conjunction with a Gated-NMOS is created for protecting a chip input or output pad from ESD, by inserting a p+ diffusion and the n-well in the drain side and a part of the drain to forms a low-trigger, high efficiency SCR. The device layout is such that the drain connection is tightly tied together at the p+ diffusion and the n+ drain making that connection very short and, thereby, preventing latch-up. The parasitic SCR is contained entirely within the n+ diffusion (the source of the grounded gate NMOS transistor) at either side of the structure and, therefore, called an embedded SCR. For a 12 volt I/O device each of two n+ drains is placed in its own n-type doped drain (ndd) area straddling halfway the n-well. The structure is repeated as required and a p+ diffusion is implanted at both perimeters and connected to the nearest n+ source and a reference voltage.

Abstract: In accordance with a particular embodiment of the present invention, a method for manufacturing a semiconductor device includes forming a buried layer of a semiconductor substrate. An active region is formed adjacent at least a portion of the buried layer, and an isolation structure is formed adjacent at least a portion of the active region. A gate oxide is formed adjacent at least a portion of the active region. The method also includes forming a polysilicon layer adjacent at least a portion of the gate oxide. At least a portion of the polysilicon layer is removed to form a polysilicon definition structure. The polysilicon definition structure at least substantially surrounds and defines an emitter contact region. The method also includes forming an implant region of the emitter contact region, wherein the implant region is self-aligned.

Abstract: A vertical thin film transistor formed in a single grain of polysilicon having few or no grain boundaries for use in memory, logic and display applications. The transistor is formed from a thin film of polysilicon having large columnar grains, in which source and drain regions have been formed. The large grain size and columnar grain orientation of the thin film are provided by recrystallizing a thin amorphous silicon film, or by specialized deposition of the thin film. Use of a thin film permits the transistor to be formed on an insulating substrate such as glass, quartz, or inexpensive silicon rather than a semiconductor chip, thereby significantly decreasing device cost.

Abstract: An ESD protection circuit that will prevent internal circuits of an integrated circuit is formed on a semiconductor substrate to prevent damage during extreme voltage levels from an ESD voltage source and is connected to an input/output pad. A plurality of drains of multiple MOS FET's is formed within the surface of the semiconductor substrate and are each connected to the input/output pad. A plurality of sources of the multiple MOS FET's is formed within the surface of the semiconductor substrate and are placed at a distance from the plurality of drains and are connected to a ground reference potential. Pairs of the plurality of sources are adjacent to each other. A plurality of isolation regions placed between each source of the pairs of sources and are allowed to float. The multiple MOS FET's have a plurality of parasitic bipolar junction transistors.

Abstract: A method for manufacturing a discrete power rectifier device having a VLSI multi-cell design employs a two spacer approach to defining a P/N junction profile having good breakdown voltage characteristics. The method provides highly repeatable device characteristics at reduced cost. The active channel regions of the device are also defined using the same two spacers. The method is a self-aligned process and channel dimensions and doping characteristics may be precisely controlled despite inevitable process variations in spacer formation. Only two masking steps are required, and additional spacers for defining the body region profile can be avoided, reducing processing costs.

Abstract: A method for fabricating a trench MOS transistor includes the step of at least partly filling the trench with a conductive material which is isolated from the inner surface of the trench by an insulating layer. The insulating layer has a layer thickness that is larger in the region of the lower end of the trench than at the upper end of the trench.

Abstract: A novel capacitively coupled NDR device can be used to implement a variety of semiconductor circuits, including high-density SRAM cells and power thyristor structures. In one example embodiment, the NDR device is used as a thin vertical PNPN structure with capacitively-coupled gate-assisted turn-off and turn-on mechanisms. An SRAM based on this new device is comparable in cell area, standby current, architecture, speed, and fabrication process to a DRAM of the same capacity. In one embodiment, an NDR-based SRAM cell consists of only two elements, has an 8 F2 footprint, can operate at high speeds and low voltages, has a good noise-margin, and is compatible in fabrication process with main-stream CMOS. This cell significantly reduces standby power consumption compared to other types of NDR-based SRAMs.

Abstract: An insulated gate field effect transistor is disclosed. The transistor includes a semi-insulating silicon carbide substrate, an epitaxial layer of silicon carbide layer adjacent the semi-insulating substrate for providing a drift region having a first conductivity type, and source and drain regions in the epitaxial layer having the same conductivity type as the drift region. A channel region is in the epitaxial layer, has portions between the source and the drain regions, and has the opposite conductivity type from the source and drain regions. The transistor includes contacts to the epitaxial layer for the source, drain and channel regions, an insulating layer over the channel region of the epitaxial layer, and a gate contact adjacent the insulating layer and the channel region.

Abstract: A semiconductor apparatus and method for making the same is disclosed herein in which the semiconductor apparatus includes a first active device formed in a mesa region of semiconductor material formed on one or more sidewalls of an isolation region, and a conductive path which extends from the active device in a linear direction of the mesa. An embodiment is disclosed in which a plurality of active devices are formed in the mesa region and electrically connected thereby.

Abstract: A method and device produced for design, construction, and use of integrated circuits in wide bandgap semiconductors, including methods for fabrication of n-channel and p-channel junction field effect transistors on a single wafer or die, such that the produced devices may have pinchoff voltages of either positive or negative polarities. A first layer of either p-type or n-type is formed as a base. An alternating, channel layer of either n-type or p-type is then formed, followed by another layer of the same type as the first layer. Etching is used to provide contacts for the gates, source, and drain of the device. In one variation, pinchoff voltage is controlled via dopant level and thickness the channel region. In another variation, pinchoff voltage is controlled by variation of dopant level across the channel layer; and in another variation, pinchoff voltage is controlled by both thickness and variation of dopant level.

Abstract: An embedded parasitic silicon controlled rectifier (SCR) in conjunction with a Gated-NMOS is created for protecting a chip input or output pad from electrostatic discharge ESD, by inserting a p+ diffusion and the n-well in the drain side and a part of the drain to forms a low-trigger, high efficiency SCR. The device layout is such that the drain connection is tightly tied together at the p+ diffusion and the n+ drain making that connection very short and, thereby, preventing latch-up. The parasitic SCR is contained entirely within the n+ diffusion (the source of the grounded gate NMOS transistor) at either side of the structure and, therefore, called an embedded SCR. For a 12 volt I/O device each of two n+ drains is placed in its own n-type doped drain (ndd) area straddling halfway the n-well. The structure is repeated as required and a p+ diffusion is implanted at both perimeters and connected to the nearest n+ source and a reference voltage.

Abstract: Compact trench-gate semiconductor devices, for example a cellular power MOSFET with sub-micron pitch (Yc), are manufactured with self-aligned techniques that use sidewall spacers (52) in different ways. The trench-gate (11) is accommodated in a narrow trench (20) that is etched via a narrow window (52b) defined by the spacers (52) at sidewalls of a wider window (51a) of a mask (51) at the body surface (10a). The spacers (52) permit a source region (13) adjacent to the trench-gate (11) and an insulating overlayer (18) over the trench-gate (11) to be self-aligned to this narrow trench (20). The overlayer (18), which defines a contact window (18a) for a source electrode (33), is provided in a simple but reproducible manner by deposition and etch-back, after removing the spacers (52). Its overlap (y4, y4′) with the body surface (10a) is well-defined, so reducing a short-circuit risk between the source electrode (33) and the trench-gate (11).

Abstract: A method of manufacturing a LDHOS transistor having a dielectric block under the gate electrode. A high voltage well, low voltage well (LV PW), and field oxide regions having bird beaks are provided in a substrate and overlay the high voltage well and the low voltage well. In a key step, a dielectric block is formed over the bird beaks of the field oxide regions. A gate is formed over the dielectric block. After this the LDMOS device is completed. The invention's dielectric block covers the bird's beaks of the field oxide regions and enhances the e-field tolerance. The invention's e-field enhancement dielectric block relieves the e-field near the bird's beak, thus increasing the breakdown voltage of the transistor.

Abstract: A structure and fabrication method using latch-up implantation to improve latch-up immunity in CMOS circuit. The impedance of parasitic SCR conducting path is raised by performing an ion-implantation process on a cathode and an anode of a parasitic SCR which may induce latch-up phenomenon. Thus, the parasitic SCR is thus not easily to be conducted with a higher resistance to noise. Therefore, the latch-up immunity can be improved. In addition, the ion implantation process can be performed to achieve the objective of preventing latch-up effect without consuming more area for layout, thus greatly enhances the flexibility in circuit design.