Abstract: A thin film transistor and a method for fabricating the same are disclosed, in which an offset region is affected or biased by a gate voltage to increase on-current, thereby improving on/off characteristic of a device. A first semiconductor layer is formed on a substrate, and insulating layer patterns are formed at both ends of the first semiconductor layer. A second semiconductor layer is formed on the first semiconductor layer and the insulating layer patterns. A gate insulating film is formed on the first and second semiconductor layers and the insulating layer patterns, and an active layer formed on the gate insulating film.

Abstract: A semiconductor device constituting an IGBT exhibits low losses yet can be manufactured using an inexpensive wafer and with high yields, and exhibits low losses. The IGBT is produced by using a wafer, for example an FZ wafer, that is cut form an ingot and has its surface polished and cleaned, wherein an n-type impurity diffusion layer having an enough dose to stop the electric field in turn-off is provided between a collector layer and a base layer as a field-stop layer for stopping an electric field in turn-off. The thickness of this field-stop layer defined by Xfs-Xj is controlled in the range from 0.5 &mgr;m to 3 &mgr;m, where Xfs is the position at which the impurity concentration in the field-stop layer is twice the impurity concentration of the base layer, and Xj is the position of the junction between the filed-stopping layer and the collector layer.

Abstract: A method and device produced for design, construction, and use of integrated circuits in wide bandgap semiconductors, including methods for fabrication of n-channel and p-channel junction field effect transistors on a single wafer or die, such that the produced devices may have pinchoff voltages of either positive or negative polarities. A first layer of either p-type or n-type is formed as a base. An alternating, channel layer of either n-type or p-type is then formed, followed by another layer of the same type as the first layer. Etching is used to provide contacts for the gates, source, and drain of the device. In one variation, pinchoff voltage is controlled via dopant level and thickness the channel region. In another variation, pinchoff voltage is controlled by variation of dopant level across the channel layer; and in another variation, pinchoff voltage is controlled by both thickness and variation of dopant level.

Abstract: A T-RAM array having a planar cell structure is presented which includes a plurality of T-RAM cells. Each of the plurality of T-RAM cells is fabricated by using doped polysilicon to form a self-aligned diffusion region to create a low-contact resistance p+ diffusion region. A silicided p+ polysilicon wire is preferably used to connect each of the plurality of the T-RAM cells to a reference voltage Vref. A self-aligned junction region is formed between every two wordlines by implanting a n+ implant into a gap between every two wordlines. The self-aligned junction region provides for a reduction in the T-RAM cell size from a cell size of 8F2 for a prior art T-RAM cell to a cell size of less than or equal to 6F2. Preferably, the T-RAM array is built on a semiconductor silicon-on-insulator (SOI) wafer to reduce junction capacitance and improve scalability.

Abstract: A semiconductor substrate having a doped well region is provided. A gate stacking structure is formed on the doped well region. The gate stacking structure divides the doped well region into a first area and a second area. The second area is masked. The first area is masked. A spacer is formed on each side wall of the gate stacking structure. A dielectric layer is formed on the semiconductor substrate to cover the gate stacking structure, the spacer, the first doped area, and the second doped area. A via is formed on the dielectric layer. An in-situ doped poly-silicon is utilized to fill the via.

Abstract: A negative buffer layer and a positive collector layer are formed on a side of one surface of a semiconductor substrate. The positive collector layer is set to have a low dose amount and set shallow so that a low injection efficiency emitter structure is realized. Bread down voltage of a power device is controlled by a thickness of a drift layer. A positive base layer, a negative emitter layer and a positive base contact layer are formed on a side of the other surface of the semiconductor substrate. A negative low resistant layer reduces a junction FET effect. An emitter electrode comes into contact with the negative emitter layer and the positive base contact layer. A collector electrode comes into contact with the positive collector layer. A gate electrode is formed on a gate insulating film above a channel region on a surface portion of the positive base layer.

Abstract: A semiconductor device efficiently providing the DC currents required in both discrete and integrated circuits operated at low DC supply voltages. The device disclosed in the present invention is an asymmetrical, enhancement mode, Junction Field Effect Transistor (JFET). The device consists of an epitaxial layer on the surface of a substrate, both of which are doped with the same polarity. The epitaxial layer has a graded doping profile with doping density increasing with distance from the substrate. A grill-like structure is constructed within the upper and lower bounds of, and extending throughout the length and width of the epitaxial layer, and is doped with a polarity opposite to that of the epitaxial layer. A first electrical connection made to the exposed side of the substrate is defined as the drain electrode. A second electrical connection made to the exposed surface of the epitaxial layer is defined as the source electrode.

Abstract: A semiconductor integrated circuit device having a switching MISFET, and a capacitor element formed over the semiconductor substrate, such as a DRAM, is disclosed. In a first aspect of the present invention, the impurity concentration of the semiconductor region of the switching MISFET to which the capacitor element is connected is less than the impurity concentration of semiconductor regions of MISFETs of peripheral circuitry. In a second aspect, the Y-select signal line overlaps the lower electrode layer of the capacitor element. In a third aspect, a potential barrier layer, provided at least under the semiconductor region of the switching MISFET to which the capacitor element is connected,, is formed by diffusion of an impurity for a channel stopper region. In a fourth aspect, the dielectric film of the capacitor element is co-extensive with the capacitor electrode layer over it.

Abstract: Fuses for integrated circuits and semiconductor devices, methods for making the same, methods of using the same, and semiconductor devices containing the same. The semiconductor fuse contains two conductive layers—an overlying and underlying layer—on an insulating substrate. The underlying layer comprises titanium nitride and the overlying layer comprises tungsten silicide. The semiconductor fuse may be fabricated during manufacture of a local interconnect structure containing the same materials. The fuse, which may be used to program redundant circuitry, is blown by electrical current rather than laser beams, thus allowing the fuse width to be smaller than prior art fuses blown by laser beams. The fuse may also be blown by less electrical current than the current required to blow conventional polysilicon fuses having similar dimensions.

Abstract: The invention comprises an integrated circuit including integral high and low-voltage peripheral transistors and a method for making the integrated circuit. In one aspect of the invention, a method of integrating high and low voltage transistors into a floating gate memory array comprises the steps of forming a tunnel oxide layer outwardly from a semiconductor substrate, forming a floating gate layer disposed outwardly from the tunnel oxide layer and forming an insulator layer disposed outwardly from the floating gate layer to create a first intermediate structure. The method further includes the steps of masking a first region and a second region of the first intermediate structure leaving a third region unmasked, removing at least a portion of the insulator layer, the floating gate layer and the tunnel oxide layer from the third region and forming a first dielectric layer disposed outwardly from the substrate in a region approximately coextensive with the third region.

Abstract: An ESD protection circuit that will prevent internal circuits of an integrated circuit is formed on a semiconductor substrate to prevent damage during extreme voltage levels from an ESD voltage source and is connected to an input/output pad. A plurality of drains of multiple MOS FET's is formed within the surface of the semiconductor substrate and are each connected to the input/output pad. A plurality of sources of the multiple MOS FET's is formed within the surface of the semiconductor substrate and are placed at a distance from the plurality of drains and are connected to a ground reference potential. Pairs of the plurality of sources are adjacent to each other. A plurality of isolation regions placed between each source of the pairs of sources and are allowed to float. The multiple MOS FET's have a plurality of parasitic bipolar junction transistors.

Abstract: Power semiconductor devices having recessed gate electrodes are formed by methods which include the steps of forming a semiconductor substrate having a drift region of first conductivity type therein extending to a face thereof and forming a trench in the substrate so that the trench has a bottom which extends opposite the drift region and a sidewall which extends from the drift region to the face. The sidewall may extend orthogonal to the face or at an angle greater than 90°. A preferred insulated gate electrode is formed by lining the face and trench with a gate electrode insulating layer and then forming a conductive layer on the gate electrode insulating layer. The conductive layer is preferably formed to extend opposite a portion of the face adjacent to the trench and into the trench. A step is then performed to pattern the conductive layer to define a T-shaped or Y-shaped gate electrode which fills the trench and also extends opposite the face at a location adjacent the trench.

Abstract: Disclosed herein is a semiconductor device wherein a thyristor protective element and a trigger element are provided in a semiconductor layer formed on a buried insulating layer, and a trigger electrode (gate) of the thyristor protective element and a back gate of the trigger element are provided in the same p well and electrically connected to each other to thereby drive the thyristor protective element based on a substrate current produced by the breakdown of the trigger element.

Abstract: A method for fabricating a semiconductor power integrated circuit includes the steps of forming a semiconductor structure having at least one active region, wherein an active region includes a well region for forming a source and a drift region for forming a drain region, forming a trench for isolation of the active regions, wherein the trench has a predetermined depth from a surface of the semiconductor structure, forming a first TEOS-oxide layer inside the trench and above the semiconductor structure, wherein the first TEOS-oxide layer has a predetermined thickness from the surface of the semiconductor device, forming a second TEOS-oxide layer on the first TEOS-oxide layer, wherein a thickness of the second TEOS-oxide layer is smaller than that of the first TEOS-oxide layer, and performing a selective etching to the first and second TEOS-oxide layers, to thereby simultaneously form a field oxide layer pattern, a diode insulating layer pattern and a gate oxide layer pattern, to thereby reduce processing step

Abstract: A semiconductor package by which contacts are made to both sides of the dice is manufactured on a wafer scale. The back side of the wafer is attached to a metal plate. The scribe lines separating the dice are saw cut to expose the metal plate but the cuts do not extend through the metal plate. A metal layer, which may include a number of sublayers, is formed on the front side of the dice, the metal covering the exposed portions of the metal plate and extending the side edges of the dice. Separate sections of the metal layer may also cover connection pads on the front side of the dice. A second set of saw cuts are made coincident with the first set of saw cuts, using a blade that is narrower than the blade used to make the first set of saw cuts. As a result, the metal layer remains on the side edges of the dice connecting the back and front sides of the dice (via the metal plate).

Abstract: A method of fabricating a self-aligned bipolar junction transistor in a semiconductor structure having a first layer of silicon carbide generally having a first conductivity type and a second layer of silicon carbide generally having a second conductivity type, opposite to the first conductivity type. The method comprises forming a pillar in the second silicon carbide layer, the pillar having a side wall and defining an adjacent horizontal surface on the second layer, forming a dielectric layer having a predetermined thickness on the second semiconductor layer, including the side wall and the horizontal surface. After formation of the dielectric layer, the dielectric layer on a portion of the horizontal surface adjacent the side wall is anisotropically etched while at least a portion of the dielectric layer remains on the side wall, thereby exposing a portion of the horizontal surface.

Abstract: In a semiconductor device with a high breakdown voltage, insulating layers are buried at regions in n− silicon substrate located between gate trenches which are arranged with a predetermined pitch. This structure increases a carrier density at a portion near an emitter, and improves characteristic of an IGBT of a gate trench type having a high breakdown voltage.

Abstract: A semiconductor technique is disclosed. Particularly a low voltage high current power device for use in a lithium ion secondary battery protecting circuit, a DC-DC converter and a motor is disclosed. Further, a method for fabricating a high density trench gate type power device is disclosed. That is, in the present invention, a trench gate mask is used for forming the well and/or source, and for this purpose, a side wall spacer is introduced. In this manner, the well and/or source is defined by using the trench gate mask, and therefore, 1 or 2 masking processes are skipped unlike the conventional process in which the well mask and the source mask are separately used. The decrease in the use of the masking process decreases the mask align errors, and therefore, the realization of a high density is rendered possible. Consequently, the on-resistance which is an important factor for the power device can be lowered.

Abstract: An ESD protection circuit (11) includes a low capacitance diode (26), a voltage divider, a trigger transistor (16), and an SCR. Reducing the capacitance associated with the diode (26) makes the ESD protection circuit particularly suitable for RF applications. To form a low capacitance diode, the parasitic junction capacitance of the diode (26) is hidden in a like-doped well; for example, an N+ cathode (54) of the diode (26) may be folded or formed partially in an N-well (53). Because the N-well (53) does not form a junction with the N+ cathode, the junction capacitance associated with the portion of the N+ well lying inside the N-well is hidden or canceled by the N-well (53), thereby reducing the overall capacitance of the diode (26).

Abstract: A method of fabricating a MOS controlled thyristor (MCT) semiconductor power device which reduces process time, reduces cell size, and increases the density of turn-off channels. The method uses a single, dopant-opaque mask to form MCT structure above the bottom N and P layers, including the upper portions of PNP and NPN transistors which form the MCT and On-FETs and Off-FETs which operate the MCT. The single mask may also be used to fabricate floating field rings for the device. The method may also be used on both sides of the device to provide a Fast Turn Off (FTO) device with both On- and Off-FETs on one side and at least an Off-FET on the other side.

Abstract: A semiconductor apparatus and method for making the same is disclosed herein in which the semiconductor apparatus includes a first active device formed in a mesa region of semiconductor material formed on one or more sidewalls of an isolation region, and a conductive path which extends from the active device in a linear direction of the mesa. An embodiment is disclosed in which a plurality of active devices are formed in the mesa region and electrically connected thereby.

Abstract: Component structures of, for example, IGBTs are manufactured on the respective top sides of two substrates, the substrates are thinned proceeding from their respective back sides, and, after polishing, the back sides of the thinned substrates are durably electrically conductively connected to one another by wafer bonding.

Abstract: A method for fabricating a semiconductor device in a substrate. Active regions are defined within the substrate using a thin oxide layer and a silicon nitride layer with portions of the silicon nitride layer being etched away to expose the thin oxide layer. Field oxide regions are formed over regions other than the defined active regions. These field oxide regions are located between the active regions. The remaining portions of the silicon nitride layer and the thin oxide layer are removed and a sacrificial oxide layer is then grown on the surfaces of the active regions. A first mask, a N-well mask, is formed for implanting N-type dopants. A buried layer implanted using P-type dopants with the first mask in place. Thereafter, the N-well regions are implanted. The first mask is removed and a second mask is formed to define regions for implanting P-well regions using P-type dopants. The P-well regions are implanted using P-type dopants.

Abstract: A first metal electrode layer is formed to be electrically connected with a p base region formed in an n drift region. A second metal electrode layer which is electrically connected with an emitter region provided in the p base region is formed. A direct current power supply unit is provided to be electrically connected with the first and second metal electrode layers. The direct current power supply unit functions as means for applying forward bias to a pn junction between the n emitter region and the p base region.

Abstract: An MOS-gated power semiconductor device is formed by a process that uses a reduced number of masking steps and minimizes the number of critical alignments. A first photolithographic masking step defines the body or channel region and the source region of each of the cells. A second photolithographic step is aligned to a small central area above the source region of each of the cells or strips, the only critical alignment in the process, and is used to define openings in a protective oxide layer which, in turn, masks the etching of depressions in the substrate surface and the formation of a contact region. An isotropic etch undercuts the protective oxide to expose shoulders at the silicon surface of the chip which surround the etched holes. A conductive layer fills the holes and thus contacts the underlying body regions and overlaps the shoulders surrounding the source regions at the silicon surface.

Abstract: A switching device is described having a semiconductor substrate with a front side and a back side. The switching device includes a first transistor which includes a first region adjacent the front side, a second region within the first region, the semiconductor substrate, and at least one island region adjacent the backside. The switching device also includes a second transistor which includes the first region, the second region, the semiconductor substrate, and a third region coupled to the at least one island region.

Abstract: In a method for producing a channel region layer in a SiC-layer for producing a voltage controlled semiconductor device n-type dopants and p-type dopants are implanted into a near-surface layer of the SiC layer. The p-type dopants implanted have a higher diffusion rate in SiC than the n-type dopants implanted. The SiC-layer is then heated at such a temperature that p-type dopants implanted diffuse from the near-surface layer into the surrounding regions of the SiC-layer being lightly n-doped to such a degree that a channel region layer in which p-type dopants dominates is created.

Abstract: A process for forming a MOS gated device in which an oxide layer grown on a silicon surface is first patterned to form windows for implantation of P++ regions. Following implantation of the P++ regions, the oxide is completely etched off, and a thermal oxide layer is grown on the wafer surface. Since oxide grows thicker over the highly doped P++ region, the result is a pattern of thick and thin oxide layers atop the silicon surface. Polysilicon is then patterned atop the oxide layer with a critical alignment step to the thin oxide layers in the process. Boron is implanted through both the thick and thin regions of the oxide which are exposed by the polysilicon mask to form P type base regions and P type guard rings in the silicon. Arsenic is thereafter implanted at an energy at which arsenic atoms significantly penetrate only the thin oxide exposed by the polysilicon to form self-aligned source regions in the P type base regions previously formed.

Abstract: A manufacturing method of a vertical DMOSFET having a concave channel structure, which does not permit the introduction of defects or contaminant into the channel part and which can make the shape of the groove uniform, is disclosed. On a surface of a (100)-oriented n.sup.- -on-n.sup.+ epitaxial wafer is formed an initial groove by chemical dry etching. The grooved surface is then oxidized by LOCOS technique to form a LOCOS oxide film, whereby the concave structure is formed on the epitaxial wafer. The concave width is set to be at least twice the concave depth, and the sidewall angle is set to be approximately 50.degree. to make the sidewall plane (111) of high channel mobility plane. Following this process, p-type and n-type impurities are diffused from the main surface using the LOCOS oxide film as a double diffusion mask to form a body region and a source region.

Abstract: A process for manufacturing a vertical gate-enhanced bipolar transistor is described. The process does not require the presence of an insulating substrate to electrically isolate devices and is suitable for both NPN as well as PNP bipolar transistors. The process begins with the formation of a buried layer. This layer is accessed from the surface through a suitable well region. Then a trench, shaped as a hollow square is formed, lined with a layer of gate oxide and then filled with low resistivity polysilicon to form the gate. A polysilicon emitter layer is formed in the interior of the square, following implantation of arsenic ions with thermal drive-in to form an emitter junction just below the surface. After formation of the emitter junction, isolation layers, including self-aligned spacers, are constructed to cover the polysilicon emitter layer. Another layer of polysilicon is then laid down and then boron ions are implanted. This is followed by a thermal drive-in to form a base contact.

Abstract: The specification describes a p-channel IGBT with improved performance attributable to a vertical underlying n-p-n structure, and fabricated by a process that is fully compatible with simultaneously forming complementary MOS and TGBT devices.

Abstract: An insulated-gate bipolar transistor includes a semiconductor region of a first conductive type; a base layer of a second conductive type diffused from a surface of the semiconductor region; a source layer of the first conductive type diffused in a surface portion of the base layer; an insulated gate buried in a recess dug from the surface of the source layer through the base layer up to the semiconductor region; a collector layer of the second conductive type diffused from a surface of the semiconductor region on an opposite side of the insulated gate with respect to the source layer; an emitter terminal drawn from the base layer and the source layer; a collector terminal drawn from the collector layer; and a gate terminal drawn from the insulated gate.

Abstract: A monolithically integrated, transistor bridge circuit of a type suiting power applications, comprises at least one pair of IGBT transistors (M1 , M2) together with vertically-conducting bipolar junction transistors transistors (T1, T2). These IGBT transistors are laterally conducting, having drain terminals (9, 19) formed on the surface of the integrated circuit (1), and through such terminals, they are connected to another pair of transistors (T1, T2) of the bipolar type.