Abstract: Provided are a semiconductor chip including a TSV passing through a transistor, and a stack module and a memory card using such a semiconductor chip. The semiconductor chip may include a semiconductor layer that has a first surface and a second surface opposite to each other. A conductive layer may be disposed on the first surface of the semiconductor layer. A TSV may pass through the semiconductor layer and the conductive layer. A side wall insulating layer may surround a side wall of the TSV in order to electrically insulate the semiconductor layer and the conductive layer from the TSV.

Abstract: The protective circuit is formed using a non-linear element which includes a gate insulating film covering a gate electrode; a first wiring layer and a second wiring layer which are over the gate insulating film and whose end portions overlap with the gate electrode; and an oxide semiconductor layer which is over the gate electrode and in contact with the gate insulating film and the end portions of the first wiring layer and the second wiring layer. The gate electrode of the non-linear element and a scan line or a signal line is included in a wiring, the first or second wiring layer of the non-linear element is directly connected to the wiring so as to apply the potential of the gate electrode.

Abstract: An organic light emitting diode (OLED) display device and a method of fabricating the same is provided. Semiconductor layers of driving transistors located in two adjacent pixels included in the OLED display device may extend in different lengthwise directions. Thus, striped stains of the OLED display device can be improved.

Abstract: An object is to provide a semiconductor device having a novel structure in which a transistor including an oxide semiconductor and a transistor including a semiconductor material other than an oxide semiconductor are stacked. The semiconductor device includes a first transistor, an insulating layer over the first transistor, and a second transistor over the insulating layer. In the semiconductor device, the first transistor includes a first channel formation region, the second transistor includes a second channel formation region, the first channel formation region includes a semiconductor material different from a semiconductor material of the second channel formation region, and the insulating layer includes a surface whose root-mean-square surface roughness is less than or equal to 1 nm.

Abstract: The present invention relates to a method for providing a Silicon-On-Insulator (SOI) stack that includes a substrate layer, a first oxide layer on the substrate layer and a silicon layer on the first oxide layer (BOX layer). The method includes providing at least one first region of the SOI stack wherein the silicon layer is thinned by thermally oxidizing a part of the silicon layer and providing at least one second region of the SOI stack wherein the first oxide layer (BOX layer) is thinned by annealing.

Abstract: A semiconductor device and method is disclosed. One embodiment provides a method comprising placing a first semiconductor chip on a carrier. After placing the first semiconductor chip on the carrier, an electrically insulating layer is deposited on the carrier. A second semiconductor chip is placed on the electrically insulating layer.

Abstract: A display device provided with an MEMS light valve, comprising: a substrate, a fixed optical grating located on the substrate, an MEMS light valve for controlling the opening and closing of the fixed optical grating, the MEMS light valve comprises a first light valve and a second light valve; the opening and closing of the fixed optical grating is controlled via controlling the movement of the first light valve and the second light valve, and the moving directions of the first light valve and the second light valve are opposite. Also disclosed is a method for forming a display device provided with an MEMS light valve. Thus the sensitivity of the MEMS light valve is improved.

Abstract: A non-volatile bistable nano-electromechanical switch is provided for use in memory devices and microprocessors. The switch employs carbon nanotubes as the actuation element. A method has been developed for fabricating nanoswitches having one single-walled carbon nanotube as the actuator. The actuation of two different states can be achieved using the same low voltage for each state.

Abstract: An integrated circuit includes a transistor, an UTBOX buried insulating layer disposed under it, a ground plane disposed under the layer, a well disposed under the plane, a first trench made at a periphery of the transistor and extending through the layer and into the well, a substrate situated under the well, a p-n diode made on a side of the transistor and comprising first and second zones of opposite doping, the first zone being configured for electrical connection to a first electrode of the transistor, wherein first and second zones are coplanar with the plane, a second trench for separating the first and second zones, the second trench extending through the layer into the plane and until a depth less than an interface between the plane and the well, and a third zone under the second trench forming a junction between the zones.

Abstract: A thin film transistor is provided, which includes a gate insulating layer covering a gate electrode, a microcrystalline semiconductor layer provided over the gate insulating layer, an amorphous semiconductor layer overlapping the microcrystalline semiconductor layer and the gate insulating layer, and a pair of impurity semiconductor layers which are provided over the amorphous semiconductor layer and to which an impurity element imparting one conductivity type is added to form a source region and a drain region. The gate insulating layer has a step adjacent to a portion in contact with an end portion of the microcrystalline semiconductor layer. A second thickness of the gate insulating layer in a portion outside the microcrystalline semiconductor layer is smaller than a first thickness thereof in a portion in contact with the microcrystalline semiconductor layer.

Abstract: A method for manufacturing a thin film transistor array panel includes; forming a gate line including a gate electrode and a height increasing member on a substrate, forming a gate insulating layer on the gate line and the height increasing member, forming a semiconductor, a data line including a source electrode, and a drain electrode facing the source electrode and overlapping at least a portion of the height increasing member on the gate insulating layer, forming a first insulating layer on the gate insulating layer, a data line and the drain electrode, forming a light-blocking member on a portion of the first insulating layer corresponding to the gate line and the data line, forming a color filter in an area bound by the light-blocking member, forming a second insulating layer on the light-blocking member and the color filter, and patterning the second insulating layer, the light-blocking member or the color filter, and the first insulating layer to form a contact hole exposing a portion of the drain elec

Abstract: The present invention discloses a thin film transistor array substrate and a manufacturing method for the same. A transparent conductive layer and a first metal layer are deposited on a substrate, and a multi-tone mask is utilized to form a gate electrode and a common electrode. A gate insulative layer and a semi-conductive layer are deposited on the substrate with the gate electrode and the common electrode, and the semi-conductive layer is patterned by a second mask to retain a region of the semi-conductive layer that is there-above the gate electrode. A second metal layer is deposited on the substrate with the gate insulative layer along with the retained semi-conductive layer, and the second metal layer is patterned by a third mask to form a source electrode, a drain electrode, and a pixel electrode. The present invention provides a simple manufacturing method.

Abstract: In a transistor including an oxide semiconductor film, a metal oxide film for preventing electrification which is in contact with the oxide semiconductor film and covers a source electrode and a drain electrode is formed. Then, oxygen is introduced (added) to the oxide semiconductor film through the metal oxide film and heat treatment is performed. Through these steps of oxygen introduction and heat treatment, impurities such as hydrogen, moisture, a hydroxyl group, or hydride are intentionally removed from the oxide semiconductor film, so that the oxide semiconductor film is highly purified. Further, by providing the metal oxide film, generation of a parasitic channel on a back channel side of the oxide semiconductor film can be prevented in the transistor.

Abstract: The present invention is to provide a semiconductor device in which the step can be simplified, the manufacturing cost can be suppressed, and the decrease in yield can be suppressed. A semiconductor device of the present invention includes an antenna, a storage element, and a transistor, wherein a conductive layer serving as an antenna is provided in the same layer as a conductive layer of the transistor or the storage element. This characteristic makes it possible to omit an independent step of forming the conductive layer serving as an antenna and to conduct the step of forming the conductive layer serving as an antenna at the same time as the step of forming a conductive layer of another element. Therefore, the manufacturing step can be simplified, the manufacturing cost can be suppressed, and the decrease in yield can be suppressed.

Abstract: An organic EL display including a plurality of pixels each having, in order from a substrate side, a first electrode, an organic layer including a light emission layer, and a second electrode; an auxiliary wiring disposed in a periphery region of each of the plurality of pixels and conducted to the second electrode; and another auxiliary wiring disposed apart from the auxiliary wiring at least in a part of outer periphery of a formation region of the auxiliary wiring in a substrate surface.

Abstract: A method for manufacturing components on a mixed substrate. The method comprises the following steps: providing a substrate of the semiconductor-on-insulator (SeOI) type comprising a buried oxide layer between a supporting substrate and a thin layer, forming in this substrate a plurality of trenches opening out at a free surface of the thin layer and extending over a depth such that each trench passes through the thin layer and the buried oxide layer, these primary trenches delimiting at least one island of the SeOI substrate, forming a mask inside the primary trenches and as a layer covering the areas of the free surface of the thin layer located outside the islands, proceeding with heat treatment for dissolving the buried oxide layer present at the island, so as to reduce the thickness thereof.

Abstract: A TFT array substrate includes: a gate electrode connected to a gate line; a source electrode connected to a data line crossing the gate line to define a pixel region; a drain electrode which is opposite to the source electrode with a channel in between; a semiconductor layer defining the channel between the source electrode and the drain electrode; a pixel electrode in the pixel region and connected to the drain electrode; a channel passivation layer on the channel of the semiconductor layer; a gate pad extending from the gate line, where a semiconductor pattern and a transparent conductive pattern are formed; a data pad connected to the data line, where the transparent conductive pattern is formed; and a gate insulating layer formed under the semiconductor layer, the gate line and the gate pad, and the data line and the data pad.

Abstract: A switching device includes a substrate; a first electrode formed over the substrate; a second electrode formed over the first electrode; a switching medium disposed between the first and second electrode; and a nonlinear element disposed between the first and second electrodes and electrically coupled in series to the first electrode and the switching medium. The nonlinear element is configured to change from a first resistance state to a second resistance state on application of a voltage greater than a threshold.

Abstract: A method for manufacturing a thin film transistor substrate includes a step of forming a gate electrode (11a) and a first interconnect on a substrate (10), a step of forming a gate insulating film (12a) having a contact hole at a position overlapping the first interconnect, a step of forming a source electrode (13a) and a drain electrode (13b) overlapping the gate electrode (11a) and separated apart from each other, and a second interconnect connected via the contact hole to the first interconnect, a step of successively forming an oxide semiconductor film (14) and a second insulating film (15), and thereafter, patterning the second insulating film (15) to form an interlayer insulating film (15a), and a step of reducing the resistance of the oxide semiconductor film (14) exposed through the interlayer insulating film (15a) to form a pixel electrode (14b).

Abstract: Nanostructure array optoelectronic devices are disclosed. The optoelectronic device may have a top electrical contact that is physically and electrically connected to sidewalls of the array of nanostructures (e.g., nanocolumns). The top electrical contact may be located such that light can enter or leave the nanostructures without passing through the top electrical contact. Therefore, the top electrical contact can be opaque to light having wavelengths that are absorbed or generated by active regions in the nanostructures. The top electrical contact can be made from a material that is highly conductive, as no tradeoff needs to be made between optical transparency and electrical conductivity. The device could be a solar cell, LED, photo-detector, etc.

Abstract: A method for fabricating a metal-gate CMOS device. A substrate having thereon a first region and a second region is provided. A first dummy gate structure and a second dummy gate structure are formed within the first region and the second region respectively. A first LDD is formed on either side of the first dummy gate structure and a second LDD is formed on either side of the second dummy gate structure. A first spacer is formed on a sidewall of the first dummy gate structure and a second spacer is formed on a sidewall of the second dummy gate structure. A first embedded epitaxial layer is then formed in the substrate adjacent to the first dummy gate structure. The first region is masked with a seal layer. Thereafter, a second embedded epitaxial layer is formed in the substrate adjacent to the second dummy gate structure.

Abstract: A common cut mask is employed to define a gate pattern and a local interconnect pattern so that local interconnect structures and gate structures are formed with zero overlay variation relative to one another. A local interconnect structure may be laterally spaced from a gate structure in a first horizontal direction, and contact another gate structure in a second horizontal direction that is different from the first horizontal direction. Further, a gate structure may be formed to be collinear with a local interconnect structure that adjoins the gate structure. The local interconnect structures and the gate structures are formed by a common damascene processing step so that the top surfaces of the gate structures and the local interconnect structures are coplanar with each other.

Abstract: A method of manufacturing a thin film electronic device comprises applying a first plastic coating (PI-1) directly to a rigid carrier substrate (40) and forming thin film electronic elements (44) over the first plastic coating. A second plastic coating (46) is applied over the thin film electronic elements with electrodes (47) on top, with a portion lying directly over the associated electronic element, spaced by the second plastic coating. The rigid carrier substrate (40) is released from the first plastic coating, by a laser release process. This method enables traditional materials to be used as the base for the electronic element manufacture, for example thin film transistors. The second plastic coating can form part of the known field shielded pixel (FSP) technology.

Abstract: Provided are a sensor array substrate and a method of fabricating the same. The sensor array substrate includes: a substrate in which a switching element region and a sensor region that senses light are defined; a first semiconductor layer which is formed in the sensor region; a first gate electrode which is formed on the first semiconductor layer and overlaps the first semiconductor layer; a second gate electrode which is formed in the switching element region; a second semiconductor layer which is formed on the second gate electrode and overlaps the second gate electrode; and a light-blocking pattern which is formed on the second semiconductor layer and overlaps the second semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer are disposed on different layers, and the second gate electrode and the light-blocking pattern are electrically connected to each other.

Abstract: Semiconductor devices using a group III-V material, and methods of manufacturing the same, include a substrate having a groove, a group III-V material layer filling in the groove and having a height the same as a height of the substrate, a first semiconductor device on the group III-V material layer, and a second semiconductor device on the substrate near the groove. The group III-V material layer is spaced apart from inner side surfaces of the groove.

Abstract: A thin-film semiconductor device includes a semiconductor device part and a capacitor part. The semiconductor device part includes: a light-transmitting first gate electrode; a light-shielding second gate electrode; a first insulating layer; a semiconductor layer; a second insulating layer; and a source electrode and a drain electrode. The capacitor part includes: a first capacitor electrode made of a light-transmitting conductive material; a dielectric layer; and a second capacitor electrode. The second gate electrode, the semiconductor layer, and the second insulating layer have outlines that are coincident with one another in a top view.

Abstract: The semiconductor integrated circuit device has a hybrid substrate structure which includes both of an SOI structure and a bulk structure on the side of the device plane of a semiconductor substrate. In the device, the height of a gate electrode of an SOI type MISFET is higher than that of a gate electrode of a bulk type MISFET with respect to the device plane.

Abstract: A manufacturing method of a thin film transistor array substrate is provided. In the method, a substrate having a display region and a sensing region is provided. At least a display thin film transistor is formed in the display region, a first sensing electrode is formed in the sensing region, and an inter-layer dielectric layer is disposed on the substrate, covers the display thin film transistor, and exposes the first sensing electrode. A patterned photo sensitive dielectric layer is then formed on the first sensing electrode. A patterned transparent conductive layer is subsequently formed on the substrate, wherein the patterned transparent conductive layer includes a pixel electrode coupled to the corresponding display thin film transistor and includes a second sensing electrode located on the patterned photo sensitive dielectric layer. A manufacturing method of a liquid crystal display panel adopting the aforementioned thin film transistor array substrate is also provided.

Abstract: A first field effect transistor includes a gate dielectric and a gate electrode located over a first portion of a top semiconductor layer in a semiconductor-on-insulator (SOI) substrate. A second field effect transistor includes a portion of a buried insulator layer and a source region and a drain region located underneath the buried insulator layer. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer. The first field effect transistor may be a high performance device and the second field effect transistor may be a high voltage device. A design structure for the semiconductor structure is also provided.

Abstract: A method for producing a solid-state semiconducting structure, includes steps in which: (i) a monocrystalline substrate is provided; (ii) a monocrystalline oxide layer is formed, by epitaxial growth, on the substrate; (iii) a bonding layer is formed by steps in which: (a) the impurities are removed from the surface of the monocrystalline oxide layer; (b) a semiconducting bonding layer is deposited by slow epitaxial growth; and (iv) a monocrystalline semiconducting layer is formed, by epitaxial growth, on the bonding layer so formed. The solid-state semiconducting heterostructures so obtained are also described.

Abstract: A substrate diode for an SOI device is formed in accordance with an appropriately designed manufacturing flow, wherein transistor performance enhancing mechanisms may be implemented substantially without affecting the diode characteristics. In one aspect, respective openings for the substrate diode may be formed after the formation of a corresponding sidewall spacer structure used for defining the drain and source regions, thereby obtaining a significant lateral distribution of the dopants in the diode areas, which may therefore provide sufficient process margins during a subsequent silicidation sequence on the basis of a removal of the spacers in the transistor devices. In a further aspect, in addition to or alternatively, an offset spacer may be formed substantially without affecting the configuration of respective transistor devices.

Abstract: A method of fabricating a semiconductor integrated circuit includes forming a first dielectric layer on a semiconductor substrate, patterning the first dielectric layer to form a first patterned dielectric layer, forming a non-single crystal seed layer on the first patterned dielectric layer, removing a portion of the seed layer to form a patterned seed layer, forming a second dielectric layer on the first patterned dielectric layer and the patterned seed layer, removing portions of the second dielectric layer to form a second patterned dielectric layer, irradiating the patterned seed layer to single-crystallize the patterned seed layer, removing portions of the first patterned dielectric layer and the second patterned dielectric layer such that the single-crystallized seed layer protrudes in the vertical direction with respect to the first and/or the second patterned dielectric layer, and forming a gate electrode in contact with the single-crystal active pattern.

Abstract: A display substrate includes a gate line, a gate insulation layer, a data line, a switching element, a protection insulation layer, a gate pad portion and a data pad portion. The gate insulation layer is disposed on the gate line. The switching element is connected to the gate line and the data line. The protection insulation layer is disposed on the switching element. The gate pad portion includes a first gate pad electrode which makes contact with an end portion of the gate line through a first hole formed through the gate insulation layer, and a second gate pad electrode which makes contact with the first gate pad electrode through a second hole formed through the protection insulation layer. The data pad portion includes a data pad electrode which makes contact with an end portion of the data line through a third hole formed through the protection insulation layer.

Abstract: A method of fabricating a liquid crystal display device includes forming first, second, and third active patterns on a substrate having a pixel region and a driving region, wherein the first and second active patterns are in the driving region and the third active pattern is in the pixel region, the first, second, and third active patterns each having an active region, a source region, and a drain region with the source and drain regions on opposing sides of the active region, forming a gate insulator on the first, second, and third active patterns, forming first, second, and third gate electrodes on the gate insulator, wherein the first, second, and third gate electrodes correspond to the active regions of the first, second, and third active patterns, respectively, doping the source and drain regions of the first, second, and third active patterns with n? ions using the first, second, and third gate electrodes as a doping mask, doping the n? doped source and drain regions of the second active pattern with p+

Abstract: The invention relates to a method for forming a pattern on a substrate (S) with an upper surface and a lower surface which comprises the steps of depositing a first layer (E1) of an opaque material on the upper surface of the substrate (S), depositing a photosensitive layer (R) such that part of the photosensitive layer (R) covers at least part of the first layer (E1), exposing the photosensitive layer (R) to a light beam (L), the light beam (L) impinging on the lower surface of the substrate (S) under an oblique angle (?) of incidence, removing the exposed region of the photosensitive layer (R), depositing a second layer (E2) of an opaque material such that part of the second layer (E2) covers a remaining region of the photosensitive layer (R), and removing at least a part of the remaining region of the photosensitive layer (R).

Abstract: Transistors (21, 41) employing floating buried layers (BL) (72) may exhibit transient breakdown voltage (BVdss)TR significantly less than (BVdss)DC. It is found that this occurs because the floating BL (72) fails to rapidly follow the applied transient, causing the local electric field within the device to temporarily exceed avalanche conditions. (BVdss)TR of such transistors (69. 69?) can be improved to equal or exceed (BVdss)DC by including a charge pump capacitance (94, 94?) coupling the floating BL (72) to whichever high-side terminal (28, 47) receives the transient. The charge pump capacitance (94, 94?) may be external to the transistor (69, 69?), may be formed on the device surface (71) or, may be formed internally to the transistor (69-3, 69?-3) using a dielectric deep trench isolation wall (100) separating DC isolated sinker regions (86, 88) extending to the BL (72). The improvement is particularly useful for LDMOS devices.

Abstract: The protective circuit is formed using a non-linear element which includes a gate insulating film covering a gate electrode; a first wiring layer and a second wiring layer which are over the gate insulating film and whose end portions overlap with the gate electrode; and an oxide semiconductor layer which is over the gate electrode and in contact with the gate insulating film and the end portions of the first wiring layer and the second wiring layer. The gate electrode of the non-linear element and a scan line or a signal line is included in a wiring, the first or second wiring layer of the non-linear element is directly connected to the wiring so as to apply the potential of the gate electrode.

Abstract: A method of forming a device is presented. The method includes providing a structure having first and second regions. A diffusion barrier is formed between at least a portion of the first and second regions. The diffusion barrier comprises cavities that reduce diffusion of elements between the first and second regions.

Abstract: In a semiconductor device manufacturing method, a first semiconductor region which includes a narrow portion and a wide portion is formed in an upper portion of a semiconductor substrate, a gate insulating film is formed on at least side surfaces of the narrow portion, a gate electrode is formed on the gate insulating film, a mask pattern that covers the wide portion is formed, ion implantation of an impurity is performed with the mask pattern as a mask to form an extension impurity region in the narrow portion, the mask pattern is removed, a heat treatment is performed to activate the impurity, a gate sidewall is formed on a side surface of the gate electrode, epitaxial growth of a semiconductor film is performed on the narrow portion and the wide portion after the formation of the gate sidewall, and source-drain regions is formed on both sides of the gate electrode.

Abstract: A three-dimensional integrated circuit includes a semiconductor device, an insulator formed on the semiconductor device, an interconnect formed in the insulator, and a graphene device formed on the insulator.

Abstract: The present invention relates to a process of making a zinc-oxide-based thin film semiconductor, for use in a transistor, comprising thin film deposition onto a substrate comprising providing a plurality of gaseous materials comprising at least first, second, and third gaseous materials, wherein the first gaseous material is a zinc-containing volatile material and the second gaseous material is reactive therewith such that when one of the first or second gaseous materials are on the surface of the substrate the other of the first or second gaseous materials will react to deposit a layer of material on the substrate and wherein the third gaseous material is inert with respect to reacting with the first or second gaseous materials.

Abstract: A nonvolatile semiconductor memory device includes: a multilayer body with a plurality of insulating films and electrode films alternately stacked therein; a plurality of select gate electrodes provided on the multilayer body, extending in one direction orthogonal to a stacking direction of the multilayer body, and spaced from each other; semiconductor pillars penetrating through the multilayer body and the select gate electrodes; and a charge storage film provided between one of the electrode films and one of the semiconductor pillars, two neighboring ones of the semiconductor pillars penetrating through a common one of the select gate electrodes and penetrating through mutually different positions in a width direction of the select gate electrodes.

Abstract: An array substrate for a liquid crystal display device includes a substrate, a gate line on the substrate, a data line crossing the gate line to define a pixel region, a thin film transistor connected to the gate line and the data line and including a gate electrode, an active layer, an ohmic contact layer, a buffer metallic layer, a source electrode and a drain electrode, and a pixel electrode in the pixel region and connected to the thin film transistor, wherein the data line includes a transparent conductive layer and an opaque conductive layer, and each of the source and drain electrodes and the pixel electrode includes a transparent conductive layer.

Abstract: Disclosed is a semiconductor device production method, which comprises the steps of: forming a pillar-shaped first-conductive-type semiconductor layer on a planar semiconductor layer; forming a second-conductive-type semiconductor layer in a portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a gate dielectric film and a gate electrode having a laminated structure of a metal film and an amorphous silicon or polysilicon film, around the pillar-shaped first-conductive-type semiconductor layer; forming a sidewall-shaped dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate electrode; forming first and second sidewall-shaped dielectric films on a sidewall of the gate electrode; forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer; forming a metal-semiconductor compound

Abstract: An organic light emitting diode display device includes a switch TFT and a drive TFT formed on a substrate; an overcoat layer formed on the TFTs; a drain contact hole exposing portions of a drain electrode of the drive TFT by removing portions of the overcoat layer; a first electrode contacting to the drain electrode of the drive TFT; a bank pattern exposing an aperture area of a pixel; an organic layer formed on the first electrode; and a second electrode formed on the organic layer, wherein the bank pattern blocks regions where the drain contact hole is formed.

Abstract: A nonvolatile semiconductor memory of an aspect of the present invention comprises a semiconductor substrate, a pillar-shaped semiconductor layer extending in the vertical direction with respect to the surface of the semiconductor substrate, a plurality of memory cells arranged in the vertical direction on the side surface of the semiconductor layer and having a charge storage layer and a control gate electrode, a first select gate transistor arranged on the semiconductor layer at an end of the memory cells on the side of the semiconductor substrate, and a second select gate transistor arranged on the semiconductor layer on the other end of the memory cells opposite to the side of the semiconductor substrate, wherein the first select gate transistor includes a diffusion layer in the semiconductor substrate and is electrically connected to the pillar-shaped semiconductor layer by way of the diffusion layer that serves as the drain region.

Abstract: An object is to provide a semiconductor device having a novel structure in which a transistor including an oxide semiconductor and a transistor including a semiconductor material other than an oxide semiconductor are stacked. The semiconductor device includes a first transistor, an insulating layer over the first transistor, and a second transistor over the insulating layer. In the semiconductor device, the first transistor includes a first channel formation region, the second transistor includes a second channel formation region, the first channel formation region includes a semiconductor material different from a semiconductor material of the second channel formation region, and the insulating layer includes a surface whose root-mean-square surface roughness is less than or equal to 1 nm.

Abstract: A display device including a thin film transistor with high electric characteristics and high reliability, and a method for manufacturing the display device with high mass-productivity. In a display device including an inverted-staggered channel-stop-type thin film transistor, the inverted-staggered channel-stop-type thin film transistor includes a microcrystalline semiconductor film including a channel formation region, and an impurity region containing an impurity element of one conductivity type is selectively provided in a region which is not overlapped with source and drain electrodes, in the channel formation region of the microcrystalline semiconductor film.

Abstract: A structure and method for forming SRAMs on HOT substrates with STI is described. Logic circuits may also be fabricated on the same chip with some devices on the SOI regions and other devices on the SOI regions.

Abstract: A first field effect transistor includes a gate dielectric and a gate electrode located over a first portion of a top semiconductor layer in a semiconductor-on-insulator (SOI) substrate. A second field effect transistor includes a portion of a buried insulator layer and a source region and a drain region located underneath the buried insulator layer. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer. The first field effect transistor may be a high performance device and the second field effect transistor may be a high voltage device. A design structure for the semiconductor structure is also provided.