Combined With Electrical Device Not On Insulating Substrate Or Layer Patents (Class 438/152)
  • Patent number: 10121707
    Abstract: A method for making a FET transistor, including the following steps: making, on a crystalline semiconducting layer, a layer of gate dielectric on which a gate conducting layer is arranged, etching the conducting layer such that a remaining portion of this layer fully covers a first semiconducting portion forming an active zone and a second semiconducting portion adjacent to the active zone, implanting atoms and/or dopants in the semiconducting layer, thus amorphizing the semiconductor around the first portion and that of the second portion, etching the remaining portion of the conducting layer and of the dielectric layer according to a gate pattern partially covering the first portion and the second portion, forming the gate and a gate overflow, etching the amorphous semiconductor.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: November 6, 2018
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Claire Fenouillet-Beranger, Philippe Coronel
  • Patent number: 9716075
    Abstract: A microelectronic assembly may include a substrate including a rigid dielectric layer having electrically conductive elements, a microelectronic element having a plurality of contacts exposed at a face thereof, and conductive vias extending through a compliant dielectric layer overlying the rigid dielectric layer. The vias electrically connect the substrate contacts respectively to the conductive elements, and the substrate contacts are joined respectively to the contacts of the microelectronic element. The vias, compliant layer and substrate contacts are adapted to appreciably relieve stress at the substrate contacts associated with differential thermal contact and expansion of the assembly.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: July 25, 2017
    Assignee: Tessera, Inc.
    Inventors: Teck-Gyu Kang, Wei-Shun Wang, Hiroaki Sato, Kiyoaki Hashimoto, Yoshikuni Nakadaira, Norihito Masuda, Belgacem Haba, Ilyas Mohammed, Philip Damberg
  • Patent number: 9577642
    Abstract: A method to form a 3D integrated circuit, the method including: fabricating two or more devices; connecting the devices together to form the 3D integrated circuit, where at least one of the devices has at least one unused designated dice line and at least one of the devices is a configurable device; and interconnecting at least two of the devices using Through Silicon Vias.
    Type: Grant
    Filed: November 7, 2010
    Date of Patent: February 21, 2017
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Ze'ev Wurman
  • Patent number: 9509313
    Abstract: A semiconductor device comprising first layer comprising multiplicity of first transistors and, second layer comprising multiplicity of second transistors and, at least one function constructed by the first transistors are structure so it could be replaced by a function constructed by the second transistors.
    Type: Grant
    Filed: March 6, 2011
    Date of Patent: November 29, 2016
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Zeev Wurman
  • Patent number: 9449831
    Abstract: An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide layer overlying the channel; and a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which a stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which a stoichiometric composition of the second oxynitride layer results in it being trap dense. In one embodiment, the device comprises a non-planar transistor including a gate having multiple surfaces abutting the channel, and the gate comprises the tunnel oxide layer and the multi-layer charge storing layer.
    Type: Grant
    Filed: March 31, 2012
    Date of Patent: September 20, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Sagy Levy, Krishnaswamy Ramkumar, Fredrick Jenne, Sam Geha
  • Patent number: 9269823
    Abstract: In a miniaturized transistor, a gate insulating layer is required to reduce its thickness; however, in the case where the gate insulating layer is a single layer of a silicon oxide film, a physical limit on thinning of the gate insulating layer might occur due to an increase in tunneling current, i.e. gate leakage current. With the use of a high-k film whose relative permittivity is higher than or equal to 10 is used for the gate insulating layer, gate leakage current of the miniaturized transistor is reduced. With the use of the high-k film as a first insulating layer whose relative permittivity is higher than that of a second insulating layer in contact with an oxide semiconductor layer, the thickness of the gate insulating layer can be thinner than a thickness of a gate insulating layer considered in terms of a silicon oxide film.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: February 23, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuta Endo, Takayuki Saito, Shunpei Yamazaki
  • Patent number: 9202546
    Abstract: The semiconductor device includes: a transistor having an oxide semiconductor layer; and a logic circuit formed using a semiconductor material other than an oxide semiconductor. One of a source electrode and a drain electrode of the transistor is electrically connected to at least one input of the logic circuit, and at least one input signal is applied to the logic circuit through the transistor. The off-current of the transistor is preferably 1×10?13 A or less.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: December 1, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Keitaro Imai, Jun Koyama
  • Patent number: 9070592
    Abstract: Disclosed herein is a fabrication method of a semiconductor device to order to increase an operation liability of the semiconductor device. A method for fabricating a semiconductor device comprises forming a buried-type wordline in an active region defined on a SOI substrate, forming a silicon connection region for connecting an upper silicon layer to a lower silicon layer between neighboring buried type wordlines, and recovering the upper silicon layer on the silicon connection region.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: June 30, 2015
    Assignee: SK Hynix Inc.
    Inventor: Sang Soo Lee
  • Patent number: 9059319
    Abstract: Embodiments of the invention provide an integrated circuit for an embedded dynamic random access memory (eDRAM), a semiconductor-on-insulator (SOI) wafer in which such an integrated circuit may be formed, and a method of forming an eDRAM in such an SOI wafer.
    Type: Grant
    Filed: January 25, 2010
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, John E. Barth, Jr., Herbert L. Ho, Edward J. Nowak, Wayne Trickle
  • Patent number: 9048142
    Abstract: The degree of integration of a semiconductor device is enhanced and the storage capacity per unit area is increased. The semiconductor device includes a first transistor provided in a semiconductor substrate and a second transistor provided over the first transistor. In addition, an upper portion of a semiconductor layer of the second transistor is in contact with a wiring, and a lower portion thereof is in contact with a gate electrode of the first transistor. With such a structure, the wiring and the gate electrode of the first transistor can serve as a source electrode and a drain electrode of the second transistor, respectively. Accordingly, the area occupied by the semiconductor device can be reduced.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: June 2, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Publication number: 20150145047
    Abstract: A method and circuit for implementing an enhanced transistor topology with a buried field effect transistor (FET) utilizing the drain of a FinFET as the gate of the new buried FET and a design structure on which the subject circuit resides are provided. A drain area of the fin area of a FinFET over a buried dielectric layer provides both the drain of the FinFET as well as the gate node of a second field effect transistor. This second field effect transistor is buried in the carrier semiconductor substrate under the buried dielectric layer.
    Type: Application
    Filed: November 27, 2013
    Publication date: May 28, 2015
    Applicant: International Business Machines Corporation
    Inventors: Karl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann, Kelly L. Williams
  • Patent number: 9035296
    Abstract: A thin film transistor includes a semiconductor layer disposed on a base substrate and including an oxide semiconductor material, a source electrode and a drain electrode, which respectively extend from opposing ends of the semiconductor layer, a plurality of low carrier concentration areas respectively disposed between the source electrode and the semiconductor layer and between the drain electrode and the semiconductor layer, a gate insulating layer disposed on the semiconductor layer, and a gate electrode disposed on the gate insulating layer.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: May 19, 2015
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Seohong Jung, Sun Hee Lee, Seung-Hwan Cho, Myounggeun Cha, Yoonho Khang, Youngki Shin
  • Patent number: 9029950
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a substrate, a first source/drain region, a second source/drain region, a first stack structure and a second stack structure. The first source/drain region is formed in the substrate. The second source/drain region is formed in the substrate. The first stack structure is on the substrate between the first source/drain region and the second source/drain region. The first stack structure comprises a first dielectric layer and a first conductive layer on the first dielectric layer. The second stack structure is on the first stack structure. The second stack structure comprises a second dielectric layer and a second conductive layer on the second dielectric layer.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: May 12, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Chien-Wen Chu, Wing-Chor Chan, Shyi-Yuan Wu
  • Publication number: 20150111349
    Abstract: A structure comprises a semiconductor substrate, a semiconductor-on-insulator region and a bulk region. The semiconductor-on-insulator region comprises a first semiconductor region, a dielectric layer provided between the semiconductor substrate and the first semiconductor region, and a first transistor comprising an active region provided in the first semiconductor region. The dielectric layer provides electrical isolation between the first semiconductor region and the semiconductor substrate. The bulk region comprises a second semiconductor region provided directly on the semiconductor substrate.
    Type: Application
    Filed: December 22, 2014
    Publication date: April 23, 2015
    Inventors: Stefan Flachowsky, Matthias Kessler, Jan Hoentschel
  • Publication number: 20150091090
    Abstract: A semiconductor device structure and a method of fabricating a semiconductor device structure are provided. A first device layer is formed over a substrate, where an alignment structure is patterned in the first device layer. A dielectric layer is provided over the first device layer. The dielectric layer is patterned to include an opening over the alignment structure. A second device layer is formed over the dielectric layer. The second device layer is patterned using a mask layer, where the mask layer includes a structure that is aligned relative to the alignment structure. The alignment structure is visible via the opening during the patterning of the second device layer.
    Type: Application
    Filed: October 2, 2013
    Publication date: April 2, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: YASUTOSHI OKUNO, YI-TANG LIN
  • Patent number: 8994025
    Abstract: The present invention relates to a visible ray sensor and a light sensor capable of improving photosensitivity by preventing photodegradation. The visible ray sensor may include: a substrate, a light blocking member formed on the substrate, and a visible ray sensing thin film transistor formed on the light blocking member. The light blocking member may be made of a transparent electrode, a band pass filter, or an opaque metal.
    Type: Grant
    Filed: December 28, 2010
    Date of Patent: March 31, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sang-Youn Han, Jun-Ho Song, Kyung-Sook Jeon, Mi-Seon Seo, Sung-Hoon Yang, Suk-Won Jung, Seung Mi Seo
  • Patent number: 8975124
    Abstract: One or more embodiments of the disclosed technology provide a thin film transistor, an array substrate and a method for preparing the same. The thin film transistor comprises a base substrate, and a gate electrode, a gate insulating layer, an active layer, an ohmic contact layer, a source electrode, a drain electrode and a passivation layer prepared on the base substrate in this order. The active layer is formed of microcrystalline silicon, and the active layer comprises an active layer lower portion and an active layer upper portion, and the active layer lower portion is microcrystalline silicon obtained by using hydrogen plasma to treat at least two layers of amorphous silicon thin film prepared in a layer-by-layer manner.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: March 10, 2015
    Assignees: Boe Technology Group Co., Ltd., Beijing Asahi Glass Electronics Co., Ltd.
    Inventors: Xueyan Tian, Chunping Long, Jiangfeng Yao
  • Patent number: 8975707
    Abstract: A region for substrate potential is formed of an n-type well at a position in the direction of a channel length relative to the gate electrode and the position is between drain regions in the direction of a channel width. An n-type of a contact region with a higher concentration of n-type impurity than that of the region is provided in the region. The contact region is arranged away from the drain regions with a distance to obtain a desired breakdown voltage of PN-junction between the region and the drain region.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: March 10, 2015
    Assignee: Ricoh Company, Ltd.
    Inventor: Masaya Ohtsuka
  • Patent number: 8951901
    Abstract: In sophisticated semiconductor devices, the encapsulation of sensitive gate materials, such as a high-k dielectric material and a metal-containing electrode material, which are provided in an early manufacturing stage may be achieved by forming an undercut gate configuration. To this end, a wet chemical etch sequence is applied after the basic patterning of the gate layer stack, wherein at least ozone-based and hydrofluoric acid-based process steps are performed in an alternating manner, thereby achieving a substantially self-limiting removal behavior.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: February 10, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Sven Beyer, Berthold Reimer, Falk Graetsch
  • Publication number: 20150037941
    Abstract: A conductive strap structure in lateral contact with a top semiconductor layer is formed on an inner electrode of a deep trench capacitor. A cavity overlying the conductive strap structure is filled with a dielectric material to form a dielectric capacitor cap having a top surface that is coplanar with a topmost surface of an upper pad layer. A portion of the upper pad layer is removed to define a line cavity. A fin-defining spacer comprising a material different from the material of the dielectric capacitor cap and the upper pad layer is formed around the line cavity by deposition of a conformal layer and an anisotropic etch. The upper pad layer is removed, and the fin-defining spacer is employed as an etch mask to form a semiconductor fin that laterally contacts the conductive strap structure. An access finFET is formed employing two parallel portions of the semiconductor fin.
    Type: Application
    Filed: October 17, 2014
    Publication date: February 5, 2015
    Inventors: Josephine B. Chang, Babar A. Khan, Paul C. Parries, Xinhui Wang
  • Patent number: 8906755
    Abstract: A hybrid integrated circuit device includes a semiconductor-on-insulator substrate having a base substrate, a semiconductor layer and a dielectric layer disposed therebetween, the base substrate being reduced in thickness. First devices are formed in the semiconductor layer, the first devices being connected to first metallizations on a first side of the dielectric layer. Second devices are formed in the base substrate, the second devices being connected to second metallizations formed on a second side of the dielectric layer opposite the first side. A through via connection is configured to connect the first metallizations to the second metallizations through the dielectric layer. Pixel circuits and methods are also disclosed.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: December 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Tak H. Ning, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 8907341
    Abstract: A thin-film semiconductor device includes a semiconductor device part and a capacitor part. The semiconductor device part includes: a light-transmitting first gate electrode; a light-shielding second gate electrode; a first insulating layer; a semiconductor layer; a second insulating layer; and a source electrode and a drain electrode. The capacitor part includes: a first capacitor electrode made of a light-transmitting conductive material; a dielectric layer; and a second capacitor electrode. The second gate electrode, the semiconductor layer, and the second insulating layer have outlines that are coincident with one another in a top view.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: December 9, 2014
    Assignee: Panasonic Corporation
    Inventors: Arinobu Kanegae, Takahiro Kawashima
  • Patent number: 8900898
    Abstract: An organic light-emitting display includes a substrate including a pixel region and a transistor region; a first transparent electrode and a second transparent electrode formed over the pixel region and the transistor region of the substrate, respectively; a gate electrode formed over the second transparent electrode; a gate insulating film formed over the gate electrode; a semiconductor layer formed over the gate insulating film; a source and drain electrode having an end connected to the semiconductor layer and the other end connected to the first transparent electrode; a pixel defining layer disposed over the source and drain electrode to cover the source and drain electrode and having an opening disposed over the first transparent electrode; a light-blocking layer formed over the pixel defining layer; and an organic light-emitting layer formed over the first transparent electrode.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: December 2, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventor: Yong-Woo Park
  • Patent number: 8877521
    Abstract: A manufacturing method for a semiconductor device, the method including forming a thin film transistor by forming a polysilicon thin film on an insulating substrate, forming a gate electrode via a gate insulating film, and forming source/drain regions and a channel region by ion implantation in the polysilicon thin film by using the gate electrode as a mask, forming an interconnection layer on an interlayer dielectric film covering this thin film transistor and forming a first contact to be connected to the thin film transistor through the interlayer dielectric film, forming a silicon hydronitride film on the interlayer dielectric film so as to cover the interconnection layer, forming a lower electrode on this silicon hydronitride film and forming a second contact to be connected to the interconnection layer through the silicon hydronitride film, and forming a ferroelectric layer on the lower electrode.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: November 4, 2014
    Assignee: Gold Charm Limited
    Inventor: Hiroshi Tanabe
  • Patent number: 8846461
    Abstract: A composite semiconductor structure and method of forming the same are provided. The composite semiconductor structure includes a first silicon-containing compound layer comprising an element selected from the group consisting essentially of germanium and carbon; a silicon layer on the first silicon-containing compound layer, wherein the silicon layer comprises substantially pure silicon; and a second silicon-containing compound layer comprising the element on the silicon layer. The first and the second silicon-containing compound layers have substantially lower silicon concentrations than the silicon layer. The composite semiconductor structure may be formed as source/drain regions of metal-oxide-semiconductor (MOS) devices.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Hsin Lin, Weng Chang, Chien-Chang Su, Kuan-Yu Chen, Hsueh-Chang Sung, Ming-Hua Yu
  • Patent number: 8835907
    Abstract: The present invention is to provide a semiconductor device in which the step can be simplified, the manufacturing cost can be suppressed, and the decrease in yield can be suppressed. A semiconductor device of the present invention includes an antenna, a storage element, and a transistor, wherein a conductive layer serving as an antenna is provided in the same layer as a conductive layer of the transistor or the storage element. This characteristic makes it possible to omit an independent step of forming the conductive layer serving as an antenna and to conduct the step of forming the conductive layer serving as an antenna at the same time as the step of forming a conductive layer of another element. Therefore, the manufacturing step can be simplified, the manufacturing cost can be suppressed, and the decrease in yield can be suppressed.
    Type: Grant
    Filed: January 20, 2006
    Date of Patent: September 16, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshitaka Moriya, Yasuko Watanabe, Yasuyuki Arai
  • Publication number: 20140231890
    Abstract: A method of forming a FinFET structure having a metal-insulator-metal capacitor. Silicon fins are formed on a semiconductor substrate followed by formation of the metal-insulator-metal capacitor on the silicon fins by depositing sequential layers of a first layer of titanium nitride, a dielectric layer and a second layer of titanium nitride. A polysilicon layer is deposited over the metal-insulator-metal capacitor followed by etching back the polysilicon layer and the metal-insulator-metal capacitor layers from ends of the silicon fins so that the first and second ends of the silicon fins protrude from the polysilicon layer. A spacer may be formed on surfaces facing the ends of the silicon fins followed by the formation of epitaxial silicon over the ends of the silicon fins. Also disclosed is a FinFET structure having a metal-insulator-metal capacitor.
    Type: Application
    Filed: February 15, 2013
    Publication date: August 21, 2014
    Applicant: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Effendi Leobandung, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 8785240
    Abstract: Provided is a method of producing a light-emitting apparatus having a field effect transistor for driving an organic EL device, the field effect transistor including an oxide semiconductor containing at least one element selected from In and Zn, the method including the steps of: forming a field effect transistor on a substrate; forming an insulating layer; forming a lower electrode on the insulating layer; forming an organic layer for constituting an organic EL device on the lower electrode; forming an upper electrode on the organic layer; and after the step of forming the semiconductor layer of the field effect transistor and before the step of forming the organic layer, performing heat treatment such that an amount of a component that is desorbable as H2O from the field effect transistor during the step of forming the organic layer is less than 10?5 g/m2.
    Type: Grant
    Filed: April 3, 2008
    Date of Patent: July 22, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tomohiro Watanabe
  • Publication number: 20140183538
    Abstract: There are provided a back plane for a flat panel display and a method of manufacturing the back plane, and more particularly, a back plane for an organic light-emitting display device, which enables front light-emitting, and a method of manufacturing the back plane. The back plane for a flat panel display includes: a substrate; a gate electrode on the substrate; a first capacitor on the substrate, the first capacitor comprising a first electrode, an insulation pattern layer on the first electrode, and a second electrode on the insulation pattern layer; a first insulation layer on the substrate to cover the gate electrode and the first capacitor; an active layer on the first insulation layer to correspond to the gate electrode; and a source electrode and a drain electrode on the substrate to contact a portion of the active layer.
    Type: Application
    Filed: August 23, 2013
    Publication date: July 3, 2014
    Applicant: Samsung Display Co., Ltd
    Inventors: Min-Kyu Kim, Yeon-Gon Mo
  • Patent number: 8766273
    Abstract: It is possible to manufacture a large-size, high-accuracy organic EL display using a plastic substrate and an organic EL display using a roll-shaped long plastic substrate. The organic EL display includes an organic EL device A having at least a lower electrode 300, an organic layer including at least a light emitting layer, and an upper electrode 305 and a thin film transistor B on a transparent plastic substrate 100, a source electrode or drain electrode of the thin film transistor B is connected to the lower electrode 300, the plastic substrate 100 has a gas barrier layer 101a, the thin film transistor B is formed on the gas barrier layer 101a, the thin film transistor B includes an active layer 203 containing a non-metallic element which a mixture of oxygen (O) and nitrogen (N) and has a ratio of N to O (N number density/O number density) from 0 to 2, and the organic EL device A is formed at least on the gas barrier layer 101a or one the thin film transistor B.
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: July 1, 2014
    Assignees: Sumitomo Chemical Company, Limited, Sumitomo Bakelite Co., Ltd.
    Inventors: Shigeyoshi Otsuki, Toshimasa Eguchi, Shinya Yamaguchi, Mamoru Okamoto
  • Patent number: 8765534
    Abstract: A semiconductor apparatus includes a first substrate and a second substrate located over a first portion of the first substrate and separated from the first substrate by a buried layer. The semiconductor apparatus also includes an epitaxial layer located over a second portion of the first substrate and isolated from the second substrate. The semiconductor apparatus further includes a first transistor formed at least partially in the second substrate and a second transistor formed at least partially in or over the epitaxial layer. The second substrate and the epitaxial layer have bulk properties with different electron and hole mobilities. At least one of the transistors is configured to receive one or more signals of at least about 5V. The first substrate could have a first crystalline orientation, and the second substrate could have a second crystalline orientation.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: July 1, 2014
    Assignee: National Semiconductor Corporation
    Inventor: Alexander H. Owens
  • Patent number: 8766255
    Abstract: A semiconductor device in which improvement of a property of holding stored data can be achieved. Further, power consumption of a semiconductor device is reduced. A transistor in which a wide-gap semiconductor material capable of sufficiently reducing the off-state current of a transistor (e.g., an oxide semiconductor material) in a channel formation region is used and which has a trench structure, i.e., a trench for a gate electrode and a trench for element isolation, is provided. The use of a semiconductor material capable of sufficiently reducing the off-state current of a transistor enables data to be held for a long time. Further, since the transistor has the trench for a gate electrode, the occurrence of a short-channel effect can be suppressed by appropriately setting the depth of the trench even when the distance between the source electrode and the drain electrode is decreased.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: July 1, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsuo Isobe, Toshihiko Saito, Kiyoshi Kato
  • Publication number: 20140167167
    Abstract: An integrated cell may include an nMOS transistor, and an pMOS transistor. The cell may be produced in fully depleted silicon-on-insulator technology, and it is possible for the substrates of the transistors of the cell to be biased with the same adjustable biasing voltage.
    Type: Application
    Filed: December 4, 2013
    Publication date: June 19, 2014
    Applicant: STMICROELECTRONICS SA
    Inventors: Frederic HASBANI, Eric Remond
  • Patent number: 8741743
    Abstract: A method for making a semiconductor device is provided which comprises (a) creating a first mask for the epitaxial growth of features in a semiconductor device, said first mask defining a set of epitaxial tiles (219); (b) creating a second mask for defining the active region of the semiconductor device, said second mask defining a set of active tiles (229); and (c) using the first and second masks to create a semiconductor device.
    Type: Grant
    Filed: January 5, 2007
    Date of Patent: June 3, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Omar Zia, Nigel Cave, Venkat Kolagunta, Ruiqi Tian, Edward O. Travis
  • Patent number: 8742412
    Abstract: A thin film transistor includes a gate electrode, a gate insulation layer, a channel layer, a source electrode, and a drain electrode formed on a substrate, in which: the channel layer contains indium, germanium, and oxygen; and the channel layer has a compositional ratio expressed by In/(In+Ge) of 0.5 or more and 0.97 or less.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: June 3, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Amita Goyal, Naho Itagaki, Tatsuya Iwasaki
  • Patent number: 8722471
    Abstract: A method for forming a via connecting a first upper level layer to a second lower level layer, both layers being surrounded with an insulating material, the method including the steps of: a) forming an opening to reach an edge of the first layer, the opening laterally continuing beyond said edge; b) forming a layer of a protection material on said edge only; c) deepening said opening by selectively etching the insulating material to reach the second lower level layer; and d) filling the opening with at least one conductive contact material.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: May 13, 2014
    Assignees: STMicroelectronics S.A., Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Perrine Batude, Yves Morand
  • Publication number: 20140124863
    Abstract: Methods and structures for forming a localized silicon-on-insulator (SOI) finFET are disclosed. Fins are formed on a bulk substrate. Nitride spacers protect the fin sidewalls. A shallow trench isolation region is deposited over the fins. An oxidation process causes oxygen to diffuse through the shallow trench isolation region and into the underlying silicon. The oxygen reacts with the silicon to form oxide, which provides electrical isolation for the fins. The shallow trench isolation region is in direct physical contact with the fins and/or the nitride spacers that are disposed on the fins. Structures comprising bulk-type fins, SOI-type fins, and planar regions are also disclosed.
    Type: Application
    Filed: February 20, 2013
    Publication date: May 8, 2014
    Applicant: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ali Khakifirooz, Kern Rim, Ramachandra Divakaruni
  • Publication number: 20140120667
    Abstract: A method of fabricating a monolithic integrated circuit using a single substrate, the method including forming a first semiconductor layer from a substrate, fabricating semiconductor devices on the substrate, fabricating at least one metal wiring layer on the semiconductor devices, forming at least one dielectric layer in integral contact with the at least one metal wiring layer, forming contact openings through the at least one dielectric layer to expose regions of the at least one metal wiring layer, integrally forming, from the substrate, a second semiconductor layer on the dielectric layer, and in contact with the at least one metal wiring layer through the contact openings, and forming a plurality of non-linear semiconductor devices in said second semiconductor layer.
    Type: Application
    Filed: January 6, 2014
    Publication date: May 1, 2014
    Applicant: International Business Machines Corporation
    Inventors: Stephen M Gates, Daniel C. Edelstein, Satyanarayana V. Nitta
  • Patent number: 8710591
    Abstract: Provided are a semiconductor chip including a TSV passing through a transistor, and a stack module and a memory card using such a semiconductor chip. The semiconductor chip may include a semiconductor layer that has a first surface and a second surface opposite to each other. A conductive layer may be disposed on the first surface of the semiconductor layer. A TSV may pass through the semiconductor layer and the conductive layer. A side wall insulating layer may surround a side wall of the TSV in order to electrically insulate the semiconductor layer and the conductive layer from the TSV.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: April 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyong-ryol Hwang, Ho-cheol Lee, Byong-wook Na
  • Patent number: 8674371
    Abstract: The protective circuit is formed using a non-linear element which includes a gate insulating film covering a gate electrode; a first wiring layer and a second wiring layer which are over the gate insulating film and whose end portions overlap with the gate electrode; and an oxide semiconductor layer which is over the gate electrode and in contact with the gate insulating film and the end portions of the first wiring layer and the second wiring layer. The gate electrode of the non-linear element and a scan line or a signal line is included in a wiring, the first or second wiring layer of the non-linear element is directly connected to the wiring so as to apply the potential of the gate electrode.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: March 18, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto, Shigeki Komori, Hideki Uochi, Tomoya Futamura, Takahiro Kasahara
  • Patent number: 8673674
    Abstract: An organic light emitting diode (OLED) display device and a method of fabricating the same is provided. Semiconductor layers of driving transistors located in two adjacent pixels included in the OLED display device may extend in different lengthwise directions. Thus, striped stains of the OLED display device can be improved.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: March 18, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hong-Ro Lee, Sang-Jo Lee
  • Patent number: 8652887
    Abstract: The present invention relates to a method for providing a Silicon-On-Insulator (SOI) stack that includes a substrate layer, a first oxide layer on the substrate layer and a silicon layer on the first oxide layer (BOX layer). The method includes providing at least one first region of the SOI stack wherein the silicon layer is thinned by thermally oxidizing a part of the silicon layer and providing at least one second region of the SOI stack wherein the first oxide layer (BOX layer) is thinned by annealing.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: February 18, 2014
    Assignee: Soitec
    Inventors: Bich-Yen Nguyen, Carlos Mazure, Richard Ferrant
  • Patent number: 8653520
    Abstract: An object is to provide a semiconductor device having a novel structure in which a transistor including an oxide semiconductor and a transistor including a semiconductor material other than an oxide semiconductor are stacked. The semiconductor device includes a first transistor, an insulating layer over the first transistor, and a second transistor over the insulating layer. In the semiconductor device, the first transistor includes a first channel formation region, the second transistor includes a second channel formation region, the first channel formation region includes a semiconductor material different from a semiconductor material of the second channel formation region, and the insulating layer includes a surface whose root-mean-square surface roughness is less than or equal to 1 nm.
    Type: Grant
    Filed: February 4, 2011
    Date of Patent: February 18, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Teruyuki Fujii, Ryota Imahayashi, Shinya Sasagawa, Motomu Kurata, Fumika Taguchi
  • Patent number: 8642408
    Abstract: A semiconductor device and method is disclosed. One embodiment provides a method comprising placing a first semiconductor chip on a carrier. After placing the first semiconductor chip on the carrier, an electrically insulating layer is deposited on the carrier. A second semiconductor chip is placed on the electrically insulating layer.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: February 4, 2014
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Joachim Mahler, Bernd Rakow, Reimund Engl, Rupert Fischer
  • Publication number: 20140029077
    Abstract: A display device provided with an MEMS light valve, comprising: a substrate, a fixed optical grating located on the substrate, an MEMS light valve for controlling the opening and closing of the fixed optical grating, the MEMS light valve comprises a first light valve and a second light valve; the opening and closing of the fixed optical grating is controlled via controlling the movement of the first light valve and the second light valve, and the moving directions of the first light valve and the second light valve are opposite. Also disclosed is a method for forming a display device provided with an MEMS light valve. Thus the sensitivity of the MEMS light valve is improved.
    Type: Application
    Filed: December 29, 2011
    Publication date: January 30, 2014
    Applicant: LEXVU OPTO MICROELECTRONICS TECHNOLOGY (SHANGHAI) LTD
    Inventors: Jianhong Mao, Deming Tang
  • Patent number: 8637356
    Abstract: A non-volatile bistable nano-electromechanical switch is provided for use in memory devices and microprocessors. The switch employs carbon nanotubes as the actuation element. A method has been developed for fabricating nanoswitches having one single-walled carbon nanotube as the actuator. The actuation of two different states can be achieved using the same low voltage for each state.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: January 28, 2014
    Assignee: Northeastern University
    Inventors: Sivasubramanian Somu, Ahmed Busnaina, Nicol McGruer, Peter Ryan, George G. Adams, Xugang Xiong, Taehoon Kim
  • Publication number: 20140017858
    Abstract: An integrated circuit includes a transistor, an UTBOX buried insulating layer disposed under it, a ground plane disposed under the layer, a well disposed under the plane, a first trench made at a periphery of the transistor and extending through the layer and into the well, a substrate situated under the well, a p-n diode made on a side of the transistor and comprising first and second zones of opposite doping, the first zone being configured for electrical connection to a first electrode of the transistor, wherein first and second zones are coplanar with the plane, a second trench for separating the first and second zones, the second trench extending through the layer into the plane and until a depth less than an interface between the plane and the well, and a third zone under the second trench forming a junction between the zones.
    Type: Application
    Filed: July 2, 2013
    Publication date: January 16, 2014
    Inventors: Claire Fenouillet-Beranger, Pascal Fonteneau
  • Patent number: 8624321
    Abstract: A thin film transistor is provided, which includes a gate insulating layer covering a gate electrode, a microcrystalline semiconductor layer provided over the gate insulating layer, an amorphous semiconductor layer overlapping the microcrystalline semiconductor layer and the gate insulating layer, and a pair of impurity semiconductor layers which are provided over the amorphous semiconductor layer and to which an impurity element imparting one conductivity type is added to form a source region and a drain region. The gate insulating layer has a step adjacent to a portion in contact with an end portion of the microcrystalline semiconductor layer. A second thickness of the gate insulating layer in a portion outside the microcrystalline semiconductor layer is smaller than a first thickness thereof in a portion in contact with the microcrystalline semiconductor layer.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: January 7, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yoshiyuki Kurokawa, Hiromichi Godo, Hidekazu Miyairi
  • Patent number: 8598581
    Abstract: A method for manufacturing a thin film transistor array panel includes; forming a gate line including a gate electrode and a height increasing member on a substrate, forming a gate insulating layer on the gate line and the height increasing member, forming a semiconductor, a data line including a source electrode, and a drain electrode facing the source electrode and overlapping at least a portion of the height increasing member on the gate insulating layer, forming a first insulating layer on the gate insulating layer, a data line and the drain electrode, forming a light-blocking member on a portion of the first insulating layer corresponding to the gate line and the data line, forming a color filter in an area bound by the light-blocking member, forming a second insulating layer on the light-blocking member and the color filter, and patterning the second insulating layer, the light-blocking member or the color filter, and the first insulating layer to form a contact hole exposing a portion of the drain elec
    Type: Grant
    Filed: May 4, 2009
    Date of Patent: December 3, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jang-Soo Kim, Jae-Hyoung Youn, Sang-Soo Kim, Dong-Gyu Kim
  • Patent number: 8563341
    Abstract: The present invention discloses a thin film transistor array substrate and a manufacturing method for the same. A transparent conductive layer and a first metal layer are deposited on a substrate, and a multi-tone mask is utilized to form a gate electrode and a common electrode. A gate insulative layer and a semi-conductive layer are deposited on the substrate with the gate electrode and the common electrode, and the semi-conductive layer is patterned by a second mask to retain a region of the semi-conductive layer that is there-above the gate electrode. A second metal layer is deposited on the substrate with the gate insulative layer along with the retained semi-conductive layer, and the second metal layer is patterned by a third mask to form a source electrode, a drain electrode, and a pixel electrode. The present invention provides a simple manufacturing method.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: October 22, 2013
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventors: Pei Jia, Liu-yang Yang