Abstract: An integrated circuit device includes an embedded insulation layer, a semiconductor layer on the embedded insulation layer, the semiconductor layer having a main surface, and a plurality of fin-type active areas protruding from the main surface to extend in a first horizontal direction and in parallel with one another, a separation insulation layer separating the semiconductor layer into at least two element regions adjacent to each other in a second horizontal direction intersecting the first horizontal direction, source/drain regions on the plurality of fin-type active areas, a first conductive plug on and electrically connected to the source/drain regions, a buried rail electrically connected to the first conductive plug while penetrating through the separation insulation layer and the semiconductor layer, and a power delivery structure arranged in the embedded insulation layer, the power delivery structure being in contact with and electrically connected to the buried rail.

Abstract: A semiconductor structure includes a substrate, a buried oxide layer formed in the substrate and near a surface of the substrate, a gate dielectric layer formed on the substrate and covering the buried oxide layer, a gate structure formed on the gate dielectric layer and overlapping the buried oxide layer, and a source region and a drain region formed in the substrate and at two sides of the gate structure.

Abstract: Disclosed herein are methods for forming MOSFETs. In some embodiments, a method may include providing a device structure including a plurality of trenches, forming a gate spacer layer over the device structure, and removing the gate spacer layer from a top surface of the device structure and from a first section of each of the plurality of trenches, wherein a portion of the gate spacer layer remains along a second section of each of the plurality of trenches. The method may further include forming a gate oxide layer along the first section of each of the plurality of trenches and along the portion of the gate spacer layer.

Abstract: Methods of self-aligned multiple patterning. A hardmask is deposited over an interlayer dielectric layer. A mandrel is formed over the hardmask. A block mask is formed that covers a first lengthwise section of the mandrel and that exposes second and third lengthwise sections of the mandrel. After forming the block mask, the second and third lengthwise sections of the mandrel are removed to define a pattern including respective first and second mandrel lines that are separated from each other by the first lengthwise section of the mandrel. The first mandrel line and the second mandrel line expose respective portions of the hardmask, and the first lengthwise section of the mandrel line covers another portion of the hardmask. The pattern is transferred to the hardmask with an etching process, and subsequently transferred to the interlayer dielectric layer with another etching process.

Abstract: A device assembly structure includes a first device and at least one second device. The first device has a first active surface and a first backside surface opposite to the first active surface, and includes a plurality of first electrical contacts disposed adjacent to the first active surface. The second device has a second active surface and a second backside surface opposite to the second active surface, and includes a plurality of second electrical contacts disposed adjacent to the second active surface. The second active surface of the second device faces the first active surface of the first device, the second electrical contacts of the second device are electrically connected to the first electrical contacts of the first device, and a thickness of the second device is less than or equal to one fifth of a thickness of the first device.

Abstract: Field effect transistors for an SRAM cell can be formed employing n-doped gate electrode portions for p-type pull-up transistors. The SRAM cell includes a first series connection of a first p-type pull-up transistor and a first n-type pull-down transistor located between a power supply source and electrical ground, and a second series connection of a second p-type pull-up transistor and a second n-type pull-down transistor located between the power supply source and the electrical ground. Each gate electrode of the SRAM cell can include a respective n-doped gate electrode portion.

Abstract: An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. The drain connecting segments may also extend beyond gate connecting segments by a distance greater than one-third of the width of the gate connecting segments. A process of forming an integrated circuit containing an array of SRAM cells with T-shaped contacts in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. A process may also form the drain connecting segments to extend beyond gate connecting segments by greater than one-third of the width of the gate connecting segments.

Abstract: The semiconductor device includes: a transistor having an oxide semiconductor layer; and a logic circuit formed using a semiconductor material other than an oxide semiconductor. One of a source electrode and a drain electrode of the transistor is electrically connected to at least one input of the logic circuit, and at least one input signal is applied to the logic circuit through the transistor. The off-current of the transistor is preferably 1×10?13 A or less.

Abstract: The semiconductor device includes a driver circuit portion including a driver circuit and a pixel portion including a pixel. The pixel includes a gate electrode layer having a light-transimitting property, a gate insulating layer, a source electrode layer and a drain electrode layer each having a light-transmitting property provided over the gate insulating layer, an oxide semiconductor layer covering top surfaces and side surfaces of the source electrode layer and the drain electrode layer and provided over the gate electrode layer with the gate insulating layer therebetween, a conductive layer provided over part of the oxide semiconductor layer and having a lower resistance than the source electrode layer and the drain electrode layer, and an oxide insulating layer in contact with part of the oxide semiconductor layer.

Abstract: An SOI or PSOI device including a device structure having a plurality of doped semiconductor regions. One or more of the doped semiconductor regions is in electrical communication with one or more electrical terminals. The device further includes an insulator layer located between a bottom surface of the device structure and a handle wafer. The device has an insulator trench structure located between a side surface of the device structure and a lateral semiconductor region located laterally with respect to the device structure. The insulator layer and the insulator trench structure are configured to insulate the device structure from the handle wafer and the lateral semiconductor region, and the insulator trench structure includes a plurality of insulator trenches.

Abstract: In certain aspects, an apparatus comprises an SOI MOSFET having a diffusion region as a source or a drain on a back insulating layer, wherein the diffusion region has a front diffusion side and a back diffusion side opposite to the front diffusion side; a silicide layer on the front diffusion side having a back silicide side facing the diffusion region and a front silicide side opposite to the back silicide side; and a backside contact connected to the silicide layer, wherein at least a portion of the backside contact is in the back insulating layer.

Abstract: Disclosed is a semiconductor device capable of functioning as a memory device. The memory device comprises a plurality of memory cells, and each of the memory cells contains a first transistor and a second transistor. The first transistor is provided over a substrate containing a semiconductor material and has a channel formation region in the substrate. The second transistor has an oxide semiconductor layer. The gate electrode of the first transistor and one of the source and drain electrodes of the second transistor are electrically connected to each other. The extremely low off current of the second transistor allows the data stored in the memory cell to be retained for a significantly long time even in the absence of supply of electric power.

Abstract: A method for making a FET transistor, including the following steps: making, on a crystalline semiconducting layer, a layer of gate dielectric on which a gate conducting layer is arranged, etching the conducting layer such that a remaining portion of this layer fully covers a first semiconducting portion forming an active zone and a second semiconducting portion adjacent to the active zone, implanting atoms and/or dopants in the semiconducting layer, thus amorphizing the semiconductor around the first portion and that of the second portion, etching the remaining portion of the conducting layer and of the dielectric layer according to a gate pattern partially covering the first portion and the second portion, forming the gate and a gate overflow, etching the amorphous semiconductor.

Abstract: A microelectronic assembly may include a substrate including a rigid dielectric layer having electrically conductive elements, a microelectronic element having a plurality of contacts exposed at a face thereof, and conductive vias extending through a compliant dielectric layer overlying the rigid dielectric layer. The vias electrically connect the substrate contacts respectively to the conductive elements, and the substrate contacts are joined respectively to the contacts of the microelectronic element. The vias, compliant layer and substrate contacts are adapted to appreciably relieve stress at the substrate contacts associated with differential thermal contact and expansion of the assembly.

Abstract: A method to form a 3D integrated circuit, the method including: fabricating two or more devices; connecting the devices together to form the 3D integrated circuit, where at least one of the devices has at least one unused designated dice line and at least one of the devices is a configurable device; and interconnecting at least two of the devices using Through Silicon Vias.

Abstract: A semiconductor device comprising first layer comprising multiplicity of first transistors and, second layer comprising multiplicity of second transistors and, at least one function constructed by the first transistors are structure so it could be replaced by a function constructed by the second transistors.

Abstract: An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide layer overlying the channel; and a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which a stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which a stoichiometric composition of the second oxynitride layer results in it being trap dense. In one embodiment, the device comprises a non-planar transistor including a gate having multiple surfaces abutting the channel, and the gate comprises the tunnel oxide layer and the multi-layer charge storing layer.

Abstract: In a miniaturized transistor, a gate insulating layer is required to reduce its thickness; however, in the case where the gate insulating layer is a single layer of a silicon oxide film, a physical limit on thinning of the gate insulating layer might occur due to an increase in tunneling current, i.e. gate leakage current. With the use of a high-k film whose relative permittivity is higher than or equal to 10 is used for the gate insulating layer, gate leakage current of the miniaturized transistor is reduced. With the use of the high-k film as a first insulating layer whose relative permittivity is higher than that of a second insulating layer in contact with an oxide semiconductor layer, the thickness of the gate insulating layer can be thinner than a thickness of a gate insulating layer considered in terms of a silicon oxide film.

Abstract: The semiconductor device includes: a transistor having an oxide semiconductor layer; and a logic circuit formed using a semiconductor material other than an oxide semiconductor. One of a source electrode and a drain electrode of the transistor is electrically connected to at least one input of the logic circuit, and at least one input signal is applied to the logic circuit through the transistor. The off-current of the transistor is preferably 1×10?13 A or less.

Abstract: Disclosed herein is a fabrication method of a semiconductor device to order to increase an operation liability of the semiconductor device. A method for fabricating a semiconductor device comprises forming a buried-type wordline in an active region defined on a SOI substrate, forming a silicon connection region for connecting an upper silicon layer to a lower silicon layer between neighboring buried type wordlines, and recovering the upper silicon layer on the silicon connection region.

Abstract: Embodiments of the invention provide an integrated circuit for an embedded dynamic random access memory (eDRAM), a semiconductor-on-insulator (SOI) wafer in which such an integrated circuit may be formed, and a method of forming an eDRAM in such an SOI wafer.

Abstract: The degree of integration of a semiconductor device is enhanced and the storage capacity per unit area is increased. The semiconductor device includes a first transistor provided in a semiconductor substrate and a second transistor provided over the first transistor. In addition, an upper portion of a semiconductor layer of the second transistor is in contact with a wiring, and a lower portion thereof is in contact with a gate electrode of the first transistor. With such a structure, the wiring and the gate electrode of the first transistor can serve as a source electrode and a drain electrode of the second transistor, respectively. Accordingly, the area occupied by the semiconductor device can be reduced.

Abstract: A method and circuit for implementing an enhanced transistor topology with a buried field effect transistor (FET) utilizing the drain of a FinFET as the gate of the new buried FET and a design structure on which the subject circuit resides are provided. A drain area of the fin area of a FinFET over a buried dielectric layer provides both the drain of the FinFET as well as the gate node of a second field effect transistor. This second field effect transistor is buried in the carrier semiconductor substrate under the buried dielectric layer.

Abstract: A thin film transistor includes a semiconductor layer disposed on a base substrate and including an oxide semiconductor material, a source electrode and a drain electrode, which respectively extend from opposing ends of the semiconductor layer, a plurality of low carrier concentration areas respectively disposed between the source electrode and the semiconductor layer and between the drain electrode and the semiconductor layer, a gate insulating layer disposed on the semiconductor layer, and a gate electrode disposed on the gate insulating layer.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a substrate, a first source/drain region, a second source/drain region, a first stack structure and a second stack structure. The first source/drain region is formed in the substrate. The second source/drain region is formed in the substrate. The first stack structure is on the substrate between the first source/drain region and the second source/drain region. The first stack structure comprises a first dielectric layer and a first conductive layer on the first dielectric layer. The second stack structure is on the first stack structure. The second stack structure comprises a second dielectric layer and a second conductive layer on the second dielectric layer.

Abstract: A structure comprises a semiconductor substrate, a semiconductor-on-insulator region and a bulk region. The semiconductor-on-insulator region comprises a first semiconductor region, a dielectric layer provided between the semiconductor substrate and the first semiconductor region, and a first transistor comprising an active region provided in the first semiconductor region. The dielectric layer provides electrical isolation between the first semiconductor region and the semiconductor substrate. The bulk region comprises a second semiconductor region provided directly on the semiconductor substrate.

Abstract: A semiconductor device structure and a method of fabricating a semiconductor device structure are provided. A first device layer is formed over a substrate, where an alignment structure is patterned in the first device layer. A dielectric layer is provided over the first device layer. The dielectric layer is patterned to include an opening over the alignment structure. A second device layer is formed over the dielectric layer. The second device layer is patterned using a mask layer, where the mask layer includes a structure that is aligned relative to the alignment structure. The alignment structure is visible via the opening during the patterning of the second device layer.

Abstract: The present invention relates to a visible ray sensor and a light sensor capable of improving photosensitivity by preventing photodegradation. The visible ray sensor may include: a substrate, a light blocking member formed on the substrate, and a visible ray sensing thin film transistor formed on the light blocking member. The light blocking member may be made of a transparent electrode, a band pass filter, or an opaque metal.

Abstract: One or more embodiments of the disclosed technology provide a thin film transistor, an array substrate and a method for preparing the same. The thin film transistor comprises a base substrate, and a gate electrode, a gate insulating layer, an active layer, an ohmic contact layer, a source electrode, a drain electrode and a passivation layer prepared on the base substrate in this order. The active layer is formed of microcrystalline silicon, and the active layer comprises an active layer lower portion and an active layer upper portion, and the active layer lower portion is microcrystalline silicon obtained by using hydrogen plasma to treat at least two layers of amorphous silicon thin film prepared in a layer-by-layer manner.

Abstract: A region for substrate potential is formed of an n-type well at a position in the direction of a channel length relative to the gate electrode and the position is between drain regions in the direction of a channel width. An n-type of a contact region with a higher concentration of n-type impurity than that of the region is provided in the region. The contact region is arranged away from the drain regions with a distance to obtain a desired breakdown voltage of PN-junction between the region and the drain region.

Abstract: In sophisticated semiconductor devices, the encapsulation of sensitive gate materials, such as a high-k dielectric material and a metal-containing electrode material, which are provided in an early manufacturing stage may be achieved by forming an undercut gate configuration. To this end, a wet chemical etch sequence is applied after the basic patterning of the gate layer stack, wherein at least ozone-based and hydrofluoric acid-based process steps are performed in an alternating manner, thereby achieving a substantially self-limiting removal behavior.

Abstract: A conductive strap structure in lateral contact with a top semiconductor layer is formed on an inner electrode of a deep trench capacitor. A cavity overlying the conductive strap structure is filled with a dielectric material to form a dielectric capacitor cap having a top surface that is coplanar with a topmost surface of an upper pad layer. A portion of the upper pad layer is removed to define a line cavity. A fin-defining spacer comprising a material different from the material of the dielectric capacitor cap and the upper pad layer is formed around the line cavity by deposition of a conformal layer and an anisotropic etch. The upper pad layer is removed, and the fin-defining spacer is employed as an etch mask to form a semiconductor fin that laterally contacts the conductive strap structure. An access finFET is formed employing two parallel portions of the semiconductor fin.

Abstract: A hybrid integrated circuit device includes a semiconductor-on-insulator substrate having a base substrate, a semiconductor layer and a dielectric layer disposed therebetween, the base substrate being reduced in thickness. First devices are formed in the semiconductor layer, the first devices being connected to first metallizations on a first side of the dielectric layer. Second devices are formed in the base substrate, the second devices being connected to second metallizations formed on a second side of the dielectric layer opposite the first side. A through via connection is configured to connect the first metallizations to the second metallizations through the dielectric layer. Pixel circuits and methods are also disclosed.

Abstract: A thin-film semiconductor device includes a semiconductor device part and a capacitor part. The semiconductor device part includes: a light-transmitting first gate electrode; a light-shielding second gate electrode; a first insulating layer; a semiconductor layer; a second insulating layer; and a source electrode and a drain electrode. The capacitor part includes: a first capacitor electrode made of a light-transmitting conductive material; a dielectric layer; and a second capacitor electrode. The second gate electrode, the semiconductor layer, and the second insulating layer have outlines that are coincident with one another in a top view.

Abstract: An organic light-emitting display includes a substrate including a pixel region and a transistor region; a first transparent electrode and a second transparent electrode formed over the pixel region and the transistor region of the substrate, respectively; a gate electrode formed over the second transparent electrode; a gate insulating film formed over the gate electrode; a semiconductor layer formed over the gate insulating film; a source and drain electrode having an end connected to the semiconductor layer and the other end connected to the first transparent electrode; a pixel defining layer disposed over the source and drain electrode to cover the source and drain electrode and having an opening disposed over the first transparent electrode; a light-blocking layer formed over the pixel defining layer; and an organic light-emitting layer formed over the first transparent electrode.

Abstract: A manufacturing method for a semiconductor device, the method including forming a thin film transistor by forming a polysilicon thin film on an insulating substrate, forming a gate electrode via a gate insulating film, and forming source/drain regions and a channel region by ion implantation in the polysilicon thin film by using the gate electrode as a mask, forming an interconnection layer on an interlayer dielectric film covering this thin film transistor and forming a first contact to be connected to the thin film transistor through the interlayer dielectric film, forming a silicon hydronitride film on the interlayer dielectric film so as to cover the interconnection layer, forming a lower electrode on this silicon hydronitride film and forming a second contact to be connected to the interconnection layer through the silicon hydronitride film, and forming a ferroelectric layer on the lower electrode.

Abstract: A composite semiconductor structure and method of forming the same are provided. The composite semiconductor structure includes a first silicon-containing compound layer comprising an element selected from the group consisting essentially of germanium and carbon; a silicon layer on the first silicon-containing compound layer, wherein the silicon layer comprises substantially pure silicon; and a second silicon-containing compound layer comprising the element on the silicon layer. The first and the second silicon-containing compound layers have substantially lower silicon concentrations than the silicon layer. The composite semiconductor structure may be formed as source/drain regions of metal-oxide-semiconductor (MOS) devices.

Abstract: The present invention is to provide a semiconductor device in which the step can be simplified, the manufacturing cost can be suppressed, and the decrease in yield can be suppressed. A semiconductor device of the present invention includes an antenna, a storage element, and a transistor, wherein a conductive layer serving as an antenna is provided in the same layer as a conductive layer of the transistor or the storage element. This characteristic makes it possible to omit an independent step of forming the conductive layer serving as an antenna and to conduct the step of forming the conductive layer serving as an antenna at the same time as the step of forming a conductive layer of another element. Therefore, the manufacturing step can be simplified, the manufacturing cost can be suppressed, and the decrease in yield can be suppressed.

Abstract: A method of forming a FinFET structure having a metal-insulator-metal capacitor. Silicon fins are formed on a semiconductor substrate followed by formation of the metal-insulator-metal capacitor on the silicon fins by depositing sequential layers of a first layer of titanium nitride, a dielectric layer and a second layer of titanium nitride. A polysilicon layer is deposited over the metal-insulator-metal capacitor followed by etching back the polysilicon layer and the metal-insulator-metal capacitor layers from ends of the silicon fins so that the first and second ends of the silicon fins protrude from the polysilicon layer. A spacer may be formed on surfaces facing the ends of the silicon fins followed by the formation of epitaxial silicon over the ends of the silicon fins. Also disclosed is a FinFET structure having a metal-insulator-metal capacitor.

Abstract: Provided is a method of producing a light-emitting apparatus having a field effect transistor for driving an organic EL device, the field effect transistor including an oxide semiconductor containing at least one element selected from In and Zn, the method including the steps of: forming a field effect transistor on a substrate; forming an insulating layer; forming a lower electrode on the insulating layer; forming an organic layer for constituting an organic EL device on the lower electrode; forming an upper electrode on the organic layer; and after the step of forming the semiconductor layer of the field effect transistor and before the step of forming the organic layer, performing heat treatment such that an amount of a component that is desorbable as H2O from the field effect transistor during the step of forming the organic layer is less than 10?5 g/m2.

Abstract: There are provided a back plane for a flat panel display and a method of manufacturing the back plane, and more particularly, a back plane for an organic light-emitting display device, which enables front light-emitting, and a method of manufacturing the back plane. The back plane for a flat panel display includes: a substrate; a gate electrode on the substrate; a first capacitor on the substrate, the first capacitor comprising a first electrode, an insulation pattern layer on the first electrode, and a second electrode on the insulation pattern layer; a first insulation layer on the substrate to cover the gate electrode and the first capacitor; an active layer on the first insulation layer to correspond to the gate electrode; and a source electrode and a drain electrode on the substrate to contact a portion of the active layer.

Abstract: A semiconductor apparatus includes a first substrate and a second substrate located over a first portion of the first substrate and separated from the first substrate by a buried layer. The semiconductor apparatus also includes an epitaxial layer located over a second portion of the first substrate and isolated from the second substrate. The semiconductor apparatus further includes a first transistor formed at least partially in the second substrate and a second transistor formed at least partially in or over the epitaxial layer. The second substrate and the epitaxial layer have bulk properties with different electron and hole mobilities. At least one of the transistors is configured to receive one or more signals of at least about 5V. The first substrate could have a first crystalline orientation, and the second substrate could have a second crystalline orientation.

Abstract: A semiconductor device in which improvement of a property of holding stored data can be achieved. Further, power consumption of a semiconductor device is reduced. A transistor in which a wide-gap semiconductor material capable of sufficiently reducing the off-state current of a transistor (e.g., an oxide semiconductor material) in a channel formation region is used and which has a trench structure, i.e., a trench for a gate electrode and a trench for element isolation, is provided. The use of a semiconductor material capable of sufficiently reducing the off-state current of a transistor enables data to be held for a long time. Further, since the transistor has the trench for a gate electrode, the occurrence of a short-channel effect can be suppressed by appropriately setting the depth of the trench even when the distance between the source electrode and the drain electrode is decreased.

Abstract: It is possible to manufacture a large-size, high-accuracy organic EL display using a plastic substrate and an organic EL display using a roll-shaped long plastic substrate. The organic EL display includes an organic EL device A having at least a lower electrode 300, an organic layer including at least a light emitting layer, and an upper electrode 305 and a thin film transistor B on a transparent plastic substrate 100, a source electrode or drain electrode of the thin film transistor B is connected to the lower electrode 300, the plastic substrate 100 has a gas barrier layer 101a, the thin film transistor B is formed on the gas barrier layer 101a, the thin film transistor B includes an active layer 203 containing a non-metallic element which a mixture of oxygen (O) and nitrogen (N) and has a ratio of N to O (N number density/O number density) from 0 to 2, and the organic EL device A is formed at least on the gas barrier layer 101a or one the thin film transistor B.

Abstract: An integrated cell may include an nMOS transistor, and an pMOS transistor. The cell may be produced in fully depleted silicon-on-insulator technology, and it is possible for the substrates of the transistors of the cell to be biased with the same adjustable biasing voltage.

Abstract: A thin film transistor includes a gate electrode, a gate insulation layer, a channel layer, a source electrode, and a drain electrode formed on a substrate, in which: the channel layer contains indium, germanium, and oxygen; and the channel layer has a compositional ratio expressed by In/(In+Ge) of 0.5 or more and 0.97 or less.

Abstract: A method for making a semiconductor device is provided which comprises (a) creating a first mask for the epitaxial growth of features in a semiconductor device, said first mask defining a set of epitaxial tiles (219); (b) creating a second mask for defining the active region of the semiconductor device, said second mask defining a set of active tiles (229); and (c) using the first and second masks to create a semiconductor device.

Abstract: A method for forming a via connecting a first upper level layer to a second lower level layer, both layers being surrounded with an insulating material, the method including the steps of: a) forming an opening to reach an edge of the first layer, the opening laterally continuing beyond said edge; b) forming a layer of a protection material on said edge only; c) deepening said opening by selectively etching the insulating material to reach the second lower level layer; and d) filling the opening with at least one conductive contact material.

Abstract: Methods and structures for forming a localized silicon-on-insulator (SOI) finFET are disclosed. Fins are formed on a bulk substrate. Nitride spacers protect the fin sidewalls. A shallow trench isolation region is deposited over the fins. An oxidation process causes oxygen to diffuse through the shallow trench isolation region and into the underlying silicon. The oxygen reacts with the silicon to form oxide, which provides electrical isolation for the fins. The shallow trench isolation region is in direct physical contact with the fins and/or the nitride spacers that are disposed on the fins. Structures comprising bulk-type fins, SOI-type fins, and planar regions are also disclosed.

Abstract: A method of fabricating a monolithic integrated circuit using a single substrate, the method including forming a first semiconductor layer from a substrate, fabricating semiconductor devices on the substrate, fabricating at least one metal wiring layer on the semiconductor devices, forming at least one dielectric layer in integral contact with the at least one metal wiring layer, forming contact openings through the at least one dielectric layer to expose regions of the at least one metal wiring layer, integrally forming, from the substrate, a second semiconductor layer on the dielectric layer, and in contact with the at least one metal wiring layer through the contact openings, and forming a plurality of non-linear semiconductor devices in said second semiconductor layer.