Abstract: A method of forming a transistor device includes forming a dummy gate stack structure over an SOI starting substrate, comprising a bulk layer, a global BOX layer over the bulk layer, and an SOI layer over the global BOX layer. Self-aligned trenches are formed completely through portions of the SOI layer and the global BOX layer at source and drain regions. Silicon is epitaxially regrown in the source and drain regions, with a local BOX layer re-established in the epitaxially regrown silicon, adjacent to the global BOX layer. A top surface of the local BOX layer is below a top surface of the global BOX layer. Embedded source and drain stressors are formed in the source and drain regions, adjacent a channel region. Silicide contacts are formed on the source and drain regions. The dummy gate stack structure is removed, and a final gate stack structure is formed.

Abstract: Multiple types of gate stacks are formed on a doped semiconductor well. A high dielectric constant (high-k) gate dielectric is formed on the doped semiconductor well. A metal gate layer is formed in one device area, while the high-k gate dielectric is exposed in other device areas. Threshold voltage adjustment oxide layers having different thicknesses are formed in the other device areas. A conductive gate material layer is then formed over the threshold voltage adjustment oxide layers. One type of field effect transistors includes a gate dielectric including a high-k gate dielectric portion. Other types of field effect transistors include a gate dielectric including a high-k gate dielectric portion and a first threshold voltage adjustment oxide portions having different thicknesses. Field effect transistors having different threshold voltages are provided by employing different gate dielectric stacks and doped semiconductor wells having the same dopant concentration.

Abstract: A semiconductor device and fabrication method include a strained semiconductor layer having a strain in one axis. A long fin and a short fin are formed in the semiconductor layer such that the long fin has a strained length along the one axis. An n-type transistor is formed on the long fin, and a p-type transistor is formed on the at least one short fin. The strain in the n-type transistor improves performance.

Abstract: A liquid crystal display device includes a plurality of gate lines and data lines on a first substrate defining a plurality of pixel regions, a thin film transistor within the pixel regions, a pixel electrode within the pixel regions, and at least one TiOx layer provided with the thin film transistor.

Abstract: A method for manufacturing a biosensor includes forming a laminate of a first silicon oxide film and a polysilicon film on one surface of a silicon substrate; forming a second silicon oxide film on the other surface of the silicon substrate; forming a source electrode, a drain electrode, and a channel on the first silicon oxide film, the channel connecting the source electrode and the drain electrode; and removing the polysilicon film.

Abstract: Provided is a method of manufacturing a thin film transistor that can improve self-alignment. In this method, a semiconductor layer comprising a first doped region, a second doped region and a channel region is formed on a sacrificial layer on a first substrate. Next, the semiconductor layer is separated from the first substrate and is then coupled on a second substrate. Next, a dielectric layer is formed on the second substrate and the semiconductor layer, and a first photoresist layer is formed on the dielectric layer. Thereafter, the first photoresist layer is exposed to light from a rear surface of the second substrate by using the first doped region and the second doped region as a mask, to form a first mask pattern.

Abstract: There is provided a thin film transistor having improved reliability. A gate electrode includes a first gate electrode having a taper portion and a second gate electrode with a width narrower than the first gate electrode. A semiconductor layer is doped with phosphorus of a low concentration through the first gate electrode. In the semiconductor layer, two kinds of n?-type impurity regions are formed between a channel formation region and n+-type impurity regions. Some of the n?-type impurity regions overlap with a gate electrode, and the other n?-type impurity regions do not overlap with the gate electrode. Since the two kinds of n?-type impurity regions are formed, an off current can be reduced, and deterioration of characteristics can be suppressed.

Abstract: A semiconductor device includes an inverter having an NMOSFET and a PMOSFET having sources, drains and gate electrodes respectively, the drains being connected to each other and the gate electrodes being connected to each other, and a pnp bipolar transistor including a collector (C), a base (B) and an emitter (E), the base (B) receiving an output of the inverter.

Abstract: To suppress generation of dangling bonds, the present invention relates to a method for manufacturing a semiconductor device including the steps of: forming a semiconductor film; forming a gate insulating film and a gate electrode over the semiconductor film; forming an impurity region in the semiconductor film by addition of an impurity element having one conductivity type thereto; forming an insulating film containing fluorine with the semiconductor film, the gate insulating film, and the gate electrode covered therewith; heating the semiconductor film and the insulating film containing fluorine; and forming a wiring, which is electrically connected to the impurity region, over the insulating film containing fluorine. The insulating film containing fluorine is any one of a silicon oxide film containing fluorine, a silicon oxide film containing fluorine and nitrogen, or a silicon nitride film containing fluorine.

Abstract: A novel semiconductor latch is presented. The semiconductor structure is simple and has a reduced number of semiconductor junctions. It offers the advantage of being very small in area, very fast and very efficient. The current conductivity in the structures of the latch circuit is controlled by the gates voltage by means of depleting and enhancing the areas under the gate oxide. The signal isolation is obtained mainly by the carrier depletion of the channel region. By having a reduced number of semiconductor junctions, the intrinsic current leakage can be very small. This latch is the elementary component for volatile memory and logic elements based on this principle.

Abstract: A first aspect of the invention provides a method of forming a semiconductor device, the method comprising: providing a complimentary metal oxide semiconductor (CMOS) device including: a silicon substrate layer; a silicon dioxide layer thereover; and an n-type field effect transistor (NFET) gate having a first recessed source/drain trench and a p-type field effect transistor (PFET) gate having a second recessed source/drain trench, the NFET gate and the PFET gate located over the silicon dioxide layer; depositing a nitride stress liner in the first recessed source/drain trench and the second recessed source/drain trench; depositing an oxide layer over the nitride stress liner; placing the CMOS device on a handling wafer, wherein the oxide layer is closest to the handling wafer; removing the silicon substrate layer; etching the silicon dioxide layer to form an opening abutting a portion of a source/drain region, the source/drain region abutting one of the first recessed source/drain trench or the second recess

Abstract: A method for manufacturing a TFT substrate in which a channel length can be stably formed while the number of masks is reduced. The method includes processing a gate of the n-type TFT, a gate of the p-type TFT, and an upper capacitor electrode by using a half-tone mask instead of some of normal masks to reduce the number of masks, and changing impurity concentrations of semiconductor films located in regions which become a channel of the n-type TFT, a source and a drain of the n-type TFT, a channel of the p-type TFT, a source and a drain of the p-type TFT, and an lower capacitor electrode, by using a pattern of the half-tone mask and a normal mask.

Abstract: The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.

Abstract: A transistor gate forming method includes forming a first and a second transistor gate. Each of the two gates includes a lower metal layer and an upper metal layer. The lower metal layer of the first gate originates from an as-deposited material exhibiting a work function the same as exhibited in an as-deposited material from which the lower metal layer of the second gate originates. However, the first gate's lower metal layer exhibits a modified work function different from a work function exhibited by the second gate's lower metal layer. The first gate's lower metal layer may contain less oxygen and/or carbon in comparison to the second gate's lower metal layer. The first gate's lower metal layer may contain more nitrogen in comparison to the second gate's lower metal layer. The first gate may be a n-channel gate and the second gate may be a p-channel gate.

Abstract: A method of fabricating an electronic structure is provided that includes forming a first conductivity doped first semiconductor material on the SOI semiconductor layer of a substrate. The SOI semiconductor layer has a thickness of less than 10 nm. The first conductivity in-situ doped first semiconductor material is removed from a first portion of the SOI semiconductor layer, wherein a remaining portion of the first conductivity in-situ doped first semiconductor material is present on a second portion of SOI semiconductor layer. A second conductivity in-situ doped second semiconductor material is formed on the first portion of the SOI semiconductor layer, wherein a mask prohibits the second conductivity in-situ doped semiconductor material from being formed on the second portion of the SOI semiconductor layer. The dopants from the first and second conductivity in-situ doped semiconductor materials are diffused into the first semiconductor layer to form dopant regions.

Abstract: A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate; forming a spacer layer over the semiconductor substrate and patterned gate structure; removing horizontally disposed portions of the spacer layer so as to form a vertical sidewall spacer adjacent the patterned gate structure; and forming a raised source/drain (RSD) structure over the semiconductor substrate and adjacent the vertical sidewall spacer, wherein the RSD structure has a substantially vertical sidewall profile so as to abut the vertical sidewall spacer and produce one of a compressive and a tensile strain on a channel region of the semiconductor substrate below the patterned gate structure.

Abstract: A method of forming a semiconductor device is provided, in which the dopant for the source and drain regions is introduced from a doped dielectric layer. In one example, a gate structure is formed on a semiconductor layer of an SOI substrate, in which the thickness of the semiconductor layer is less than 10 nm. A doped dielectric layer is formed over at least the portion of the semiconductor layer that is adjacent to the gate structure. The dopant from the doped dielectric layer is driven into the portion of the semiconductor layer that is adjacent to the gate structure. The dopant diffused into the semiconductor provides source and drain extension regions.

Abstract: In one exemplary embodiment, a method for fabricating a nanowire product comprising: providing a wafer having a buried oxide (BOX) upper layer in which a well is formed, the wafer further having a nanowire having ends resting on the BOX layer such that the nanowire forms a beam spanning said well; and forming a mask coating on an upper surface of the BOX layer leaving an uncoated window over a center part of said beam over said well and also forming a mask coating around beam intermediate ends between each end of a beam center part and a side wall of said well.

Abstract: A FinFET and nanowire transistor with strain direction optimized in accordance with the sideface orientation and carrier polarity and an SMT-introduced manufacturing method for achieving the same are provided. A semiconductor device includes a pMISFET having a semiconductor substrate, a rectangular solid-shaped semiconductor layer formed at upper part of the substrate to have a top surface parallel to a principal plane of the substrate and a sideface with a (100) plane perpendicular to the substrate's principal plane, a channel region formed in the rectangular semiconductor layer, a gate insulating film formed at least on the sideface of the rectangular layer, a gate electrode on the gate insulator film, and source/drain regions formed in the rectangular semiconductor layer to interpose the channel region therebetween. The channel region is applied a compressive strain in the perpendicular direction to the substrate principal plane. A manufacturing method of the device is also disclosed.

Abstract: A high density, asymmetric, butted junction CMOS inverter, formed on an SOI substrate, may include: an asymmetric p-FET that includes a halo implant on only a source side of the p-FET; an asymmetric n-FET that includes a halo implant on only a source side of the n-FET; and a butted junction comprising an area of said SOI substrate where a drain region of the asymmetric n-FET and a drain region of the asymmetric p-FET are in direct physical contact. Asymmetric halo implants may be formed by a sequential process of covering a first FET of the CMOS inverter with an ion-absorbing structure and applying angled ion radiation to only the source side of the second FET, removing the ion-absorbing structure, covering the first FET with a second ion-absorbing structure, and applying angled ion radiation to only the source side of the second FET.

Abstract: A semiconductor device includes a p-type TFT having a first semiconductor layer, and an n-type TFT having a second semiconductor layer. A tilted portion, which is widened toward the insulating substrate side, is formed in at least a part of an outer edge portion of the first semiconductor layer. A tilt angle of a surface of the tilted portion to a surface of an insulating substrate, which is an angle formed inside the first semiconductor layer, is smaller than an angle of a side surface of an outer edge portion of the second semiconductor layer to the surface of the insulating substrate, which is an angle formed inside the second semiconductor layer.

Abstract: A CMOS chip comprising a high performance device region and a high density device region includes a plurality of high performance devices comprising n-type field effect transistors (NFETs) and p-type field effect transistors (PFETs) in the high performance device region, wherein the high performance devices have a high performance pitch; and a plurality of high density devices comprising NFETs and PFETs in the high density device region, wherein the high density devices have a high density pitch, and wherein the high performance pitch is about 2 to 3 times the high density pitch; wherein the high performance device region comprises doped source and drain regions, NFET gate regions having an elevated stress induced using stress memorization technique (SMT), gate and source/drain silicide regions, and a dual stressed liner, and wherein the high density device region comprises doped source and drain regions, gate silicide regions, and a neutral stressed liner.

Abstract: A memory device includes a multi gate field effect transistor (MuGFET) having a fin with a contact area. A programmable memory element abuts the fin contact area.

Abstract: A semiconductor integrated circuit device includes a substrate, a nonvolatile memory device formed in a memory cell region of the substrate, and a semiconductor device formed in a device region of the substrate. The nonvolatile memory device has a multilayer gate electrode structure including a tunnel insulating film and a floating gate electrode formed thereon. The floating gate electrode has sidewall surfaces covered with a protection insulating film. The semiconductor device has a gate insulating film and a gate electrode formed thereon. A bird's beak structure is formed of a thermal oxide film at an interface of the tunnel insulating film and the floating gate electrode, the bird's beak structure penetrating into the floating gate electrode along the interface from the sidewall faces of the floating gate electrode, and the gate insulating film is interposed between the substrate and the gate electrode to have a substantially uniform thickness.

Abstract: An electronic system, method of manufacture of a semiconductor structure, and one or more semiconductor structures are disclosed. For example, a method of manufacture of a semiconductor structure is disclosed, which includes forming a first semiconductor substructure over a semiconductor substrate, forming a first spacer layer over the first semiconductor substructure and the semiconductor substrate, and forming a second semiconductor substructure over at least a portion of the first spacer layer.

Abstract: The disclosure concerns a method of manufacturing a semiconductor device including forming a plurality of fins made of a semiconductor material on an insulating layer; forming a gate insulating film on side surfaces of the plurality of fins; and forming a gate electrode on the gate insulating film in such a manner that a compressive stress is applied to a side surface of a first fin which is used in an NMOSFET among the plurality of fins in a direction perpendicular to the side surface and a tensile stress is applied to a side surface of a second fin which is used in a PMOSFET among the plurality of fins in a direction perpendicular to the side surface.

Abstract: A CMOS device comprising a FinFET comprises at least one fin structure comprising a source region; a drain region; and a channel region comprising silicon separating the source region from the drain region. The FinFET further comprises a gate region comprising a N+ polysilicon layer on one side of the channel region and a P+ polysilicon layer on an opposite side of the channel region, thereby, partitioning the fin structure into a first side and a second side, respectively. The channel region is in mechanical tension on the first side and in mechanical compression on the second side. The FinFET may comprise any of a nFET and a pFET, wherein the nFET comprises a N-channel inversion region in the first side, and wherein the pFET comprises a P-channel inversion region in the second side. The CMOS device may further comprise a tensile film and a relaxed film on opposite sides of the fin structure adjacent to the source and drain regions, and an oxide cap layer over the fin structure.

Abstract: A semiconductor gate stack comprising a silicon oxide based gate dielectric and a doped semiconductor material is formed on a semiconductor substrate. A high-k material metal gate electrode comprising a high-k gate dielectric and a metal gate portion is also formed on the semiconductor substrate. Oxygen-impermeable dielectric spacers are formed on the sidewalls of the semiconductor gate stack and the high-k material metal gate stack. The oxygen-impermeable dielectric spacer on the semiconductor gate stack is removed, while the oxygen impermeable dielectric spacer on the high-k material metal gate electrode is preserved. A low-k dielectric spacer is formed on the semiconductor gate stack, which provides a low parasitic capacitance for the device employing the semiconductor gate stack.

Abstract: A method of forming a display device is provided.

Abstract: Silicon-on-insulator (SOI) structures with silicon layers less than 20 nm thick are used to form extremely thin silicon-on-insulator (ETSOI) semiconductor devices. ETSOI devices are manufactured using a thin tungsten backgate encapsulated by thin nitride layers to prevent metal oxidation, the tungsten backgate being characterized by its low resistivity. The structure further includes at least one FET having a gate stack formed by a high-K metal gate and a tungsten region superimposed thereon, the footprint of the gate stack utilizing the thin SOI layer as a channel. The SOI structure thus formed controls the Vt variation from the thin SOI thickness and dopants therein. The ETSOI high-K metal backgate fully depleted device in conjunction with the thin BOX provides an excellent short channel control and significantly lowers the drain induced bias and sub-threshold swings.

Abstract: The purpose of the present invention is to provide a reliable semiconductor device comprising TFTs having a large area integrated circuit with low wiring resistance. One of the features of the present invention is that an LDD region including a region which overlaps with a gate electrode and a region which does not overlap with the gate electrode is provided in one TFT.

Abstract: There is provided a field effect transistor having an organic semiconductor layer, including: an organic semiconductor layer containing at least porphyrin; and a layer composed of at least a polysiloxane compound, the layer being laminated on the organic semiconductor layer so as to be in intimate contact with the organic semiconductor layer. As a result, there can be provided a field effect transistor which enables an organic semiconductor layer having high crystallinity and high orientation to be formed and which exhibits a high mobility.

Abstract: An electrical device is provided with a p-type semiconductor device having a first gate structure that includes a gate dielectric on top of a semiconductor substrate, a p-type work function metal layer, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An n-type semiconductor device is also present on the semiconductor substrate that includes a second gate structure that includes a gate dielectric, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An interlevel dielectric is present over the semiconductor substrate. The interlevel dielectric includes interconnects to the source and drain regions of the p-type and n-type semiconductor devices. The interconnects are composed of a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. The present disclosure also provides a method of forming the aforementioned structure.

Abstract: A method for manufacturing a dual workfunction semiconductor device and the device made thereof are disclosed. In one aspect, the method includes manufacturing a first transistor in a first region and a second transistor in a second region of a substrate, the first transistor including a first gate stack, the first gate stack having a first gate dielectric capping layer and a first metal gate electrode layer. The second gate stack is similar to the first gate stack. The method includes applying a first thermal budget to the first gate dielectric capping layer and a second thermal budget to the second gate dielectric capping material to tune the workfunction of the first and second gate stack, the first thermal budget being smaller than the second thermal budget such that after the thermal treatment the first and the second gate stack have different work functions.

Abstract: A method includes forming a first fin and a second fin extending above a semiconductor substrate, with a shallow trench isolation (STI) region between them. A space is defined between the first and second fins above a top surface of the STI region. A first height is defined between the top surface of the STI region and top surfaces of the first and second fins. A flowable dielectric material is deposited into the space. The dielectric material has a top surface above the top surface of the STI region, so as to define a second height between the top surface of the dielectric material and the top surfaces of the first and second fins. The second height is less than the first height. First and second fin extensions are epitaxially formed above the dielectric, on the first and second fins, respectively, after the depositing step.

Abstract: An integrated circuit includes a bulk technology integrated circuit (bulk IC) including a bulk silicon layer and complementary MOSFET (CMOS) transistors fabricated thereon. The integrated circuit also includes a single transistor dynamic random access memory (1T DRAM) cell arranged adjacent to and integrated with the bulk IC.

Abstract: A multiple-gate field-effect transistor includes a fluid in a top gate, two lateral gates, and a bottom gate. The multiple-gate field-effect transistor also includes a patterned depletion zone and a virtual depletion zone that has a lesser width than the patterned depletion zone. The virtual depletion zone width creates a virtual semiconductor nanowire that is lesser in width than the patterned depletion zone.

Abstract: An electrical component, in the crystalline semiconductor body of which several CMOS transistors in high-voltage or low-voltage technology are formed. The individual CMOS transistors are separated from one another by insulation regions. On one insulation region, a thin-film transistor is formed, having a gate that is realized simultaneously with the gates of the CMOS transistors from the same polysilicon layer. The gate oxide of the thin-film transistor, just like a second polysilicon layer for source drain and body of the thin-film transistor, can be produced together with the structural elements already present in the CMOS process.

Abstract: The present invention is directed to CMOS structures that include at least one nMOS device located on one region of a semiconductor substrate; and at least one pMOS device located on another region of the semiconductor substrate. In accordance with the present invention, the at least one nMOS device includes a gate stack comprising a gate dielectric, a low workfunction elemental metal having a workfunction of less than 4.2 eV, an in-situ metallic capping layer, and a polysilicon encapsulation layer and the at least one pMOS includes a gate stack comprising a gate dielectric, a high workfunction elemental metal having a workfunction of greater than 4.9 eV, a metallic capping layer, and a polysilicon encapsulation layer. The present invention also provides methods of fabricating such a CMOS structure.

Abstract: A semiconductor structure includes an epitaxial surface semiconductor layer having a first dopant polarity and a first crystallographic orientation, and a laterally adjacent semiconductor-on-insulator surface semiconductor layer having a different second dopant polarity and different second crystallographic orientation. The epitaxial surface semiconductor layer has a first edge that has a defect and an adjoining second edge absent a defect. Located within the epitaxial surface semiconductor layer is a first device having a first gate perpendicular to the first edge and a second device having a second gate perpendicular to the second edge. The first device may include a performance sensitive logic device and the second device may include a yield sensitive memory device.

Abstract: There is disclosed a method of fabricating TFTs having reduced interconnect resistance by having improved contacts to source/drain regions. A silicide layer is formed in intimate contact with the source/drain regions. The remaining metallization layer is selectively etched to form a contact pad or conductive interconnects.

Abstract: Symmetrical/asymmetrical bidirectional S-shaped I-V characteristics with trigger voltages ranging from 10 V to over 40 V and relatively high holding current are obtained for advanced sub-micron silicided CMOS (Complementary Metal Oxide Semiconductor)/BiCMOS (Bipolar CMOS) technologies by custom implementation of P1-N2-P2-N1//N1-P3-N3-P1 lateral structures with embedded ballast resistance 58, 58A, 56, 56A and periphery guard-ring isolation 88-86. The bidirectional protection devices render a high level of electrostatic discharge (ESD) immunity for advanced CMOS/BiCMOS processes with no latchup problems. Novel design-adapted multifinger 354/interdigitated 336 layout schemes of the ESD protection cells allow for scaling-up the ESD performance of the protection structure and custom integration, while the I-V characteristics 480 are adjustable to the operating conditions of the integrated circuit (IC).

Abstract: A semiconductor device includes a Si substrate, an insulating film formed on one part of the Si substrate, a bulk Si region grown on other part of the Si substrate other than the insulating film, Si1-xGex(0<x?1) thin film formed on the insulating film in direct contact with the insulating film, and substantially flush with top of the bulk Si region, a first field effect transistor fabricated in the bulk Si region, and a second field effect transistor fabricated in the Si1-xGex thin film.

Abstract: A semiconductor device and fabrication method include a strained semiconductor layer having a strain in one axis. A long fin and a short fin are formed in the semiconductor layer such that the long fin has a strained length along the one axis. An n-type transistor is formed on the long fin, and a p-type transistor is formed on the at least one short fin. The strain in the n-type transistor improves performance.

Abstract: A single crystal semiconductor substrate including an embrittlement layer is attached to a base substrate with an insulating layer interposed therebetween, and the single crystal semiconductor layer is separated at the embrittlement layer by heat treatment; accordingly, a single crystal semiconductor layer is fixed over the base substrate. The single crystal semiconductor layer is irradiated with a laser beam so that the single crystal semiconductor layer is partially melted and then is re-single crystallized, whereby crystal defects are removed. In addition, an island-shaped single crystal semiconductor layer for forming an n-channel transistor is channel-doped using a photomask and then is etched back using the photomask so that the island-shaped single crystal semiconductor layer for forming an n-channel transistor is thinner than the island-shaped single crystal semiconductor layer for forming a p-channel transistor.

Abstract: A memory cell has N?6 transistors, in which two are access transistors, at least one pair [say (N?2)/2] are pull-up transistors, and at least another pair [say (N?2)/2] are pull-down transistors. The pull-up and pull-down transistors are all coupled between the two access transistors. Each of the access transistors and the pull-up transistors are the same type, p-type or n-type. Each of the pull-down transistors is the other type, p-type or n-type. The access transistors are floating body devices. The pull-down transistors are non-floating body devices. The pull-up transistors may be floating or non-floating body devices. Various specific implementations and methods of making the memory cell are also detailed.

Abstract: A method for improving channel carrier mobility in ultra-thin Silicon-on-oxide (UTSOI) FET devices by integrating an embedded pFET SiGe extension with raised source/drain regions. The method includes selectively growing embedded SiGe (eSiGe) extensions in pFET regions and forming strain-free raised Si or SiGe source/drain (RSD) regions on CMOS. The eSiGe extension regions enhance hole mobility in the pFET channels and reduce resistance in the pFET extensions. The strain-free raised source/drain regions reduce contact resistance in both UTSOI pFETs and nFETs.

Abstract: A method for fabricating a LCD having enhanced aperture ratio and brightness includes: forming a gate line, a gate electrode, a common electrode and a common line in a first mask process; depositing a gate insulating layer covering the gate line, the gate electrode and the common electrode; forming an active layer on the gate insulating layer, and an ohmic contact layer on the active layer in a second mask process; forming a data line, a source electrode, and a drain electrode facing the source electrode in a third mask process; depositing a protective layer over the data line, the source electrode and the drain electrode; forming a pixel contact hole in a fourth mask process; and forming a pixel electrode, wherein the pixel electrode is connected to the drain electrode through the pixel contact hole in a fifth mask process using a reverse tapered photo-resist pattern.

Abstract: An eFUSE is formed with a gate stack including a layer of embedded silicon germanium (eSiGe) on the polysilicon. An embodiment includes forming a shallow trench isolation (STI) region in a substrate, forming a first gate stack on the substrate for a PMOS device, forming a second gate stack on an STI region for an eFUSE, forming first embedded silicon germanium (eSiGe) on the substrate on first and second sides of the first gate stack, and forming second eSiGe on the second gate stack. The addition of eSiGe to the eFUSE gate stack increases the distance between the eFUSE debris zone and an underlying metal gate, thereby preventing potential shorting.

Abstract: Disclosed is an organic light emitting display. In the organic light emitting display, a substrate is divided into a display region, in which an image is displayed, and a non-display region surrounding the display region. The organic light emitting display includes a plurality of pixels provided on the display region. At least one thin film transistor is formed on the non-display region. The display region includes a first electrode connected to the thin film transistor, an organic light emitting layer formed on the first electrode, and a second electrode formed on the organic light emitting layer to apply voltage to the organic light emitting layer with the first electrode. A light blocking layer having an opening formed below the semiconductor layer is formed on the non-display region.