Abstract: A display substrate and a display apparatus are provided. The display substrate includes a base substrate, a crack detection line and an electrostatic discharge element electrically connected to the crack detection line. The base substrate includes a main body area, an auxiliary area, and a necked-down area connecting the main body area and the auxiliary area, and a display area of the display substrate is in the main body area. The crack detection line surrounds, at least in part, the display area and extends through the necked-down area to the auxiliary area. A length direction of the necked-down area is parallel to a first direction; the main body area, the necked-down area and the auxiliary area are connected in a second direction intersecting the first direction; and the electrostatic discharge element is located in the auxiliary area.

Abstract: A display apparatus includes a substrate including a display area and a peripheral area outside the display area, a thin film transistor arranged on the substrate corresponding to the display area and including a semiconductor layer and a gate electrode, a pad electrode arranged on the substrate corresponding to the peripheral area and including a material the same as that of the semiconductor layer, and a first insulating layer arranged on the thin film transistor and the pad electrode and including an opening that partially exposes the pad electrode. Accordingly, failure to perform a normal operation by a pixel circuit and a light-emitting element may be prevented.

Abstract: The display device includes: a display area; a first peripheral area disposed outside the display area; a second peripheral area disposed outside the first peripheral area; an inner dam disposed in the first peripheral area; an outer dam disposed outside the inner dam in the first peripheral area; a resin part formed between the inner dam and the outer dam so as to be higher than the inner dam and the outer dam; and a sealing film disposed so as to overlap with the display area in a plan view. An outer edge of the sealing film overlaps with the resin part or the outer dam in a plan view.

Abstract: A light-emitting panel, a method making same, and a display panel are disclosed in the present disclosure. The light-emitting panel includes a light-emitting board which includes a substrate; a first metal layer disposed on the substrate; a gate insulating layer covering the first metal layer; and a second metal layer on a side of the gate insulating layer away from the first metal layer. The second metal layer includes a connection portion located in the bonding area of the light-emitting board, and a conductive protection layer formed by chemical plating is disposed on a surface of the connection portion.

Abstract: A display device comprises a substrate in which a first subpixel and a second subpixel arranged to adjoin the first subpixel are defined, a first electrode provided in each of the first subpixel and the second subpixel on the substrate, a light emitting layer provided in each of the first subpixel and the second subpixel on the first electrode, a second electrode commonly provided in the first subpixel and the second subpixel on the light emitting layer, a trench portion provided between the first subpixel and the second subpixel, and an insulating portion filling at least a part of the trench portion.

Abstract: A display device includes a substrate, a pixel driver on the substrate, and a display element connected to the pixel driver. The pixel driver includes a conductive layer on the substrate, a buffer layer on the conductive layer, a semiconductor layer on the buffer layer, a gate electrode, the gate electrode overlapping the semiconductor layer, and a source electrode and a drain electrode connected to the semiconductor layer. The buffer layer includes a flattened portion overlapping the conductive layer, and a stepped portion overlapping the periphery of the conductive layer. The semiconductor layer includes a first oxide semiconductor layer on the buffer layer, and a second oxide semiconductor layer on the first oxide semiconductor layer. A width of the first oxide semiconductor layer is larger than a width of the second oxide semiconductor layer, and the first oxide semiconductor layer is on the stepped portion of the buffer layer.

Abstract: A manufacturing method of a display panel and the display panel are provided, wherein the display panel includes a base substrate, a first metal layer, an insulation layer, an active layer, a second metal layer, and a passivation layer. The passivation layer corresponding to a bonding area further includes hole structures. Surface materials of the second metal layer corresponding to the hole structures are a third metal material. Reducing materials are introduced to make a surface of the second metal layer form the third metal material during a preparation.

Abstract: An array substrate, a manufacturing method thereof, and a display device are provided. The array substrate includes: a base substrate; a first signal line on the base substrate; a first buffer layer provided on the base substrate and covering the first signal line; a second signal line on a side of the first buffer layer facing away from the base substrate; a first insulating layer provided on the base substrate and covering the second signal line; and a thin film transistor on a side of the first insulating layer facing away from the base substrate, the thin film transistor including a gate electrode, a source electrode and a drain electrode. A thickness of the first signal line is greater than that of the gate electrode, and a thickness of the second signal line is greater than that of the source electrode or the drain electrode.

Abstract: The present invention refers to a method for exfoliating and transferring graphene from a doped silicon carbide substrate to another substrate, the method being based on exfoliation induced by hydrogen bubbles produced in the electrolysis of water.

Abstract: A patterning method and a method for manufacturing an array substrate are provided, and the patterning method includes: forming a photolithography auxiliary film and a positive photoresist film in turn on a base substrate provided with a layer to be patterned; subjecting the photolithography auxiliary film and the positive photoresist film to a photolithography process to form a photolithography auxiliary layer pattern and a positive photoresist pattern; patterning the layer to be patterned; and UV irradiating the photolithography auxiliary layer pattern and the positive photoresist pattern and then removing the photolithography auxiliary layer pattern and the positive photoresist pattern.

Abstract: Embodiments herein describe techniques for a semiconductor device including a TFT having a gate electrode with a gate length determined by a spacer. Embodiments may include a gate electrode above a substrate, a channel layer above the gate electrode, and a source electrode, a drain electrode, and a spacer above the channel layer. The drain electrode may be separated from the source electrode by the spacer. The drain electrode and the source electrode may have different widths or include different materials. Furthermore, the spacer may overlap with the gate electrode, hence the gate length of the gate electrode may be determined by the spacer width. Other embodiments may be described and/or claimed.

Abstract: Disclosed are an array substrate, a preparation method thereof, a display panel and a display device. The array substrate includes a base substrate, a first thin film transistor, a photosensitive sensor, and a dielectric layer. The first thin film is on the base substrate and includes a gate, a drain, a source and a conductive channel between the drain and the source. The photosensitive sensor has the drain of the first thin film transistor as an electrode of the photosensitive sensor. The dielectric layer covers the conductive channel of the first thin film transistor, where the dielectric layer is a metal oxide film.

Abstract: The present application provides a TFT, a manufacturing method thereof, and a sensor. The TFT includes a substrate, and a source, a drain and an active layer on the substrate. The active layer includes a microchannel, and the thin film transistor is configured to detect a sample in the microchannel. When a sample to be detected enters the microchannel, the electron distribution in the active layer would be affected, which causes fluctuations in the TFT characteristics. By detecting such fluctuations, detecting the composition and property of the liquid to be detected may be achieved. Moreover, by virtue of the microchannel, the sample may be precisely controlled. The impact of the external environment may be reduced and the detection accuracy can be enhanced. Continuous monitoring instead of one-time detection of the sample may be achieved and the sample detection efficiency may be improved.

Abstract: A method of forming imprinted patterns is provided. The method may include detecting a particle located on a wafer. The method may include distributing an imprint medium material on a surface of the wafer. The method may include forming an imprint medium layer on a surface of the wafer with a template and the imprint medium material.

Abstract: The present invention teaches a TFT array substrate, including a substrate; a first metallic layer disposed on the substrate; a gate insulation layer disposed on the first metallic layer and the substrate, where the gate insulation layer includes a level section above the first metallic layer and a pair of step sections respectively connected to lateral sides of the level section; a second metallic layer disposed on the level section, where an area of the second metallic layer's vertical projection onto the top side of the substrate is smaller than an area of the level section's top side; and a protection layer disposed on the second metallic layer and the gate insulation layer. As the second metallic layer is withdrawn for a distance from the level section's circumference, the protection layer is not required to rise continuously, and the protection layer is less prone to broken film and oxidization.

Abstract: An imaging panel includes a photoelectric conversion layer on a side of one of surfaces of a substrate. Further, the imaging panel includes an electrode connected to one of surfaces of the photoelectric conversion layer, a bias line connected with the electrode, and a protection film that is made of a material resistant against an etching agent containing hydrofluoric acid, and covers side surfaces of the bias line.

Abstract: Disclosed are embodiments of a multi-layer stack and photolithography methods and systems that employ such a stack. The disclosed multi-layer stacks include a photoresist layer on an underlayer. The photoresist layer and underlayer are made of different materials, which are selected so that valence and conduction band offsets between the underlayer and photoresist layer create an effective electric field (i.e., so that the stack is “self-biased”). When areas of the photoresist layer are exposed to radiation during photolithography and the radiation passes through photoresist layer and excites electrons in the underlayer, this effective electric field facilitates movement of the radiation-excited electrons from the underlayer into the radiation-exposed areas of the photoresist layer in a direction normal to the interface between the underlayer and the photoresist layer.

Abstract: When a semiconductor device including a transistor in which a gate electrode layer, a gate insulating film, and an oxide semiconductor film are stacked and a source and drain electrode layers are provided in contact with the oxide semiconductor film is manufactured, after the formation of the gate electrode layer or the source and drain electrode layers by an etching step, a step of removing a residue remaining by the etching step and existing on a surface of the gate electrode layer or a surface of the oxide semiconductor film and in the vicinity of the surface is performed. The surface density of the residue on the surface of the oxide semiconductor film or the gate electrode layer can be 1×1013 atoms/cm2 or lower.

Abstract: A semiconductor device includes a gate electrode, an insulating layer, a first carbon nanotube, a second carbon nanotube, a P-type semiconductor layer, an N-type semiconductor layer, a conductive film, a first electrode, a second electrode and a third electrode. The insulating layer is located on a surface of the gate electrode. The first carbon nanotube and the second carbon nanotube are located on a surface of the insulating layer. The P-type semiconductor layer and the N-type semiconductor layer are located on the surface of the insulating layer and apart from each other. The conductive film is located on surfaces of the P-type semiconductor layer and the N-type semiconductor layer. The first electrode is electrically connected with the first carbon nanotube. The second electrode is electrically connected with the second carbon nanotube. The third electrode is electrically connected with the conductive film.

Abstract: The present application relates to a grating assembly, a display device, a control method thereof and a storage medium, in the field of display technology. The grating assembly comprises: a first substrate and a second substrate disposed opposite to each other, and a liquid crystal layer disposed between the first substrate and the second substrate. The first substrate is provided with a power supply electrode on a side adjacent to the liquid crystal layer, and the second substrate is provided with k strip electrodes on a side adjacent to the liquid crystal layer. The k strip electrodes are connected to form a coil.

Abstract: The present disclosure relates to a mask plate and a manufacturing method of array substrates. The mask plate includes: at least two first sub-areas and at least one second sub-area. Wherein the first sub-areas are spaced apart from each other, and the first sub-areas are configured to be as semi-transparent areas, and a transmittance rate of the the second sub-area is greater than the first sub-area. When conducting an exposure process on a photoresist, a thickness of the exposed photoresist via the second sub-area is greater than a thickness of the exposed photoresist via the first sub-area. When manufacturing an array substrate, a channel of the array substrate corresponds to the second sub-area. The time for conducting the exposure process and an ashing process may be reduced by adopting the mask plate when manufacturing the array substrates.

Abstract: There are provided a display panel and a display device including the same. In the display panel and display device including the same, in a structure in which an insulating layer having a depression point is provided between different conductive layers, another insulating layer may be disposed to cover the depression point. Accordingly, an occurrence of a short circuit may be minimized between the different conductive layers.

Abstract: Systems and methods for synthesizing nanocrystals using continuous, microwave-assisted, segmented flow reactor.

Abstract: A semiconductor device includes a base; a gate electrode to which a gate voltage is applied; a source electrode and a drain electrode through which an electric current is generated according to the gate voltage being applied to the gate electrode; a semiconductor layer made of an oxide semiconductor; and a gate insulating layer inserted between the gate electrode and the semiconductor layer. The semiconductor layer includes a channel-forming region and a non-channel-forming region; the channel-forming region is in contact with the source electrode and the drain electrode, and the non-channel-forming region is in contact with the source electrode and the drain electrode.

Abstract: There is provided a display device including: a light emitting element; and a drive transistor (DRTr) that includes a coupling section (W1) and a plurality of channel sections (CH) coupled in series through the coupling section (W1), wherein the drive transistor (DRTr) is configured to supply a drive current to the light emitting element.

Abstract: A vacuum processing apparatus includes a processing chamber inside a vacuum vessel, a plasma forming chamber above, a dielectric plate member having multiple through-holes for introducing particles of plasma to the processing chamber between the processing chamber and the plasma forming chamber above a sample stage upper surface in the processing chamber, heating lamp arranged around an outer periphery of the plate member to irradiate an electromagnetic wave to the wafer to heat, and a ring-shaped window member for transmitting the electromagnetic wave from the lamp. The apparatus performs, from the through-holes to the wafer, supplying particles of plasma formed in the plasma forming chamber to form a reaction product, extinguishing the plasma and heating the wafer to desorb the product, and supplying particles, formed in the plasma forming chamber, of the plasma of cleaning gas to the plasma forming chamber, the processing chamber, and the window member.

Abstract: There is provided a display device including: a light emitting element; and a drive transistor (DRTr) that includes a coupling section (W1) and a plurality of channel sections (CH) coupled in series through the coupling section (W1), wherein the drive transistor (DRTr) is configured to supply a drive current to the light emitting element.

Abstract: A transparent display device includes a base substrate having a pixel area and a transmission area, a barrier layer disposed on the base substrate, a pixel circuit disposed in the pixel area, a display structure disposed on the pixel circuit, a transmitting structure disposed in the transmission area, an adhesive layer disposed between the base substrate and the barrier layer, and between the base substrate and the transmitting structure, and a transmitting window defined in the transmission area where the transmitting structure may include a composition including silicon oxynitride, the adhesive layer may include aluminum oxide, and the transmitting window may expose a surface of the transmitting structure.

Abstract: A method for manufacturing a display device is provided. The method includes forming a display element interposed between a first substrate and a second substrate and peeling the second substrate from the first substrate so that an electrode, which is located between the first and second substrates and to be connected to an external electrode, is exposed simultaneously with the peeling of the second substrate.

Abstract: A display apparatus includes a first substrate including a channel-forming area, a second substrate facing the first substrate, a thin-film transistor disposed on the first substrate, a pixel electrode electrically connected to the thin-film transistor, a gate line disposed on the first substrate and electrically connected to the thin-film transistor, a data line electrically connected to the thin-film transistor and divided into at least two portions such that the channel-forming area is disposed between the two portions of the data line, and a connection portion electrically connecting the two portions of the data line to each other, in which the thin-film transistor includes a gate electrode branched from the gate line and overlapping the channel-forming area, a semiconductor pattern overlapping the gate electrode and contacting the two portions of the data line so that the channel-forming area is disposed in the semiconductor pattern, and a drain electrode electrically connected to the pixel electrode and

Abstract: An array substrate, a display device, and a method for manufacturing the array substrate are disclosed. The array substrate comprises a base substrate, a light-absorbing layer, and a bottom-gate thin film transistor unit arranged in sequence, wherein a projection of the light-absorbing layer covers a gate metal layer, a source metal layer, and a drain metal layer of the bottom-gate thin film transistor unit. According to the present disclosure, the ambient light can be prevented from irradiating the metal layers of the bottom-gate thin film transistor unit effectively in the case that the brightness of the display panel is not reduced.

Abstract: A method for manufacturing a display device is provided. The method includes forming a display element interposed between a first substrate and a second substrate and peeling the second substrate from the first substrate so that an electrode, which is located between the first and second substrates and to be connected to an external electrode, is exposed simultaneously with the peeling of the second substrate.

Abstract: An organic light-emitting diode (OLED) display and a method of manufacturing thereof are disclosed. In one aspect, the display includes a scan line formed over a substrate and configured to provide a scan signal. An initialization voltage line has substantially the same pattern as the scan line and is insulated from the scan line. A data line crosses the scan line and is configured to provide a data voltage. A switching transistor is electrically connected to the scan line and the data line, and a driving transistor is electrically connected to the switching transistor and includes a driving gate electrode. A storage capacitor includes a first storage electrode and a second storage electrode overlapping the first storage electrode, wherein the first storage electrode and the driving gate electrode are integrally formed.

Abstract: In a thin film transistor, an increase in off current or negative shift of the threshold voltage is prevented. In the thin film transistor, a buffer layer is provided between an oxide semiconductor layer and each of a source electrode layer and a drain electrode layer. The buffer layer includes a metal oxide layer which is an insulator or a semiconductor over a middle portion of the oxide semiconductor layer. The metal oxide layer functions as a protective layer for suppressing incorporation of impurities into the oxide semiconductor layer. Therefore, in the thin film transistor, an increase in off current or negative shift of the threshold voltage can be prevented.

Abstract: An object is to improve reliability of a semiconductor device. A semiconductor device including a driver circuit portion and a display portion (also referred to as a pixel portion) over the same substrate is provided. The driver circuit portion and the display portion include thin film transistors in which a semiconductor layer includes an oxide semiconductor; a first wiring; and a second wiring. The thin film transistors each include a source electrode layer and a drain electrode layer. In the thin film transistor in the driver circuit portion, the semiconductor layer is sandwiched between a gate electrode layer and a conductive layer. The first wiring and the second wiring are electrically connected to each other in an opening provided in a gate insulating film through an oxide conductive layer.

Abstract: The touch panel includes a plurality of touch pads arranged in an array on the touch panel. Each of the touch pads are arranged in N columns and M rows, the touch pad in the ith column and in the jth row is coupled to the touch pad in the (i?1)th column and in the (j?1)th row and the touch pad in the (i+1)th column and in the (j+1)th row, or the touch pad in the ith column and in the jth row is coupled to the touch pad in the (i+1)th column and in the (j?1)th row and the touch pad in the (i?1)th column and in the (j+1)th row.

Abstract: A method for fabricating a touch panel includes forming a routing and pad pattern group on a substrate to include first and second routing lines, first pad electrodes connected to the first routing line, and second pad electrodes connected to the second routing line, by using a first mask, forming a sensor electrode pattern group on the substrate having the routing and pad pattern group formed thereon to include first sensor electrodes formed in a first direction, second sensor electrodes formed in a second direction, and connection portions that each connects adjacent first sensor electrodes, by using a second mask, forming a first insulating layer to include contact holes to expose portions of the second sensor electrodes, respectively, by using a third mask and forming bridges that each connects adjacent second sensor electrodes through the contact holes and a second insulating layer on the bridges, by using a fourth mask.

Abstract: A manufacturing method of an array substrate, an array substrate and a display device are provided. The array substrate includes a first thin film transistor and a pixel electrode (327), wherein, an active layer (324) and source and drain electrodes in the first thin film transistor as well as the pixel electrode (327) are formed by one patterning process. According to the invention, an array substrate with good performance can be manufactured only by three photolithography processes. Thus, the production cycle of a thin film transistor is shorted greatly, characteristics of the thin film transistor is improved, and meanwhile, yield of products is enhanced greatly.

Abstract: To provide an imaging device capable of high-speed reading. The imaging device includes a photodiode, a first transistor, a second transistor, a third transistor, and a fourth transistor. The back gate electrode of the first transistor is electrically connected to a wiring that can supply a potential higher than a source potential of the first transistor and a potential lower than the source potential of the first transistor. The back gate electrode of the second transistor is electrically connected to a wiring that can supply a potential higher than a source potential of the second transistor. The back gate electrode of the third transistor is electrically connected to a wiring that can supply a potential higher than a source potential of the third transistor and a potential lower than the source potential of the third transistor.

Abstract: A transistor having an oxide semiconductor film in a channel formation region and a manufacturing method thereof are disclosed. The transistor is formed by the steps of: forming a base insulating over a substrate; forming an oxide semiconductor film over the base insulating film; forming a conductive film over the oxide semiconductor film; processing the conductive film to form a source electrode and a drain electrode; processing the oxide semiconductor film; forming a gate insulating film over the source electrode, the drain electrode, and the oxide semiconductor film; and forming a gate electrode over the gate insulating film. The aforementioned manufacturing method allows the formation of a transistor in which a side surface of the oxide semiconductor film is not in direct contact with bottom surfaces of the source electrode and the drain electrode, which contributes to the extremely small leak current of the transistor.

Abstract: Disclosed is an LCD device having a dual link structure and a method of manufacturing the same, which can reduce a width of a bezel. A link line structure includes a plurality of first and second link lines which are alternately disposed. The first and second link lines are formed on different layers. Also, embodiments herein provide a method which can reduce the number of masks used in a manufacturing process and can easily manufacture the LCD device in consideration of the possibility of misalignment of exposure equipment.

Abstract: When a semiconductor device including a transistor in which a gate electrode layer, a gate insulating film, and an oxide semiconductor film are stacked and a source and drain electrode layers are provided in contact with the oxide semiconductor film is manufactured, after the formation of the gate electrode layer or the source and drain electrode layers by an etching step, a step of removing a residue remaining by the etching step and existing on a surface of the gate electrode layer or a surface of the oxide semiconductor film and in the vicinity of the surface is performed. The surface density of the residue on the surface of the oxide semiconductor film or the gate electrode layer can be 1×1013 atoms/cm2 or lower.

Abstract: Cohesive carbon assemblies are prepared by obtaining a carbon starting material in the form of powder, particles, flakes, or loose agglomerates, dispersing the carbon in a selected organic solvent by mechanical mixing and/or sonication, and substantially removing the organic solvent, typically by evaporation, whereby the cohesive assembly of carbon is formed. The method is suitable for preparing free-standing, monolithic assemblies of carbon nanotubes in the form of films, wafers, or discs, having high carbon packing density and low electrical resistivity. The method is suitable for preparing adherent cohesive carbon assemblies on substrates comprising various materials. The assemblies have various potential applications, such as electrodes or current collectors in electrochemical capacitors, fuel cells, and batteries, or as electromagnetic interference shielding materials.

Abstract: A novel 2D/3D hierarchical-BL NAND array with at least one plane on independent Psubstrate comprising a plurality of LG groups respectively associated with a plurality of local bit lines (LBLs) laid at a level below a plurality of broken or non-broken global bit lines (GBLs) connected to Page Buffer. Each LG group includes multiple blocks and connects an independent power supply line to each of the plurality of LBLs. Each block including N-bit 2D/3D NAND strings each with S cells connected in series and terminated by two string-select devices and coupled to a common source line. In particular, random-size partial-block WLs are selected from each block of randomly selected LG groups of one plane of the 2D/3D NAND array for erase at the same time with border WLs being optionally preread and program into another plane of the 2D/3D NAND array or optionally saved off-chip and wrote back for data security.

Abstract: An object is to improve reliability of a semiconductor device. A semiconductor device including a driver circuit portion and a display portion (also referred to as a pixel portion) over the same substrate is provided. The driver circuit portion and the display portion include thin film transistors in which a semiconductor layer includes an oxide semiconductor; a first wiring; and a second wiring. The thin film transistors each include a source electrode layer and a drain electrode layer. In the thin film transistor in the driver circuit portion, the semiconductor layer is sandwiched between a gate electrode layer and a conductive layer. The first wiring and the second wiring are electrically connected to each other in an opening provided in a gate insulating film through an oxide conductive layer.

Abstract: A thin film transistor array panel includes an insulation substrate; a gate line and a first electrode on the insulation substrate; a gate insulating layer on the gate line and the first electrode; a data line on the gate insulating layer; a passivation layer on the gate insulating layer and the data line; and a second electrode on the passivation layer. Relative permittivity (?) of the gate insulating layer is more than about 15, and a thickness of the gate insulating layer is about 2000 angstroms.

Abstract: An array substrate includes a plurality of data lines, a plurality of gamma lines, a repair pad, a repair line, an inspection pad and an inspection line. The data lines transmit a data voltage to an active region. The gamma lines apply a gamma reference voltage to generate the data voltage. The repair pad repairs the data line. The repair line extends from the repair pad. The repair line is disposed adjacent to the gamma line. The inspection pad applies an inspection signal. The inspection line extends from the inspection pad. The inspection line is connected to the data lines. The gamma lines are connected to the inspection line.

Abstract: An edge termination structure for a silicon carbide semiconductor device includes a plurality of spaced apart concentric floating guard rings in a silicon carbide layer that at least partially surround a silicon carbide-based junction, an insulating layer on the floating guard rings, and a silicon carbide surface charge compensation region between the floating guard rings and adjacent the surface of the silicon carbide layer. A silicon nitride layer is on the silicon carbide layer, and an organic protective layer is on the silicon nitride layer. An oxide layer may be between the silicon nitride layer and the surface of the silicon carbide layer. Methods of forming edge termination structures are also disclosed.

Abstract: A circuit including an inverter is provided for a wiring layer. A semiconductor device is provided with a wiring layer circuit which is formed over an insulating film and includes at least one inverter element. The inverter is provided with a first transistor element and a resistance element which is connected to the first transistor via a connection node. The first transistor element is provided with a gate electrode which is embedded in an interlayer insulating film including the insulating film, a gate insulating film which is formed over the interlayer insulating film and the gate electrode, and a first semiconductor layer which is formed over the gate insulating film between a source electrode and a drain electrode. The resistance element is provided with a second semiconductor layer which functions as a resistance. The first semiconductor layer and the second semiconductor layer are formed in the same layer.

Abstract: A touch screen panel includes a touch substrate, first sensing electrodes, second sensing electrodes, and outer lines. The touch substrate includes a touch active area and a touch non-active area. The first and second sensing electrodes are disposed in the touch active area and insulated from each other while crossing each other. Each first sensing electrode includes a first sensing metal layer and a first transparent sensing electrode layer. Each second sensing electrode includes a second sensing metal layer and a second transparent sensing electrode layer. Each outer line includes a first outer metal layer, a transparent outer electrode layer, and a second outer metal layer.