Inverted Transistor Structure Patents (Class 438/158)
  • Patent number: 11011570
    Abstract: An imaging panel includes a photoelectric conversion layer on a side of one of surfaces of a substrate. Further, the imaging panel includes an electrode connected to one of surfaces of the photoelectric conversion layer, a bias line connected with the electrode, and a protection film that is made of a material resistant against an etching agent containing hydrofluoric acid, and covers side surfaces of the bias line.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: May 18, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Katsunori Misaki
  • Patent number: 10782606
    Abstract: Disclosed are embodiments of a multi-layer stack and photolithography methods and systems that employ such a stack. The disclosed multi-layer stacks include a photoresist layer on an underlayer. The photoresist layer and underlayer are made of different materials, which are selected so that valence and conduction band offsets between the underlayer and photoresist layer create an effective electric field (i.e., so that the stack is “self-biased”). When areas of the photoresist layer are exposed to radiation during photolithography and the radiation passes through photoresist layer and excites electrons in the underlayer, this effective electric field facilitates movement of the radiation-excited electrons from the underlayer into the radiation-exposed areas of the photoresist layer in a direction normal to the interface between the underlayer and the photoresist layer.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: September 22, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yong Liang, Lei Sun, Yongan Xu, Craig D. Higgins
  • Patent number: 10535776
    Abstract: When a semiconductor device including a transistor in which a gate electrode layer, a gate insulating film, and an oxide semiconductor film are stacked and a source and drain electrode layers are provided in contact with the oxide semiconductor film is manufactured, after the formation of the gate electrode layer or the source and drain electrode layers by an etching step, a step of removing a residue remaining by the etching step and existing on a surface of the gate electrode layer or a surface of the oxide semiconductor film and in the vicinity of the surface is performed. The surface density of the residue on the surface of the oxide semiconductor film or the gate electrode layer can be 1×1013 atoms/cm2 or lower.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: January 14, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiko Hayakawa, Tatsuya Honda
  • Patent number: 10424638
    Abstract: A semiconductor device includes a gate electrode, an insulating layer, a first carbon nanotube, a second carbon nanotube, a P-type semiconductor layer, an N-type semiconductor layer, a conductive film, a first electrode, a second electrode and a third electrode. The insulating layer is located on a surface of the gate electrode. The first carbon nanotube and the second carbon nanotube are located on a surface of the insulating layer. The P-type semiconductor layer and the N-type semiconductor layer are located on the surface of the insulating layer and apart from each other. The conductive film is located on surfaces of the P-type semiconductor layer and the N-type semiconductor layer. The first electrode is electrically connected with the first carbon nanotube. The second electrode is electrically connected with the second carbon nanotube. The third electrode is electrically connected with the conductive film.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: September 24, 2019
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Jin Zhang, Yang Wei, Kai-Li Jiang, Shou-Shan Fan
  • Patent number: 10389013
    Abstract: The present application relates to a grating assembly, a display device, a control method thereof and a storage medium, in the field of display technology. The grating assembly comprises: a first substrate and a second substrate disposed opposite to each other, and a liquid crystal layer disposed between the first substrate and the second substrate. The first substrate is provided with a power supply electrode on a side adjacent to the liquid crystal layer, and the second substrate is provided with k strip electrodes on a side adjacent to the liquid crystal layer. The k strip electrodes are connected to form a coil.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: August 20, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD
    Inventor: Dongmei Wei
  • Patent number: 10345697
    Abstract: The present disclosure relates to a mask plate and a manufacturing method of array substrates. The mask plate includes: at least two first sub-areas and at least one second sub-area. Wherein the first sub-areas are spaced apart from each other, and the first sub-areas are configured to be as semi-transparent areas, and a transmittance rate of the the second sub-area is greater than the first sub-area. When conducting an exposure process on a photoresist, a thickness of the exposed photoresist via the second sub-area is greater than a thickness of the exposed photoresist via the first sub-area. When manufacturing an array substrate, a channel of the array substrate corresponds to the second sub-area. The time for conducting the exposure process and an ashing process may be reduced by adopting the mask plate when manufacturing the array substrates.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: July 9, 2019
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Dongzi Gao
  • Patent number: 10276604
    Abstract: There are provided a display panel and a display device including the same. In the display panel and display device including the same, in a structure in which an insulating layer having a depression point is provided between different conductive layers, another insulating layer may be disposed to cover the depression point. Accordingly, an occurrence of a short circuit may be minimized between the different conductive layers.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: April 30, 2019
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Jaeyeong Choi, ChongHun Park
  • Patent number: 10189003
    Abstract: Systems and methods for synthesizing nanocrystals using continuous, microwave-assisted, segmented flow reactor.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: January 29, 2019
    Assignee: OREGON STATE UNIVERSITY
    Inventors: Ki-Joong Kim, Eric Bradley Hostetler, Gregory Scott Herman, Daniel Alan Peterson, Chih-hung Chang, Brendan Thomas Flynn, Brian Kevin Paul, Richard Paul Oleksak, Padmavathi Chandran, Bob C. Fitzmorris, Gustavo Henrique Albuquerque
  • Patent number: 10170635
    Abstract: A semiconductor device includes a base; a gate electrode to which a gate voltage is applied; a source electrode and a drain electrode through which an electric current is generated according to the gate voltage being applied to the gate electrode; a semiconductor layer made of an oxide semiconductor; and a gate insulating layer inserted between the gate electrode and the semiconductor layer. The semiconductor layer includes a channel-forming region and a non-channel-forming region; the channel-forming region is in contact with the source electrode and the drain electrode, and the non-channel-forming region is in contact with the source electrode and the drain electrode.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: January 1, 2019
    Assignee: RICOH COMPANY, LTD.
    Inventors: Shinji Matsumoto, Naoyuki Ueda, Yuki Nakamura, Yukiko Abe, Yuji Sone, Ryoichi Saotome, Sadanori Arae, Minehide Kusayanagi
  • Patent number: 10147779
    Abstract: There is provided a display device including: a light emitting element; and a drive transistor (DRTr) that includes a coupling section (W1) and a plurality of channel sections (CH) coupled in series through the coupling section (W1), wherein the drive transistor (DRTr) is configured to supply a drive current to the light emitting element.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: December 4, 2018
    Assignee: Sony Corporation
    Inventor: Seiichiro Jinta
  • Patent number: 10141207
    Abstract: A vacuum processing apparatus includes a processing chamber inside a vacuum vessel, a plasma forming chamber above, a dielectric plate member having multiple through-holes for introducing particles of plasma to the processing chamber between the processing chamber and the plasma forming chamber above a sample stage upper surface in the processing chamber, heating lamp arranged around an outer periphery of the plate member to irradiate an electromagnetic wave to the wafer to heat, and a ring-shaped window member for transmitting the electromagnetic wave from the lamp. The apparatus performs, from the through-holes to the wafer, supplying particles of plasma formed in the plasma forming chamber to form a reaction product, extinguishing the plasma and heating the wafer to desorb the product, and supplying particles, formed in the plasma forming chamber, of the plasma of cleaning gas to the plasma forming chamber, the processing chamber, and the window member.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: November 27, 2018
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Yutaka Kouzuma, Hiroyuki Kobayashi, Nobuya Miyoshi, Kenetsu Yokogawa, Tomoyuki Watanabe
  • Patent number: 10121841
    Abstract: There is provided a display device including: a light emitting element; and a drive transistor (DRTr) that includes a coupling section (W1) and a plurality of channel sections (CH) coupled in series through the coupling section (W1), wherein the drive transistor (DRTr) is configured to supply a drive current to the light emitting element.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: November 6, 2018
    Assignee: Sony Corporation
    Inventor: Seiichiro Jinta
  • Patent number: 10068923
    Abstract: A transparent display device includes a base substrate having a pixel area and a transmission area, a barrier layer disposed on the base substrate, a pixel circuit disposed in the pixel area, a display structure disposed on the pixel circuit, a transmitting structure disposed in the transmission area, an adhesive layer disposed between the base substrate and the barrier layer, and between the base substrate and the transmitting structure, and a transmitting window defined in the transmission area where the transmitting structure may include a composition including silicon oxynitride, the adhesive layer may include aluminum oxide, and the transmitting window may expose a surface of the transmitting structure.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: September 4, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Seung-Ho Jung, Chaun-Gi Choi, Hyeon-Sik Kim, Hye-Young Park, Hye-Hyang Park, Hui-Won Yang, Eun-Young Lee, Joo-Hee Jeon, Su-Kyoung Yang, Chan-Woo Yang
  • Patent number: 10038171
    Abstract: A method for manufacturing a display device is provided. The method includes forming a display element interposed between a first substrate and a second substrate and peeling the second substrate from the first substrate so that an electrode, which is located between the first and second substrates and to be connected to an external electrode, is exposed simultaneously with the peeling of the second substrate.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: July 31, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuya Sakuishi, Daiki Nakamura, Akihiro Chida, Tomoya Aoyama
  • Patent number: 9954044
    Abstract: A display apparatus includes a first substrate including a channel-forming area, a second substrate facing the first substrate, a thin-film transistor disposed on the first substrate, a pixel electrode electrically connected to the thin-film transistor, a gate line disposed on the first substrate and electrically connected to the thin-film transistor, a data line electrically connected to the thin-film transistor and divided into at least two portions such that the channel-forming area is disposed between the two portions of the data line, and a connection portion electrically connecting the two portions of the data line to each other, in which the thin-film transistor includes a gate electrode branched from the gate line and overlapping the channel-forming area, a semiconductor pattern overlapping the gate electrode and contacting the two portions of the data line so that the channel-forming area is disposed in the semiconductor pattern, and a drain electrode electrically connected to the pixel electrode and
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: April 24, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Dong Gun Oh, Seunghyun Park, JiEun Lee, Cheol-Gon Lee, Woongki Jeon
  • Patent number: 9887392
    Abstract: A method for manufacturing a display device is provided. The method includes forming a display element interposed between a first substrate and a second substrate and peeling the second substrate from the first substrate so that an electrode, which is located between the first and second substrates and to be connected to an external electrode, is exposed simultaneously with the peeling of the second substrate.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: February 6, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuya Sakuishi, Daiki Nakamura, Akihiro Chida, Tomoya Aoyama
  • Patent number: 9887255
    Abstract: An array substrate, a display device, and a method for manufacturing the array substrate are disclosed. The array substrate comprises a base substrate, a light-absorbing layer, and a bottom-gate thin film transistor unit arranged in sequence, wherein a projection of the light-absorbing layer covers a gate metal layer, a source metal layer, and a drain metal layer of the bottom-gate thin film transistor unit. According to the present disclosure, the ambient light can be prevented from irradiating the metal layers of the bottom-gate thin film transistor unit effectively in the case that the brightness of the display panel is not reduced.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: February 6, 2018
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventor: Xiangyang Xu
  • Patent number: 9865667
    Abstract: An organic light-emitting diode (OLED) display and a method of manufacturing thereof are disclosed. In one aspect, the display includes a scan line formed over a substrate and configured to provide a scan signal. An initialization voltage line has substantially the same pattern as the scan line and is insulated from the scan line. A data line crosses the scan line and is configured to provide a data voltage. A switching transistor is electrically connected to the scan line and the data line, and a driving transistor is electrically connected to the switching transistor and includes a driving gate electrode. A storage capacitor includes a first storage electrode and a second storage electrode overlapping the first storage electrode, wherein the first storage electrode and the driving gate electrode are integrally formed.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: January 9, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Elly Gil, Seung Gyu Tae
  • Patent number: 9859306
    Abstract: In a thin film transistor, an increase in off current or negative shift of the threshold voltage is prevented. In the thin film transistor, a buffer layer is provided between an oxide semiconductor layer and each of a source electrode layer and a drain electrode layer. The buffer layer includes a metal oxide layer which is an insulator or a semiconductor over a middle portion of the oxide semiconductor layer. The metal oxide layer functions as a protective layer for suppressing incorporation of impurities into the oxide semiconductor layer. Therefore, in the thin film transistor, an increase in off current or negative shift of the threshold voltage can be prevented.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: January 2, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshikazu Kondo, Hideyuki Kishida
  • Patent number: 9837442
    Abstract: An object is to improve reliability of a semiconductor device. A semiconductor device including a driver circuit portion and a display portion (also referred to as a pixel portion) over the same substrate is provided. The driver circuit portion and the display portion include thin film transistors in which a semiconductor layer includes an oxide semiconductor; a first wiring; and a second wiring. The thin film transistors each include a source electrode layer and a drain electrode layer. In the thin film transistor in the driver circuit portion, the semiconductor layer is sandwiched between a gate electrode layer and a conductive layer. The first wiring and the second wiring are electrically connected to each other in an opening provided in a gate insulating film through an oxide conductive layer.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: December 5, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichiro Sakata, Masayuki Sakakura, Yoshiaki Oikawa, Kenichi Okazaki, Hotaka Maruyama, Masashi Tsubuku
  • Patent number: 9817525
    Abstract: The touch panel includes a plurality of touch pads arranged in an array on the touch panel. Each of the touch pads are arranged in N columns and M rows, the touch pad in the ith column and in the jth row is coupled to the touch pad in the (i?1)th column and in the (j?1)th row and the touch pad in the (i+1)th column and in the (j+1)th row, or the touch pad in the ith column and in the jth row is coupled to the touch pad in the (i+1)th column and in the (j?1)th row and the touch pad in the (i?1)th column and in the (j+1)th row.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: November 14, 2017
    Assignee: Novatek Microelectronics Corp.
    Inventors: Shih-Jung Lu, Wing-Kai Tang
  • Patent number: 9727195
    Abstract: A method for fabricating a touch panel includes forming a routing and pad pattern group on a substrate to include first and second routing lines, first pad electrodes connected to the first routing line, and second pad electrodes connected to the second routing line, by using a first mask, forming a sensor electrode pattern group on the substrate having the routing and pad pattern group formed thereon to include first sensor electrodes formed in a first direction, second sensor electrodes formed in a second direction, and connection portions that each connects adjacent first sensor electrodes, by using a second mask, forming a first insulating layer to include contact holes to expose portions of the second sensor electrodes, respectively, by using a third mask and forming bridges that each connects adjacent second sensor electrodes through the contact holes and a second insulating layer on the bridges, by using a fourth mask.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: August 8, 2017
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Seung-Hyun Kim, Hyung-Chul Kim, Tae-Yeon Yoo
  • Patent number: 9685461
    Abstract: A manufacturing method of an array substrate, an array substrate and a display device are provided. The array substrate includes a first thin film transistor and a pixel electrode (327), wherein, an active layer (324) and source and drain electrodes in the first thin film transistor as well as the pixel electrode (327) are formed by one patterning process. According to the invention, an array substrate with good performance can be manufactured only by three photolithography processes. Thus, the production cycle of a thin film transistor is shorted greatly, characteristics of the thin film transistor is improved, and meanwhile, yield of products is enhanced greatly.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: June 20, 2017
    Assignee: BOE Technology Group Co., Ltd.
    Inventor: Guangcai Yuan
  • Patent number: 9685476
    Abstract: To provide an imaging device capable of high-speed reading. The imaging device includes a photodiode, a first transistor, a second transistor, a third transistor, and a fourth transistor. The back gate electrode of the first transistor is electrically connected to a wiring that can supply a potential higher than a source potential of the first transistor and a potential lower than the source potential of the first transistor. The back gate electrode of the second transistor is electrically connected to a wiring that can supply a potential higher than a source potential of the second transistor. The back gate electrode of the third transistor is electrically connected to a wiring that can supply a potential higher than a source potential of the third transistor and a potential lower than the source potential of the third transistor.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: June 20, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Seiichi Yoneda, Takuro Ohmaru, Yuki Okamoto
  • Patent number: 9673336
    Abstract: A transistor having an oxide semiconductor film in a channel formation region and a manufacturing method thereof are disclosed. The transistor is formed by the steps of: forming a base insulating over a substrate; forming an oxide semiconductor film over the base insulating film; forming a conductive film over the oxide semiconductor film; processing the conductive film to form a source electrode and a drain electrode; processing the oxide semiconductor film; forming a gate insulating film over the source electrode, the drain electrode, and the oxide semiconductor film; and forming a gate electrode over the gate insulating film. The aforementioned manufacturing method allows the formation of a transistor in which a side surface of the oxide semiconductor film is not in direct contact with bottom surfaces of the source electrode and the drain electrode, which contributes to the extremely small leak current of the transistor.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: June 6, 2017
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Shunpei Yamazaki
  • Patent number: 9658502
    Abstract: Disclosed is an LCD device having a dual link structure and a method of manufacturing the same, which can reduce a width of a bezel. A link line structure includes a plurality of first and second link lines which are alternately disposed. The first and second link lines are formed on different layers. Also, embodiments herein provide a method which can reduce the number of masks used in a manufacturing process and can easily manufacture the LCD device in consideration of the possibility of misalignment of exposure equipment.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: May 23, 2017
    Assignee: LG Display Co., Ltd.
    Inventors: Je Hyung Park, Tae Yong Jung
  • Patent number: 9617158
    Abstract: Cohesive carbon assemblies are prepared by obtaining a carbon starting material in the form of powder, particles, flakes, or loose agglomerates, dispersing the carbon in a selected organic solvent by mechanical mixing and/or sonication, and substantially removing the organic solvent, typically by evaporation, whereby the cohesive assembly of carbon is formed. The method is suitable for preparing free-standing, monolithic assemblies of carbon nanotubes in the form of films, wafers, or discs, having high carbon packing density and low electrical resistivity. The method is suitable for preparing adherent cohesive carbon assemblies on substrates comprising various materials. The assemblies have various potential applications, such as electrodes or current collectors in electrochemical capacitors, fuel cells, and batteries, or as electromagnetic interference shielding materials.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: April 11, 2017
    Assignee: YAZAKI CORPORATION
    Inventors: Satyabrata Raychaudhuri, Yongan Yan, Leonid Grigorian
  • Patent number: 9620623
    Abstract: When a semiconductor device including a transistor in which a gate electrode layer, a gate insulating film, and an oxide semiconductor film are stacked and a source and drain electrode layers are provided in contact with the oxide semiconductor film is manufactured, after the formation of the gate electrode layer or the source and drain electrode layers by an etching step, a step of removing a residue remaining by the etching step and existing on a surface of the gate electrode layer or a surface of the oxide semiconductor film and in the vicinity of the surface is performed. The surface density of the residue on the surface of the oxide semiconductor film or the gate electrode layer can be 1×1013 atoms/cm2 or lower.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: April 11, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiko Hayakawa, Tatsuya Honda
  • Patent number: 9595319
    Abstract: A novel 2D/3D hierarchical-BL NAND array with at least one plane on independent Psubstrate comprising a plurality of LG groups respectively associated with a plurality of local bit lines (LBLs) laid at a level below a plurality of broken or non-broken global bit lines (GBLs) connected to Page Buffer. Each LG group includes multiple blocks and connects an independent power supply line to each of the plurality of LBLs. Each block including N-bit 2D/3D NAND strings each with S cells connected in series and terminated by two string-select devices and coupled to a common source line. In particular, random-size partial-block WLs are selected from each block of randomly selected LG groups of one plane of the 2D/3D NAND array for erase at the same time with border WLs being optionally preread and program into another plane of the 2D/3D NAND array or optionally saved off-chip and wrote back for data security.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: March 14, 2017
    Inventor: Peter Wung Lee
  • Patent number: 9583509
    Abstract: An object is to improve reliability of a semiconductor device. A semiconductor device including a driver circuit portion and a display portion (also referred to as a pixel portion) over the same substrate is provided. The driver circuit portion and the display portion include thin film transistors in which a semiconductor layer includes an oxide semiconductor; a first wiring; and a second wiring. The thin film transistors each include a source electrode layer and a drain electrode layer. In the thin film transistor in the driver circuit portion, the semiconductor layer is sandwiched between a gate electrode layer and a conductive layer. The first wiring and the second wiring are electrically connected to each other in an opening provided in a gate insulating film through an oxide conductive layer.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: February 28, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichiro Sakata, Masayuki Sakakura, Yoshiaki Oikawa, Kenichi Okazaki, Hotaka Maruyama, Masashi Tsubuku
  • Patent number: 9559127
    Abstract: A thin film transistor array panel includes an insulation substrate; a gate line and a first electrode on the insulation substrate; a gate insulating layer on the gate line and the first electrode; a data line on the gate insulating layer; a passivation layer on the gate insulating layer and the data line; and a second electrode on the passivation layer. Relative permittivity (?) of the gate insulating layer is more than about 15, and a thickness of the gate insulating layer is about 2000 angstroms.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: January 31, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Daisuke Inoue, Mi Suk Kim, Si Heun Kim, Tae Ho Kim, So Youn Park, Keun Chan Oh, Chang-Hun Lee
  • Patent number: 9541809
    Abstract: An array substrate includes a plurality of data lines, a plurality of gamma lines, a repair pad, a repair line, an inspection pad and an inspection line. The data lines transmit a data voltage to an active region. The gamma lines apply a gamma reference voltage to generate the data voltage. The repair pad repairs the data line. The repair line extends from the repair pad. The repair line is disposed adjacent to the gamma line. The inspection pad applies an inspection signal. The inspection line extends from the inspection pad. The inspection line is connected to the data lines. The gamma lines are connected to the inspection line.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: January 10, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yun-Seok Han, Seul-Ki Kim, Seung-Jin Kim, Jeong-Hyun Lee
  • Patent number: 9515135
    Abstract: An edge termination structure for a silicon carbide semiconductor device includes a plurality of spaced apart concentric floating guard rings in a silicon carbide layer that at least partially surround a silicon carbide-based junction, an insulating layer on the floating guard rings, and a silicon carbide surface charge compensation region between the floating guard rings and adjacent the surface of the silicon carbide layer. A silicon nitride layer is on the silicon carbide layer, and an organic protective layer is on the silicon nitride layer. An oxide layer may be between the silicon nitride layer and the surface of the silicon carbide layer. Methods of forming edge termination structures are also disclosed.
    Type: Grant
    Filed: January 12, 2006
    Date of Patent: December 6, 2016
    Assignee: Cree, Inc.
    Inventors: Sei-Hyung Ryu, Anant K. Agarwal, Allan Ward
  • Patent number: 9496403
    Abstract: A circuit including an inverter is provided for a wiring layer. A semiconductor device is provided with a wiring layer circuit which is formed over an insulating film and includes at least one inverter element. The inverter is provided with a first transistor element and a resistance element which is connected to the first transistor via a connection node. The first transistor element is provided with a gate electrode which is embedded in an interlayer insulating film including the insulating film, a gate insulating film which is formed over the interlayer insulating film and the gate electrode, and a first semiconductor layer which is formed over the gate insulating film between a source electrode and a drain electrode. The resistance element is provided with a second semiconductor layer which functions as a resistance. The first semiconductor layer and the second semiconductor layer are formed in the same layer.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: November 15, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kishou Kaneko, Hiroshi Sunamura, Yoshihiro Hayashi
  • Patent number: 9477358
    Abstract: A touch screen panel includes a touch substrate, first sensing electrodes, second sensing electrodes, and outer lines. The touch substrate includes a touch active area and a touch non-active area. The first and second sensing electrodes are disposed in the touch active area and insulated from each other while crossing each other. Each first sensing electrode includes a first sensing metal layer and a first transparent sensing electrode layer. Each second sensing electrode includes a second sensing metal layer and a second transparent sensing electrode layer. Each outer line includes a first outer metal layer, a transparent outer electrode layer, and a second outer metal layer.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: October 25, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Byeong-Jin Lee, Joo-Han Bae, Byeongkyu Jeon, Sungku Kang, Jinhwan Kim, Heewoong Park, Jee-Hun Lim
  • Patent number: 9437819
    Abstract: A donor substrate includes a base layer, a light-to-heat conversion layer disposed on the base layer, a buffer layer disposed on the light-to-heat conversion layer and a transfer layer disposed on the buffer layer. The buffer layer includes a cross-linked polymer, a spacer polymer bonded to the cross-linked polymer, and a perfluoroalkyl alcohol group bonded to the spacer polymer.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: September 6, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: YoungGil Kwon
  • Patent number: 9437746
    Abstract: The present disclosure relates to a thin film transistor substrate with a metal oxide semiconductor layer that has enhanced characteristics and stability. The present disclosure also relates to a method for manufacturing a thin film transistor substrate in which a thermal treatment is conducted for the metal oxide semiconductor layer and the damages to the substrate by the thermal treatment are minimized.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: September 6, 2016
    Assignee: LG Display Co., Ltd.
    Inventors: Kisul Cho, Seongmoh Seo
  • Patent number: 9417521
    Abstract: A method of forming a metal pattern is disclosed. In the method, a metal layer is formed on a base substrate. A photoresist composition is coated on the metal layer to form a coating layer. The photoresist composition includes a binder resin, a photo-sensitizer and a mixed solvent including a first solvent, a second solvent having a higher volatility than the first solvent, and a third solvent having a higher volatility than the second solvent. The coating layer is exposed to light. The coating layer is partially removed to form a photoresist pattern. The metal layer is patterned by using the photoresist pattern as a mask.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: August 16, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ki-Hyun Cho, Hoon Kang, Jae-Sung Kim, Dong-Min Kim, Seung-Ki Kim, Eun Jeagal
  • Patent number: 9373292
    Abstract: An object of the present invention is to provide a small-sized active matrix type liquid crystal display device that may achieve large-sized display, high precision, high resolution and multi-gray scales. According to the present invention, gray scale display is performed by combining time ratio gray scale and voltage gray scale in a liquid crystal display device which performs display in OCB mode. In doing so, one frame is divided into subframes corresponding to the number of bit for the time ratio gray scale. Initialize voltage is applied onto the liquid crystal upon display of a subframe.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: June 21, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Patent number: 9368360
    Abstract: An anti-diffusion layer, a preparation method thereof, a thin-film transistor (TFT), an array substrate and a display device are provided, involve the display device manufacturing field and can resolve problem that a high atmosphere temperature is need in process of preparing a tantalum dioxide anti-diffusion layer by PVD or CVD, which causes the gate electrode to volatilize and affect the performance of a display device. The method for preparing the anti-diffusion layer comprises: placing a conductive base (1) and a cathode (4) in a electrolytic solution (3), taking the conductive base (1) as an anode, and forming a tantalum dioxide anti-diffusion layer on the conductive base (1) after energizing.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: June 14, 2016
    Assignee: BOE TECHNOLOGY GROUP CO., LTD
    Inventors: Chunsheng Jiang, Haijing Chen, Dongfang Wang
  • Patent number: 9343517
    Abstract: A display device includes a pixel portion in which a pixel electrode layer is arranged in a matrix, and an inverted staggered thin film transistor having a combination of at least two kinds of oxide semiconductor layers with different amounts of oxygen is provided corresponding to the pixel electrode layer. In the periphery of the pixel portion in this display device, a pad portion is provided to be electrically connected to a common electrode layer formed on a counter substrate through a conductive layer made of the same material as the pixel electrode layer. One objection of our invention to prevent a defect due to separation of a thin film in various kinds of display devices is realized, by providing a structure suitable for a pad portion provided in a display panel.
    Type: Grant
    Filed: February 3, 2011
    Date of Patent: May 17, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto, Shigeki Komori, Hideki Uochi, Rihito Wada, Yoko Chiba
  • Patent number: 9293599
    Abstract: A transistor with stable electric characteristics is provided. A transistor with small variation in electrical characteristics is provided. A miniaturized transistor is provided. A transistor having low off-state current is provided. A transistor having high on-state current is provided. A semiconductor device including the transistor is provided. One embodiment of the present invention is a semiconductor device including an island-shaped stack including a base insulating film and an oxide semiconductor film over the base insulating film; a protective insulating film facing a side surface of the stack and not facing a top surface of the stack; a first conductive film and a second conductive film which are provided over and in contact with the stack to be apart from each other; an insulating film over the stack, the first conductive film, and the second conductive film; and a third conductive film over the insulating film.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: March 22, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Suguru Hondo, Daigo Ito
  • Patent number: 9224609
    Abstract: A semiconductor device for high power application in which a novel semiconductor material having high mass productivity is provided. An oxide semiconductor film is formed, and then, first heat treatment is performed on the exposed oxide semiconductor film in order to reduce impurities such as moisture or hydrogen in the oxide semiconductor film. Next, in order to further reduce impurities such as moisture or hydrogen in the oxide semiconductor film, oxygen is added to the oxide semiconductor film by an ion implantation method, an ion doping method, or the like, and after that, second heat treatment is performed on the exposed oxide semiconductor film.
    Type: Grant
    Filed: December 1, 2010
    Date of Patent: December 29, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichiro Sakata, Hiroki Ohara
  • Patent number: 9224981
    Abstract: An organic light emitting display apparatus including a thin film encapsulation layer of an improved structure. The organic light emitting display apparatus includes: a display unit formed on a substrate; metal wires formed on an outer portion of the display unit on the substrate; and a thin film encapsulation layer formed by alternately stacking at least one organic layer and at least one inorganic layer on the display unit for sealing the display unit, wherein the at least one organic layer is separated from the metal wires so as not to contact the metal wires. According to the above structure, since the organic layer that is close to the display unit is separated completely from the metal wires formed on an outer portion of the display unit, moisture infiltration to the display unit via the metal wires may be prevented.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: December 29, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventor: Tae-Wook Kang
  • Patent number: 9219173
    Abstract: Solar cells having emitter regions composed of wide bandgap semiconductor material are described. In an example, a method includes forming, in a process tool having a controlled atmosphere, a thin dielectric layer on a surface of a semiconductor substrate of the solar cell. The semiconductor substrate has a bandgap. Without removing the semiconductor substrate from the controlled atmosphere of the process tool, a semiconductor layer is formed on the thin dielectric layer. The semiconductor layer has a bandgap at least approximately 0.2 electron Volts (eV) above the bandgap of the semiconductor substrate.
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: December 22, 2015
    Assignee: SunPower Corporation
    Inventors: Richard M. Swanson, Marius M. Bunea, Michael C. Johnson, David D. Smith, Yu-Chen Shen, Peter J. Cousins, Tim Dennis
  • Patent number: 9207507
    Abstract: The present invention provides a structure of a pixel, which includes an array substrate (10), a color filter substrate (20), and a liquid crystal layer (30) between the array substrate (10) and the color filter substrate (20). The array substrate (10) includes a first substrate (11), a data line (12) and a gate line (13) arranged on the first substrate (11), and a pixel unit (14). The pixel unit (14) includes a thin-film transistor (15) and a pixel electrode (16). The thin-film transistor (15) is electrically connected to the data line (12), the gate line (13), and the pixel electrode (16). The color filter substrate (20) includes a second substrate (21) and a common electrode (22) arranged on the second substrate (21). The common electrode (22) and the pixel electrode (16) have a first overlapping portion (23), which forms a first storage capacitor of the pixel unit (14).
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: December 8, 2015
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Zuomin Liao
  • Patent number: 9196746
    Abstract: A thin film transistor includes a gate electrode on a substrate, a main active layer in electrical connection with the gate electrode and including an exposed channel portion, a source electrode in electrical connection with the main active layer, a drain electrode which is spaced apart from the source electrode and in electrical connection with the main active layer, and a sub active layer in electrical connection to the main active layer.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: November 24, 2015
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hong-Long Ning, Byeong-Beom Kim, Chang-Oh Jeong, Sang-Won Shin, Hyeong-Suk Yoo, Xin-Xing Li, Joon-Yong Park, Hyun-Ju Kang, Su-Kyoung Yang, Kyung-Seop Kim
  • Patent number: 9177855
    Abstract: By using a conductive layer including Cu as a long lead wiring, increase in wiring resistance is suppressed. Further, the conductive layer including Cu is provided in such a manner that it does not overlap with the oxide semiconductor layer in which a channel region of a TFT is formed, and is surrounded by insulating layers including silicon nitride, whereby diffusion of Cu can be prevented; thus, a highly reliable semiconductor device can be manufactured. Specifically, a display device which is one embodiment of a semiconductor device can have high display quality and operate stably even when the size or definition thereof is increased.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: November 3, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Masahiro Takahashi, Hideyuki Kishida, Akiharu Miyanaga, Junpei Sugao, Hideki Uochi, Yasuo Nakamura
  • Patent number: 9147754
    Abstract: In a manufacturing process of a bottom-gate transistor including an oxide semiconductor film, dehydration or dehydrogenation through heat treatment and oxygen doping treatment are performed. A transistor including an oxide semiconductor film subjected to dehydration or dehydrogenation through heat treatment and oxygen doping treatment can be a highly reliable transistor having stable electric characteristics in which the amount of change in threshold voltage of the transistor between before and after the bias-temperature stress (BT) test can be reduced.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: September 29, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9147752
    Abstract: A device with reduced gate resistance includes a gate structure having a first conductive portion and a second conductive portion formed in electrical contact with the first conductive portion and extending laterally beyond the first conductive portion. The gate structure is embedded in a dielectric material and has a gate dielectric on the first conductive portion. A channel layer is provided over the first conductive portion. Source and drain electrodes are formed on opposite end portions of a channel region of the channel layer. Methods for forming a device with reduced gate resistance are also provided.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: September 29, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shu-Jen Han, Alberto Valdes Garcia