Inverted Transistor Structure Patents (Class 438/158)
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Patent number: 8956930Abstract: A TFT substrate 50a that includes a transparent substrate 10 and a plurality of TFTs 5a each arranged on the transparent substrate 10 through a base coat film 9 and each having a semiconductor layer 17a, in which the base coat film 9 includes a resin film 11 formed on the transparent substrate 10, and a region of the resin film 11 that overlaps with each of the semiconductor layers 17a has a light-shielding property.Type: GrantFiled: September 29, 2011Date of Patent: February 17, 2015Assignee: Sharp Kabushiki KaishaInventor: Masahiko Miwa
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Patent number: 8956926Abstract: Disclosed is a method for manufacturing a self-aligned metal oxide thin film transistor. According to the present invention, a metal oxide semiconductor layer having a high carrier concentration is formed, and then a channel region which is self-aligned with a gate electrode is oxidized by a plasma having oxidbillity so that the channel region has a low carrier concentration and the source and drain regions have high carrier concentrations while the resulting transistor has a self-aligned structure. In addition, the threshold voltage of the transistor is controlled by the conditions under which the channel region of the transistor is subsequently oxidized by plasma having oxidbillity at a low temperature. Therefore, the controllability of the characteristics of the transistor is improved significantly, and the manufacturing process is simplified.Type: GrantFiled: June 13, 2011Date of Patent: February 17, 2015Assignee: Peking University Shenzhen Graduate SchoolInventors: Shengdong Zhang, Xin He, Yi Wang, Dedong Han, Jeng Han
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Patent number: 8957415Abstract: A thin film transistor includes: a gate electrode on a substrate; a source electrode; a drain electrode positioned in a same layer as the source electrode and facing the source electrode; an oxide semiconductor layer positioned between the gate electrode and the source electrode or drain electrode; and a gate insulating layer positioned between the gate electrode and the source electrode or drain electrode. The oxide semiconductor layer includes titanium oxide (TiOx) doped with niobium (Nb).Type: GrantFiled: October 30, 2012Date of Patent: February 17, 2015Assignee: Samsung Display Co., Ltd.Inventors: Byung Du Ahn, Jun Hyung Lim, Jin Seong Park
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Patent number: 8951849Abstract: An object is to provide a semiconductor device including a microcrystalline semiconductor film with favorable quality and a method for manufacturing the semiconductor device. In a thin film transistor formed using a microcrystalline semiconductor film, yttria-stabilized zirconia having a fluorite structure is formed in the uppermost layer of a gate insulating film in order to improve quality of a microcrystalline semiconductor film to be formed in the initial stage of deposition. The microcrystalline semiconductor film is deposited on the yttria-stabilized zirconia, so that the microcrystalline semiconductor film around an interface with a base particularly has favorable crystallinity while by crystallinity of the base.Type: GrantFiled: March 17, 2011Date of Patent: February 10, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Toru Takayama, Kengo Akimoto
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Patent number: 8952368Abstract: A thin film transistor, a method of manufacturing the same, and a display device including the same, the thin film transistor including a substrate; a polysilicon semiconductor layer on the substrate; and a metal pattern between the semiconductor layer and the substrate, the metal pattern being insulated from the semiconductor layer, wherein the polysilicon of the semiconductor layer includes a grain boundary parallel to a crystallization growing direction, and a surface roughness of the polysilicon semiconductor layer defined by a distance between a lowest peak and a highest peak in a surface thereof is less than about 15 nm.Type: GrantFiled: May 20, 2013Date of Patent: February 10, 2015Assignee: Samsung Display Co., Ltd.Inventors: Jong-Hyun Park, Chun-Gi You, Sun Park, Jin-Hee Kang, Yul-Kyu Lee
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Publication number: 20150037943Abstract: A method of fabricating a display device includes forming a thin-film transistor including a gate electrode, a source electrode and a drain electrode on a substrate, forming a first insulating layer and a second insulating layer on the thin-film transistor, forming a common electrode on the second insulating layer by depositing a common electrode material on the second insulating layer, plasma-treating a photoresist pattern on the common electrode material, and etching the common electrode material using the plasma-treated photoresist pattern as a mask, defining a contact hole in the second insulating layer which corresponds to the drain electrode using the plasma-treated photoresist pattern and the common electrode as a mask, forming a third insulating layer on the second insulating layer and the common electrode to expose the contact hole and the drain electrode and forming a pixel electrode connected to the drain electrode on the third insulating layer.Type: ApplicationFiled: November 15, 2013Publication date: February 5, 2015Applicant: Samsung Display Co., Ltd.Inventors: Ji Young PARK, Dong Il KIM, Sang Gab KIM
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Publication number: 20150037944Abstract: An object is to reduce a capacitance value of parasitic capacitance without decreasing driving capability of a transistor in a semiconductor device such as an active matrix display device. Further, another object is to provide a semiconductor device in which the capacitance value of the parasitic capacitance was reduced, at low cost. An insulating layer other than a gate insulating layer is provided between a wiring which is formed of the same material layer as a gate electrode of the transistor and a wiring which is formed of the same material layer as a source electrode or a drain electrode.Type: ApplicationFiled: October 16, 2014Publication date: February 5, 2015Inventor: Shunpei YAMAZAKI
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Patent number: 8946712Abstract: A light blocking member having variable transmittance, a display panel including the same, and a manufacturing method thereof. A light blocking member having a variable transmittance according to one exemplary embodiment includes a polymerizable compound, a binder, and a thermochromic material that exhibits a black color at a temperature below a threshold temperature and becomes transparent at a temperature above the threshold temperature.Type: GrantFiled: August 15, 2012Date of Patent: February 3, 2015Assignee: Samsung Display Co., Ltd.Inventors: Byung-Duk Yang, Vladimir Urazaev, Sung-Wook Kang
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Patent number: 8946011Abstract: A manufacturing method of a semiconductor device having a stacked structure in which a lower layer is exposed is provided without increasing the number of masks. A source electrode layer and a drain electrode layer are formed by forming a conductive film to have a two-layer structure, forming an etching mask thereover, etching the conductive film using the etching mask, and performing side-etching on an upper layer of the conductive film in a state where the etching mask is left so that part of a lower layer is exposed. The thus formed source and drain electrode layers and a pixel electrode layer are connected in a portion of the exposed lower layer. In the conductive film, the lower layer and the upper layer may be a Ti layer and an Al layer, respectively. The plurality of openings may be provided in the etching mask.Type: GrantFiled: September 1, 2011Date of Patent: February 3, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hidekazu Miyairi, Takafumi Mizoguchi
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Patent number: 8946070Abstract: Producing a transistor includes providing a substrate including in order a first electrically conductive material layer positioned on the substrate and a first electrically insulating material layer positioned on the first electrically conductive material layer. A gate including a reentrant profile is formed from an electrically conductive material layer stack provided on the first electrically insulating material layer in which a first portion of the gate is sized and positioned to extend beyond a second portion of the gate. The gate including the reentrant profile and at least a portion of the first electrically insulating material layer are conformally coated with a second electrically insulating material layer. The second electrically insulating material layer is conformally coated the with a semiconductor material layer. A source and drain electrodes are formed simultaneously by directionally depositing a second electrically conductive material layer on portions of the semiconductor material layer.Type: GrantFiled: June 19, 2013Date of Patent: February 3, 2015Assignee: Eastman Kodak CompanyInventors: Lee W. Tutt, Shelby F. Nelson
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Patent number: 8946005Abstract: A thin-film transistor includes a semiconductor pattern, source and drain electrodes and a gate electrode, the semiconductor pattern is formed on a base substrate, and the semiconductor pattern includes metal oxide. The source and drain electrodes are formed on the semiconductor pattern such that the source and drain electrodes are spaced apart from each other and an outline of the source and drain electrodes is substantially same as an outline of the semiconductor pattern. The gate electrode is disposed in a region between the source and drain electrodes such that portions of the gate electrode are overlapped with the source and drain electrodes. Therefore, leakage current induced by light is minimized. As a result, characteristics of the thin-film transistor are enhanced, after-image is reduced to enhance display quality, and stability of manufacturing process is enhanced.Type: GrantFiled: February 18, 2011Date of Patent: February 3, 2015Assignee: Samsung Display Co., Ltd.Inventors: Je-Hun Lee, Do-Hyun Kim, Eun-Guk Lee, Chang-Oh Jeong
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Publication number: 20150028340Abstract: Source wires having a semiconductor film thereunder are formed wide within a range that does not overlap pixel electrodes formed later. Thereafter, a resist pattern for use in patterning the pixel electrodes is formed so as to overlap edge portions of the source wires, and etching using the resist pattern as a mask is performed, whereby the pixel electrodes are formed, and in addition, the edge portions of the source wires are removed, whereby a structure in which the semiconductor film has a portion projecting beyond the source wires on both sides is formed.Type: ApplicationFiled: July 21, 2014Publication date: January 29, 2015Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Toshihiko IWASAKA, Makoto HIRAKAWA
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Publication number: 20150028343Abstract: A display panel is discloses. A gate line and a gate connection line of an array substrate are disposed perpendicular to each other. A passivation layer is formed on a side of a source electrode or a drain electrode of the array substrate which is close to the color filter substrate. A first via hole is disposed in the passivation layer. A color filter substrate includes a first substrate, and a data line parallel to the gate connection line is formed on a side of the first substrate which is close to the array substrate. A protection layer, a black matrix and a common electrode are sequentially formed on a side of the data line which is close to the array substrate. A second via hole is disposed in a region of the protection layer, the black matrix and the common electrode which corresponds to the data line.Type: ApplicationFiled: November 27, 2013Publication date: January 29, 2015Inventor: Fan Li
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Publication number: 20150028342Abstract: An array substrate, a manufacturing method thereof and a display device are provided, and the array substrate comprises: a substrate (1); a plurality of data lines (16), formed on the substrate and extending in a first direction; a plurality of gate lines (15), formed on the substrate (1), crossing the plurality of data lines (15), and extending in a second direction perpendicular to the first direction; a plurality of pixel regions, defined by the plurality of gate lines (15) and the plurality of data lines (15) crossing each other and arranged in a matrix form, wherein each of the pixel regions is provided with a thin film transistor and a pixel electrode (12), wherein, the thin film transistor comprises: a gate electrode (2), connected with one of the plurality of gate lines (15); a gate insulating layer (3), provided above the gate line (15) and the gate electrode (2); an active layer (5), formed on the gate insulating layer (3) and disposed corresponding to the gate electrode (2); a drain electrode (8) aType: ApplicationFiled: October 31, 2013Publication date: January 29, 2015Applicant: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Heecheol Kim, Youngsuk Song, Seongyeol Yoo, Seungjin Choi
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Publication number: 20150028420Abstract: The present provides a method for fabricating a thin film transistor including following steps. A substrate is provided. A gate is formed above the substrate. A first source is formed above the substrate. A channel is formed, in which one end of the channel contacts with the first source. A stop layer covering the one end of the channel and exposing another end of the channel is formed. A drain connected with the other end of the channel is formed. Moreover, the present invention also provides a thin film transistor fabricated by the method.Type: ApplicationFiled: September 5, 2013Publication date: January 29, 2015Applicant: Chunghwa Picture Tubes, LTD.Inventors: Yen-Yu Huang, Hsi-Ming Chang
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Publication number: 20150021612Abstract: An array substrate, a display device and a method of producing the array substrate are provided, and the array substrate includes a substrate and a thin film field effect transistor and a data line formed on the substrate, and the thin film field effect transistor includes a gate electrode, an active layer, a source electrode and a drain electrode, a gate insulating layer is formed between the gate electrode and the active layer, and the array substrate includes: a protection layer formed between the gate insulating layer and the data line and being in direct contact with the data line; and the protection layer is provided on the same layer with and has the same material with the active layer.Type: ApplicationFiled: December 3, 2013Publication date: January 22, 2015Inventors: Xiangyang Xu, Lei Du, Sheng Wang
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Patent number: 8937305Abstract: To provide a highly reliable semiconductor device which includes a transistor including an oxide semiconductor, in a semiconductor device including a staggered transistor having a bottom-gate structure provided over a glass substrate, a gate insulating film in which a first gate insulating film and a second gate insulating film, whose compositions are different from each other, are stacked in this order is provided over a gate electrode layer. Alternatively, in a staggered transistor having a bottom-gate structure, a protective insulating film is provided between a glass substrate and a gate electrode layer. A metal element contained in the glass substrate has a concentration lower than or equal to 5×1018 atoms/cm3 at the interface between the first gate insulating film and the second gate insulating film or the interface between the gate electrode layer and a gate insulating film.Type: GrantFiled: October 16, 2012Date of Patent: January 20, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Takayuki Cho, Shunsuke Koshioka, Masatoshi Yokoyama, Shunpei Yamazaki
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Patent number: 8936975Abstract: A touch display comprising a first substrate formed with a common electrode; a second substrate formed with a gate line and a data line, wherein a first thin film transistor and a pixel electrode is provided in a pixel region defined by the gate line and the data line and the pixel region and the common electrode form a liquid crystal capacitor; a touch element provided in the pixel region in the second substrate and used to sense a touch voltage reflecting the change of the liquid crystal capacitance at a touch point; and a touch processing device connected with the touch element and used to obtaining a position coordinates of the touch point according to the touch voltage.Type: GrantFiled: February 11, 2014Date of Patent: January 20, 2015Assignees: Beijing Boe Optoelectronics Technology Co., Ltd., Boe Technology Group Co., Ltd.Inventors: Yinglong Huang, Zheng Wang
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Patent number: 8936952Abstract: An object is to provide a manufacturing method of a semiconductor device in which a defect in characteristics due to a crack occurring in a semiconductor device is reduced. Provision of a crack suppression layer formed of a metal film in the periphery of a semiconductor element makes it possible to suppress a crack occurring from the outer periphery of a substrate and reduce damage to the semiconductor element. In addition, even if the semiconductor device is subjected to physical forces from the outer periphery in separation and transposition steps, progression (growth) of a crack to the semiconductor device can be suppressed by the crack suppression layer.Type: GrantFiled: June 8, 2011Date of Patent: January 20, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Akihiro Chida
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Publication number: 20150014693Abstract: A display substrate is provided. The display substrate includes a switching element disposed on a base substrate, wherein the switching element comprises a gate electrode, an active pattern, a source electrode, and a drain electrode. The display substrate also includes a first electrode disposed on a same layer as the gate electrode, wherein the first electrode includes a wire grid pattern; and a second electrode overlapping the first electrode.Type: ApplicationFiled: March 31, 2014Publication date: January 15, 2015Applicant: Samsung Display Co., LTD.Inventors: Yu-Jin LEE, Jun-Ho SONG, Hwa-Yeul OH, Su-Mi LEE, Yeon-Mun JEON, Young-Je CHO, Tae-Hyung HWANG
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Publication number: 20150017766Abstract: There is provided an electronic device including at least a first electrode, a second electrode disposed to be spaced apart from the first electrode, and an active layer disposed over the second electrode from above the first electrode and formed of an organic semiconductor material. A charge injection layer is formed between the first electrode and the active layer and between the second electrode and the active layer, and the charge injection layer is formed of an organic material having an increased electric conductivity when the charge injection layer is oxidized.Type: ApplicationFiled: July 23, 2014Publication date: January 15, 2015Applicant: Sony CorporationInventor: Mao Katsuhara
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Publication number: 20150014641Abstract: An organic light emitting diode (OLED) display according to the present invention includes a substrate; a driving gate electrode formed on the substrate; and a first gate insulating layer covering the substrate and the driving gate electrode. A semiconductor layer formed on the first gate insulating layer and including a switching semiconductor layer and a driving semiconductor layer separated from each other. A second gate insulating layer disposed covering the semiconductor layer. A switching gate electrode formed on the second gate insulating layer and overlapping the switching semiconductor layer. An interlayer insulating layer is disposed covering the switching gate electrode and the second gate insulating layer, wherein a thickness of the first gate insulating layer is thicker a thickness of the second gate insulating layer.Type: ApplicationFiled: December 16, 2013Publication date: January 15, 2015Applicant: Samsung Display Co., Ltd.Inventors: Jin-Goo JUNG, Chung Yl
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Patent number: 8932917Abstract: A manufacturing method of a thin film transistor (TFT) includes forming a gate electrode including a metal that can be combined with silicon to form silicide on a substrate and forming a gate insulation layer by supplying a gas which includes silicon to the gate electrode at a temperature below about 280° C. The method further includes forming a semiconductor on the gate insulation layer, forming a data line and a drain electrode on the semiconductor and forming a pixel electrode connected to the drain electrode.Type: GrantFiled: July 12, 2013Date of Patent: January 13, 2015Assignee: Samsung Display Co., Ltd.Inventors: Byoung-June Kim, Jae-Ho Choi, Chang-Oh Jeong, Sung-Hoon Yang, Je-Hun Lee, Do-Hyun Kim, Hwa-Yeul Oh, Yong-Mo Choi
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Publication number: 20150009446Abstract: A liquid crystal display panel and a method of manufacturing the same are proposed. A bottom electrode of an electrode used as a storage capacitor is disposed between a scan line and a voltage controlling line. A first conducting area and a second conducting area of another electrode used as the storage capacitor are formed by a transparent conducting layer. Because the storage capacitor is formed between the scan line and the voltage controlling line, a second sub-pixel electrode has larger layout space. The aperture ratio of the second sub-pixel electrode is increased accordingly.Type: ApplicationFiled: March 27, 2012Publication date: January 8, 2015Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd.Inventors: Jiali Jiang, Peng Du, Shihchyn Lin
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Publication number: 20150011055Abstract: A manufacturing method of an LTPS-TFT array substrate is provided. The exemplary method comprises a step of sequentially forming a poly-silicon layer and a data-line-metal layer on a base substrate, and performing a patterning process by using a third mask to simultaneously form an active layer and source and drain electrodes, the active layer being provided on the gate insulating layer and corresponding to the gate electrode, and the source and drain electrodes being provided on the active layer.Type: ApplicationFiled: September 24, 2014Publication date: January 8, 2015Inventor: Zhanjie MA
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Publication number: 20150008434Abstract: A thin film transistor array panel includes a first insulating substrate, a gate electrode positioned on the first insulating substrate, a gate insulating layer positioned on the gate electrode, a semiconductor layer positioned on the gate insulating layer, and a source electrode and a drain electrode positioned on the semiconductor layer and spaced apart from each other, in which the semiconductor layer includes three or more amorphous silicon layers having different bandgap energies from one another in order to reduce a leakage current and improve performance of a liquid crystal display.Type: ApplicationFiled: December 10, 2013Publication date: January 8, 2015Applicant: Samsung Display Co., Ltd.Inventors: Sung Hoon Yang, Hyeong Suk Yoo, Hae Yoon Jung, Jong-Chul Park, Jong Hyun Park, Jang-Ki Baek, Eun-Chan Lim
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Publication number: 20150009441Abstract: The present invention proposes an LCD panel. Conducting traces traversing a scan line and a voltage controlling line are made of a transparent conducting layer which are used for first and second sub-pixel electrodes, rather than a second metallic layer for data lines. Compared with the conventional technology in which the transparent conducting layer is separated from the second metallic layer used as the data lines by the insulating layer, the transparent conducting layer is separated from the first metallic layer used as the scan lines by the insulating layer and the passivation layer in the present invention. Since the parasitic capacitances across the conducting traces and the scan lines or the voltage controlling lines are lower, RC delay is reduced.Type: ApplicationFiled: March 23, 2012Publication date: January 8, 2015Applicant: Shenzhen China Star Optoelectronics Technology Co. Ltd.Inventors: Jiali Jiang, Peng Du, Shihchyn Lin
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Publication number: 20150011054Abstract: An array structure, which includes a TFT, a passivation layer, a pixel electrode, a first connecting layer and a first spacer is provided. The TFT includes a gate, a source and a drain. The passivation layer overlays the TFT. The pixel electrode is located on the passivation layer. The first connecting layer is located on the pixel electrode and electrically connected to the pixel electrode and the drain. The first spacer is located on the first connecting layer.Type: ApplicationFiled: September 23, 2014Publication date: January 8, 2015Inventors: Yu-Cheng Chen, Chih-Hung Lin, Yi-Hui Li
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Patent number: 8927981Abstract: The drain voltage of a transistor is determined depending on the driving voltage of an element connected to the transistor. With downsizing of a transistor, intensity of the electric field concentrated in the drain region is increased, and hot carriers are easily generated. An object is to provide a transistor in which the electric field hardly concentrates in the drain region. Another object is to provide a display device including such a transistor. End portions of first and second wiring layers having high electrical conductivity do not overlap with a gate electrode layer, whereby concentration of an electric field in the vicinity of a first electrode layer and a second electrode layer is reduced; thus, generation of hot carriers is suppressed. In addition, one of the first and second electrode layers having higher resistivity than the first and second wiring layers is used as a drain electrode layer.Type: GrantFiled: March 17, 2010Date of Patent: January 6, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kengo Akimoto, Hiromichi Godo, Akiharu Miyanaga
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Publication number: 20150001543Abstract: An array substrate includes: a trench having a depth from a surface of a substrate; a gate line, a gate electrode and a data pattern filling the respective trenches, wherein the data pattern is between the adjacent gate lines; a gate insulating layer on the gate line, the gate electrode and the data pattern, substantially flat over the substrate, and including contact holes that expose both ends of the data pattern, respectively; a data connection portion on the gate insulating layer and contacting the adjacent data patterns through the contact holes; a source electrode extending from the data connection portion, and a drain electrode spaced apart from the source electrode; a passivation layer on the source and drain electrodes and including a drain contact hole exposing the drain electrode; and a pixel electrode on the passivation layer and contacting the drain electrode through the drain contact hole.Type: ApplicationFiled: December 4, 2013Publication date: January 1, 2015Applicant: LG DISPLAY CO., LTD.Inventors: Tae-Hyoung MOON, Tae-Joon SONG, Kyu-Hwang LEE, Kyung-Ha LEE
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Publication number: 20150004760Abstract: A method of manufacturing a liquid crystal display having a touch sensor, the method including forming a plurality of thin film transistors on a first substrate, forming a plurality of pixel electrodes each coupled to a corresponding one of the thin film transistors, forming an insulating layer on the pixel electrodes, and forming, on the insulating layer, a plurality of first touch electrodes each having openings formed therein and a plurality of driving lines coupled to the first touch electrodes.Type: ApplicationFiled: November 13, 2013Publication date: January 1, 2015Applicant: SAMSUNG DISPLAY CO., LTD.Inventors: Hyun-Young Kim, Ji-Ryun Park, Se-Il Cho, Ki-Hoon Kim, Jung-Sun Kim, Hee-Sang Park
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Patent number: 8921850Abstract: A thin film transistor (TFT), a method for fabricating a TFT, an array substrate for a display device having a TFT, and a method for fabricating the same are provided. An oxide thin film transistor (TFT) includes: a gate electrode formed on a substrate; a gate insulating layer formed on the gate electrode; an active layer formed on the gate insulating layer above the gate electrode; an etch stop layer pattern formed on the active layer; a source alignment element and a drain alignment element formed on the etch stop layer pattern and spaced apart from one another; and a source electrode in contact with the source alignment element and the active layer and a drain electrode in contact with the drain alignment element and the active layer.Type: GrantFiled: December 27, 2012Date of Patent: December 30, 2014Assignee: LG Display Co., Ltd.Inventor: SangHee Yu
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Patent number: 8916870Abstract: It is an object to provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a semiconductor device including an inverted staggered thin film transistor whose semiconductor layer is an oxide semiconductor layer, a buffer layer is provided over the oxide semiconductor layer. The buffer layer is in contact with a channel formation region of the semiconductor layer and source and drain electrode layers. A film of the buffer layer has resistance distribution. A region provided over the channel formation region of the semiconductor layer has lower electrical conductivity than the channel formation region of the semiconductor layer, and a region in contact with the source and drain electrode layers has higher electrical conductivity than the channel formation region of the semiconductor layer.Type: GrantFiled: June 16, 2014Date of Patent: December 23, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Junichiro Sakata, Takuya Hirohashi, Hideyuki Kishida
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Patent number: 8916865Abstract: An object is to provide a semiconductor device including an oxide semiconductor, which has stable electric characteristics and high reliability. In a transistor including an oxide semiconductor film, the oxide semiconductor film is subjected to dehydration or dehydrogenation performed by heat treatment. In addition, as a gate insulating film in contact with the oxide semiconductor film, an insulating film containing oxygen, preferably, a gate insulating film including a region containing oxygen with a higher proportion than the stoichiometric composition is used. Thus, oxygen is supplied from the gate insulating film to the oxide semiconductor film. Further, a metal oxide film is used as part of the gate insulating film, whereby reincorporation of an impurity such as hydrogen or water into the oxide semiconductor is suppressed.Type: GrantFiled: June 7, 2011Date of Patent: December 23, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Patent number: 8912080Abstract: The semiconductor device is manufactured through the following steps: after first heat treatment is performed on an oxide semiconductor film, the oxide semiconductor film is processed to form an oxide semiconductor layer; immediately after that, side walls of the oxide semiconductor layer are covered with an insulating oxide; and in second heat treatment, the side surfaces of the oxide semiconductor layer are prevented from being exposed to a vacuum and defects (oxygen deficiency) in the oxide semiconductor layer are reduced.Type: GrantFiled: January 9, 2012Date of Patent: December 16, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Patent number: 8912538Abstract: Embodiments of the present invention provide a thin film transistor array substrate, a method for manufacturing the same, a display panel and a display device. The method for manufacturing the thin film transistor array substrate comprises: sequentially depositing a first metal oxide layer, a second metal oxide layer and a source and drain metal layer, conductivity of the first metal oxide layer being smaller than conductivity of the second metal oxide layer; patterning the first metal oxide layer, the second metal oxide layer and the source and drain metal layer, so as to form an active layer, a buffer layer, a source electrode and a drain electrode, respectively. According to technical solutions of the embodiments of the invention, it is possible that the manufacturing process of the metal oxide TFT array substrate is simplified, and the production cost of products is reduced.Type: GrantFiled: December 17, 2012Date of Patent: December 16, 2014Assignee: Boe Technology Group Co., Ltd.Inventors: Xiang Liu, Woobong Lee
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Patent number: 8912040Abstract: An object is to establish a processing technique in manufacture of a semiconductor device in which an oxide semiconductor is used. A gate electrode is formed over a substrate, a gate insulating layer is formed over the gate electrode, an oxide semiconductor layer is formed over the gate insulating layer, the oxide semiconductor layer is processed by wet etching to form an island-shaped oxide semiconductor layer, a conductive layer is formed to cover the island-shaped oxide semiconductor layer, the conductive layer is processed by dry etching to form a source electrode, and a drain electrode and part of the island-shaped oxide semiconductor layer is removed by dry etching to form a recessed portion in the island-shaped oxide semiconductor layer.Type: GrantFiled: January 25, 2011Date of Patent: December 16, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hideomi Suzawa, Shinya Sasagawa, Taiga Muraoka
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Publication number: 20140363934Abstract: Embodiments disclosed herein relate to a TFT and methods for manufacture thereof. Specifically, the embodiments herein relate to methods for forming a semiconductor layer at a low temperature for use in a TFT. The semiconductor layer may be formed by depositing a nitride or oxynitride layer, such as zinc nitride or oxynitride, and then converting the nitride layer into an oxynitride layer with a different oxygen content. The oxynitride layer is formed by exposing the deposited nitride layer to a wet atmosphere at a temperature between about 85 degrees Celsius and about 150 degrees Celsius. The exposure temperature is lower than the typical deposition temperature used for forming the oxynitride layer directly or annealing, which may be performed at temperatures of about 400 degrees Celsius.Type: ApplicationFiled: December 17, 2012Publication date: December 11, 2014Applicant: APPLIED MATERIALS, INC.Inventor: Yan Ye
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Patent number: 8906739Abstract: A method includes: a step of forming a gate electrode (14) on a substrate (10a); a step of forming a gate insulating film (15) to cover the gate electrode (14), and then forming an In-Ga-Zn-O-based oxide semiconductor layer (16) in which a ratio of In:Ga:Zn in atomic % is 1:1:1 or 4:5:1 on the gate insulating film (15) to overlap the gate electrode (14); a step of forming a source electrode (19a) and a drain electrode (19b) on the oxide semiconductor layer (16) to overlap the gate electrode (14) and to face each other; and a step of performing an annealing process in an atmosphere containing steam (S) on the substrate (10a) provided with the source electrode (19a) and the drain electrode (19b).Type: GrantFiled: February 9, 2011Date of Patent: December 9, 2014Assignee: Sharp Kabushiki KaishaInventors: Yoshifumi Ohta, Yoshimasa Chikama, Masahiko Suzuki, Okifumi Nakagawa, Yoshiyuki Harumoto
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Patent number: 8906756Abstract: An object is to provide a semiconductor device including an oxide semiconductor, which has stable electrical characteristics and high reliability. In a manufacturing process of a bottom-gate transistor including an oxide semiconductor layer, heat treatment in an atmosphere containing oxygen and heat treatment in vacuum are sequentially performed for dehydration or dehydrogenation of the oxide semiconductor layer. In addition, irradiation with light having a short wavelength is performed concurrently with the heat treatment, whereby elimination of hydrogen, OH, or the like is promoted. A transistor including an oxide semiconductor layer on which dehydration or dehydrogenation treatment is performed through such heat treatment has improved stability, so that variation in electrical characteristics of the transistor due to light irradiation or a bias-temperature stress (BT) test is suppressed.Type: GrantFiled: May 18, 2011Date of Patent: December 9, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Ryosuke Watanabe, Suzunosuke Hiraishi, Junichiro Sakata
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Publication number: 20140353661Abstract: A thin film transistor (TFT) array substrate is disclosed. The TFT array substrate includes a gate line, a first gate electrode branched from the gate line, a gate insulating film formed over the substrate, an active layer formed on the gate insulating film, a data line formed to comprise a plurality of metal layers including a first metal layer and a second metal layer formed of copper (Cu), a source electrode formed on the gate insulating film to comprise the remaining metal layer excluding the second metal layer among the plurality of the metal layers, and a drain electrode formed on the gate insulating film to comprise the remaining metal layer excluding the second metal layer among the plurality of the metal layers.Type: ApplicationFiled: December 17, 2013Publication date: December 4, 2014Applicant: LG DISPLAY CO., LTD.Inventors: Hyun-Sik SEO, Jong-Woo KIM, Chung-Ho LEE
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Publication number: 20140353750Abstract: A carbon-based semiconductor structure includes a substrate and a gate stack. The gate stack includes a carbon-based gate electrode formed on the substrate. The gate stack also includes a gate dielectric formed on the carbon-based gate electrode. The gate stack further includes a carbon-based channel formed on the gate dielectric.Type: ApplicationFiled: May 30, 2013Publication date: December 4, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Damon FARMER
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Publication number: 20140353754Abstract: A carbon-based semiconductor structure includes a substrate and a gate stack. The gate stack includes a carbon-based gate electrode formed on the substrate. The gate stack also includes a gate dielectric formed on the carbon-based gate electrode. The gate stack further includes a carbon-based channel formed on the gate dielectric.Type: ApplicationFiled: September 19, 2013Publication date: December 4, 2014Applicant: International Business Machines CorporationInventor: Damon FARMER
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Publication number: 20140353589Abstract: A self-aligned carbon nanostructure transistor is formed by a method that includes providing a material stack including a gate dielectric material having a dielectric constant of greater than silicon oxide and a sacrificial gate material. Next, a carbon nanostructure is formed on an exposed surface of the gate dielectric material. After forming the carbon nanostructure, metal semiconductor alloy portions are formed self-aligned to the material stack. The sacrificial gate material is then replaced with a conductive metal.Type: ApplicationFiled: June 4, 2013Publication date: December 4, 2014Inventors: Qing Cao, Zhengwen Li, Fei Liu, Zhen Zhang
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Publication number: 20140353659Abstract: A method of manufacturing a flat panel display device includes forming a first gate electrode and a second gate electrode on a substrate. The method includes forming a gate insulating layer on the substrate covering the gate electrodes. The method includes forming a first active layer and a second active layer on the gate insulating layer. The method includes forming an active insulation layer on the gate insulating layer to cover the first active layer. The active insulation layer includes a first hole and a second hole exposing portions of the first active layer. The method includes forming a first source electrode and a first drain electrode on the active insulation layer respectively filling the first hole and the second hole. The method includes forming a second source electrode and a second drain electrode to contact portions of the second active layer.Type: ApplicationFiled: October 22, 2013Publication date: December 4, 2014Applicant: SAMSUNG DISPLAY CO., LTD.Inventor: SANG IL PARK
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Patent number: 8901658Abstract: A thin film transistor (TFT) is provided, which includes a gate, a semiconductor layer, an insulation layer, a source and a drain. The semiconductor layer has a first end and a second end opposite to the first end. The insulation layer is disposed between the gate and the semiconductor layer. The source clamps the first end of the semiconductor layer and the drain clamps the second end of the semiconductor layer.Type: GrantFiled: December 4, 2012Date of Patent: December 2, 2014Assignee: E Ink Holdings Inc.Inventors: Henry Wang, Chia-Chun Yeh, Xue-Hung Tsai, Ted-Hong Shinn
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Patent number: 8900938Abstract: A manufacturing method of the array substrate includes the steps: A. A first mask manufacturing process is adopted to from scan lines and thin film transistor (TFT) gates on a surface of a substrate. B. A second mask manufacturing process is adopted to form scan lines and data lines of the array substrate, a source electrode and a drain electrode of TFT and a conducting channel positioned between the source electrode and the drain electrode. C. A photoresistor formed in the second mask manufacturing process is incinerated, and then, an a-Si film is paved on the surface of the array substrate. D. The photoresistor is stripped to form an undoped active layer. E. A third mask manufacturing process is adopted to form a transparent conducting layer on the surface of the drain electrode of the TFT. Only three mask manufacturing process in the present disclosure are needed to manufacture the entire array substrate.Type: GrantFiled: July 12, 2012Date of Patent: December 2, 2014Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.Inventor: Jun Wang
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Patent number: 8901587Abstract: A display panel apparatus includes a substrate and an organic electro-luminescence unit that includes an array. The array is above the substrate and includes a red, a green, and a blue pixel. A glass layer is above the organic electro-luminescence unit. A resin layer is between the glass layer and the organic electro-luminescence unit. A surface of the resin layer that is on a side toward the organic electro-luminescence unit includes concaves. Each of the concaves is concaved toward the glass layer and corresponds to one of the pixels. Lens resins are each in one of the concaves and include a surface that is substantially coplanar with the surface of the resin layer. A refractive index of the lens resin in the concave that corresponds to the blue pixel is greater than a refractive index of the lens resin in the concave that corresponds to the red pixel.Type: GrantFiled: May 21, 2012Date of Patent: December 2, 2014Assignee: Panasonic CorporationInventor: Takashi Ohta
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Patent number: 8895375Abstract: Provided is a novel structure of a field effect transistor using a metal-semiconductor junction. The field effect transistor includes a wiring which is provided over a substrate and also functions as a gate electrode; an insulating film which is provided over the wiring, has substantially the same shape as the wiring, and also functions as a gate insulating film; a semiconductor layer which is provided over the insulating film and includes an oxide semiconductor and the like; an oxide insulating layer which is provided over the semiconductor layer and whose thickness is 5 times or more as large as the sum of the thickness of the insulating film and the thickness of the semiconductor layer or 100 nm or more; and wirings which are connected to the semiconductor layer through openings provided in the oxide insulating layer.Type: GrantFiled: May 24, 2011Date of Patent: November 25, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Yasuhiko Takemura
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Patent number: 8895376Abstract: A thin film transistor includes: an insulating layer; a gate electrode provided on the insulating layer; a gate insulating film provided on the gate electrode; a semiconductor layer provided on the gate insulating film, the semiconductor layer being formed of oxide; source and drain electrodes provided on the semiconductor layer; and a channel protecting layer provided between the source and drain electrodes and the semiconductor layer. The source electrode is opposed to one end of the gate electrode. The drain electrode is opposed to another end of the gate electrode. The another end is opposite to the one end. The drain electrode is apart from the source electrode. The channel protecting layer covers at least a part of a side face of a part of the semiconductor layer. The part of the semiconductor layer is not covered with the source and drain electrodes above the gate electrode.Type: GrantFiled: January 27, 2014Date of Patent: November 25, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Nobuyoshi Saito, Tomomasa Ueda, Shintaro Nakano, Shuichi Uchikoga